JP2002231955A - Display and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display where polycrystalline silicon thin film transistors different in crystal grain or mobility exist mixedly in the display picture element region and the circuit region. SOLUTION: This is a display which has a display picture element region and a circuit region on a substrate, and first film transistors in each of which the source region, the channel formation region, and the drain region consist of first polycrystalline silicon films and second thin film transistors in each of which the source region, the channel formation region, and the drain region consists of second polycrystalline silicon films are made mixedly at least in either the above display picture element region or the circuit region, and for the above second polycrystalline silicon film, the average grain diameter of the crystals positioned at the outermost surface is larger than the average grain diameter of the crystals positioned at the outermost surface of the above first polycrystalline silicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a technique effective when applied to a display device having a circuit including a thin film transistor.

[0002]

BACKGROUND OF THE INVENTION thin film transistor (t hin f ilm t ransist
or; hereinafter, referred to as TFT. The liquid crystal display device of the TFT type having a pixel switching element and a peripheral circuit of a display pixel region using a polycrystalline silicon TFT is disclosed in, for example, JP-A-64-2088. It has been disclosed. In the liquid crystal display device of the TFT type with a built-in circuit, if the mobility of the TFT is improved in order to improve the performance of the circuit, there are problems such as deterioration of withstand voltage of the TFT for pixel switching and increase of leak current. For example, JP-A-2-27320 and JP-A-2-208635 disclose devices having different crystallinities and performances between the TFTs constituting the circuit and the TFTs. In these devices, when crystallizing amorphous silicon by laser annealing,
By selectively irradiating laser light only to the circuit part,
A polycrystalline silicon TFT is formed in a circuit portion, and an amorphous silicon TFT is formed in a pixel portion. Further, as disclosed in, for example, JP-A-5-190853 and JP-A-5-203977, a structure in which the polycrystalline silicon TFT in the pixel portion is inferior in crystallinity to the polycrystalline silicon TFT in the circuit portion. I was

[0003]

SUMMARY OF THE INVENTION T for pixel switching
The FT is an amorphous silicon TFT or a polycrystalline silicon TFT with poor crystallinity, and the circuit is made of polycrystalline silicon with good crystallinity. In the above-described conventional technology, the effect of improving the breakdown voltage of the pixel switching TFT and reducing the leak current is obtained. However, there is a problem that the withstand voltage of the pixel portion peripheral circuit TFT is deteriorated and the reliability is deteriorated due to electric stress. Further, in a display device with a pixel function in which each pixel has a function such as a memory device, there is a problem that sufficient TFT performance required for these functions cannot be obtained. The present invention has been made in order to solve the problems of the prior art, and an object of the present invention is to provide a display pixel region and a circuit region in which polycrystalline silicon thin film transistors having different crystal grain sizes and mobilities are mixed. To provide a display device. Another object of the present invention is to manufacture a display device capable of easily manufacturing a display device in which a polycrystalline silicon thin film transistor having a different crystal grain size and mobility is mixed in a display pixel region and a circuit region. It is to provide a method. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0004]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention is a display device having a display pixel region and a circuit region on a substrate, wherein at least one of the display pixel region and the circuit region includes a source region, a channel formation region, and a drain region. A first thin film transistor comprising a polycrystalline silicon film of
A plurality of second thin film transistors, each of which has a source region, a channel formation region, and a drain region formed of a second polycrystalline silicon film, are formed in a mixed manner, and the second polycrystalline silicon film is formed of a crystal located at the outermost surface. Is larger than the average grain size of the crystal located on the outermost surface of the first polycrystalline silicon film.

Further, the present invention is a display device having a display pixel region and a circuit region on a substrate, wherein at least one of the display pixel region and the circuit region has a first field-effect transistor, And the first field-effect transistor is a first thin-film transistor having a channel region made of a first polycrystalline silicon film, and the second field-effect transistor The type transistor is a second thin film transistor having a channel region formed of a second polycrystalline silicon film, and the first thin film transistor has a mobility of the channel region of the second thin film transistor which is higher than a mobility of the channel region of the second thin film transistor. It is characterized by being smaller.

In a preferred embodiment of the present invention, the display pixel region includes a pixel transistor, and the pixel transistor is constituted by the first thin film transistor. In a preferred embodiment of the present invention,
The circuit region includes a signal line selection switch circuit, a buffer circuit, and a shift register circuit, and at least one of the circuits is configured by the first thin film transistor. In a preferred embodiment of the present invention, the first thin film transistor has a withstand voltage higher than that of the second thin film transistor having the same size. In a preferred embodiment of the present invention, the first
The thin film transistor of the present invention is characterized in that the leak current is smaller than the leak current of the second thin film transistor having the same size. In a preferred embodiment of the present invention, the first
The characteristic degradation life of the thin film transistor when an electrical stress is applied is longer than the characteristic degradation life of the same dimension when the same electrical stress is applied to the second thin film transistor.

The present invention also relates to a method of manufacturing a display device having a display pixel region and a circuit region on a substrate, wherein an adjustment film for adjusting the irradiation energy of a laser beam is selectively formed on the substrate. A step of depositing an amorphous silicon film on the substrate, and a step of laser annealing,
The amorphous silicon film is crystallized, and at least one of the display pixel region and the circuit region has a first polycrystalline silicon film and an average grain size of the crystal located on the outermost surface is the same as that of the first polycrystalline silicon film. Forming a mixture with a second polycrystalline silicon film larger than the average grain size of crystals located on the surface.

According to the present invention, a high performance polycrystalline silicon TFT for a data processing circuit (hereinafter, referred to as a circuit TFT).
And high performance polycrystalline silicon TFTs for each pixel function
This is referred to as a pixel function TFT. ), Etc., the crystal grain size of a high performance polycrystalline silicon TFT requiring high performance can be increased, and the crystal defect density can be reduced. Therefore, the mobility of the TFT is improved, so that the performance of the data processing circuit and the pixel function circuit can be improved, and power consumption can be reduced by reducing the power supply voltage. Also, a high withstand voltage low leak polycrystalline silicon TFT (hereinafter, referred to as a pixel TFT) for pixel switching, a pixel TFT, or the like.
The crystal defect density is appropriately increased by making the crystal grain size of a high-breakdown-voltage polycrystalline silicon TFT (hereinafter referred to as a high-breakdown-voltage TFT) for a direct peripheral circuit for driving a semiconductor device smaller than that of a high-performance polycrystalline silicon TFT. However, since the mobility can be appropriately reduced, it is possible to suppress the breakdown voltage, the reliability, and the leak current from increasing by suppressing the parasitic bipolar operation and reducing the ionization rate in the high electric field region of the junction. Further, according to the manufacturing method of the present invention, the polycrystalline silicon films having different crystal grain sizes and mobilities can be formed in the same crystallization step by laser annealing. It is not necessary to perform crystallization by the laser annealing step. Therefore, it is possible to form polycrystalline silicon films having different crystal grain sizes and mobilities on the same substrate by a simple method.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. [First Embodiment] FIG. 1 is a schematic sectional view showing a schematic structure of a TFT type liquid crystal display device with a built-in circuit according to a first embodiment of the present invention. FIG. 2 is a schematic plan view illustrating a schematic configuration of a liquid crystal display device of a TFT type with a built-in circuit according to the present embodiment.
FIG. 1 is a cross-sectional view of a polycrystalline silicon TFT in a region where a high-breakdown-voltage TFT 12 and a circuit TFT 13 mixed in a circuit region around a pixel portion shown in FIG. As shown in FIGS. 1 and 2, each pixel is arranged in a matrix in the display pixel region 1, and the area of the display region is approximately 14 cm in diagonal length. Each pixel has an area of approximately 85 μm square, and has a total of 131 dots in the horizontal direction and 1280 dots in the vertical direction.
Ten thousand pieces are arranged. Each pixel 5 is provided with three n-type channel pixel TFTs 11 each having a gate length of about 2 μm for red display, green display, and blue display for color display. This n-type channel pixel TFT 11
Provided on the glass substrate 10. FIG. 2 shows one pixel 5 in an enlarged manner as an example, and is represented by an equivalent circuit.

In FIG. 2, for red display of each pixel 5,
Pixel electrodes for green display and blue display (not shown) are connected to two adjacent scan electrode lines (gate signal lines or horizontal signal lines).
It is arranged in an intersecting region (a region surrounded by four signal lines) between the signal signal line 21 and two adjacent signal electrode lines (drain signal lines or vertical signal lines) 20. The drain region of each column of each pixel TFT 11 arranged in a matrix is connected to a signal electrode line 20, and the source region of each pixel TFT 11 arranged in a matrix is connected to a pixel electrode. Each pixel TFT1 arranged in a matrix
The gate electrode of each row is connected to the scanning electrode line 21. In addition, pixel electrode and counter electrode (common electrode)
Since a liquid crystal layer is provided between the pixel electrodes, a liquid crystal capacitor 22 is connected to each pixel electrode in an equal manner. In addition, the storage capacity 23
Is connected between the pixel electrode and the storage capacitor line 24, and the storage capacitor line 24 is applied to the counter electrode (Vco
m) is applied.

A sampling switch for driving the pixel TFT 11 is provided in a pixel peripheral area 2 of the display pixel area 1.
A signal electrode line drive circuit such as a buffer circuit and a shift register, and a scan electrode line drive circuit such as a buffer circuit and a shift register are formed in the pixel peripheral region 3 by high-voltage TFTs 12 each having a gate length of about 1 μm. ing. These circuits are composed of complementary MOS circuits (hereinafter, CMs) comprising both n-type channel TFTs and p-type channel TFTs.
It is called an OS circuit. ), One for driving the liquid crystal.
It is driven by a high power supply voltage of 0 V or more. Therefore, a high voltage of 10 V or more is applied to the pixel TFT 11 and the high breakdown voltage TFT 12. A circuit TFT 13 having a gate length of about 1 μm is arranged in a circuit area 4 such as an arithmetic circuit for processing image data and a frame memory. The circuit in the circuit area 4 is also a CMOS circuit, but is driven at a low voltage of about 5 V necessary for calculation and memory, so that the voltage applied to the circuit TFT 13 is as low as about 5 V.

FIG. 3 shows a pixel peripheral region (2, 2) shown in FIG.
It is a block diagram which shows an example of a circuit structure of 3). The signal electrode lines 20 shown in FIG. 2 are connected to the analog signal input lines 136 via the signal electrode line selection switch circuits 133, respectively. The signal electrode line selection switch circuit 133 receives a shift pulse for capturing a video signal from the signal electrode line shift register circuit 131 via the signal electrode line buffer circuit 132, and the signal electrode line selection switch circuit 133 Scanning is performed by the electrode line shift register circuit 131. The signal electrode line shift register circuit 131 receives the signal electrode line driving clock signals (φD, φD (inv.)) And the start pulse (DX) from the signal electrode line clock waveform shaping circuit 130 and receives these clocks. Based on the signal, the signal electrode line shift register circuit 131 performs a shift operation, and outputs a shift pulse for capturing a video signal. Note that a video signal is input to the analog signal input line 136. Signal electrode line clock waveform shaping circuit 1
The horizontal drive clock signal (CLX) is input to 30, and the signal electrode line clock waveform shaping circuit 130 shapes the waveform of the horizontal drive clock signal (CLX) to obtain a signal electrode line drive clock signal (φD). , ΦD (inv.)).

The scanning electrode line 21 shown in FIG. 2 is connected to a scanning electrode line shift register circuit 141 via a scanning electrode line buffer circuit 142. The scan electrode line shift register circuit 141 supplies the scan electrode line drive clock signals (φG, φG
(inv.)) and a start pulse (DY) are input, and based on these clock signals, the scan electrode line shift register circuit 141 performs a shift operation to generate a scan shift pulse for scanning the scan electrode line 21. Output. The scanning electrode line clock waveform shaping circuit 140 receives a vertical drive clock signal (CLY), and the scan electrode line clock waveform shaping circuit 140 outputs the vertical drive clock signal (CL
Y) is shaped and the scan electrode line driving clock signals (φG, φG (inv.)) Are output. Although each circuit shown in FIG. 3 is driven by a voltage of 10 V or more as described above, the scan electrode line buffer circuit 142 and the signal electrode line buffer circuit 132 are constituted by the high-breakdown-voltage TFTs 12, and these circuits are used. Is supplied with a voltage of 10 V or more as a power supply voltage, and other circuits (the signal electrode line clock waveform shaping circuit 130,
The scan electrode line clock waveform shaping circuit 140, the signal electrode line shift register circuit 131, and the scan electrode line shift register circuit 141) are configured by the circuit TFT 13, and supply a voltage of 5 V as a power supply voltage to these circuits. Is also good.

In the liquid crystal display device of a TFT type with a built-in circuit according to the present embodiment, the transmission of light from a light source is controlled by a liquid crystal layer driven by a pixel TFT 11 to display a color image on a display screen. FIG. 1 shows a cross-sectional structure of both n-type channel polycrystalline silicon TFTs in a region where the pixel peripheral region 2 and the circuit region 4 in FIG. 2 are adjacent to each other. In addition,
Although a p-type channel polycrystalline silicon TFT is not shown in this figure, the conductivity type of the source / drain impurity diffusion layers is opposite to that of the n-type channel polycrystalline silicon TFT, and the n-type channel polycrystalline silicon TFT is not shown. The structure is the same as that of the n-channel polycrystalline silicon TFT except that there is no low-concentration n-type impurity diffusion layer (hereinafter, referred to as an LDD diffusion layer) for reducing the electric field at the junction provided only in the silicon TFT. is there. These TFTs are MOS field-effect transistors and have a polycrystalline silicon film 30 on a glass substrate 10.
And 31, a gate oxide film 32, gate electrodes 33 and 34, source diffusion layers 35 and 37 formed inside polycrystalline silicon films (30, 31), and drain diffusion layers 36 and 38. .

Among them, the crystal grain size of the polycrystalline silicon film 30 of the high breakdown voltage TFT 12 is as small as about 0.1 μm or less.
The mobility is around 50 cm ² / Vs. Pixel TFT 11
The crystal grain size and mobility of are also not shown, but are the same.
For this reason, the drain current of the high-breakdown-voltage TFT 12 and the pixel TFT 11 is lower than that of the circuit TFT 13, and the current amplification factor of the parasitic npn bipolar transistor formed by the source, channel, and drain is low. It has a sufficiently high withstand voltage and a sufficiently long life for electrical stress (hereinafter, referred to as reliability).
On the other hand, the circuit TFT 13 has a large crystal grain size of the polycrystalline silicon film 31 of about 1.0 μm and a mobility of 300 c.
It has high performance of about m ² / Vs or more.
For this reason, even if the power supply voltage is reduced to about 5 V, sufficient performance required for circuit operation can be obtained, and at the same time, sufficient reliability and low power consumption can be realized. In this case, the high breakdown voltage TFT
The characteristic deterioration life when the same electrical stress is applied to the circuit TFTs 13 of the same size is longer than the characteristic deterioration life when the electric stress is applied to the pixel TFT 11 and the pixel TFT 11.

The crystal grain size of the polycrystalline silicon films (30, 31) was measured according to the following procedure. (A) A measurement target region is determined in a surface region of a polycrystalline silicon film of a thin film transistor to be measured. here,
Since the size of the crystal grains is substantially uniform in the polycrystalline silicon film of the thin film transistor to be measured, the measurement target region may be a region where at least one crystal grain to be measured is contained, that is, , A source region, a channel region, and a drain region. The size (that is, the area) of the measurement target region may be any size as long as at least one crystal grain to be measured fits in the measurement target region. (B) Take an electron micrograph of the surface of this measurement target area. (C) A crystal grain which is entirely contained in the measurement target area of the electron micrograph, that is, a crystal grain which is entirely contained in the outermost surface of the measurement target area is regarded as a measurement target crystal grain, and the number thereof is counted. Further, the total area of the crystal grains to be measured, that is, the total area of the crystal grains to be measured at the outermost surface of the measurement target area is measured from the electron micrograph. (D) The average area S of the crystal grains to be measured is obtained by dividing the total area of the crystal grains to be measured by the number of the crystal grains to be measured. (E) Assuming that the shape of the crystal grain to be measured on the outermost surface of the measurement target area is a circle, S is substituted into an expression consisting of 2 (S / π) ^1/2 to determine the diameter of the crystal grain. The size of the crystal grains is
Since the crystal grain size is almost uniform in the polycrystalline silicon film of the thin film transistor to be measured, the number of measurement of the crystal grain size according to the above-mentioned procedures (a) to (e) may be one, but It may be performed several times.

In this embodiment, it can be said that the crystal defect density of the polycrystalline silicon film 31 in the channel region of the circuit TFT 13 is lower than the crystal defect density of the polycrystalline silicon film 30 in the channel region of the high breakdown voltage TFT 12. .
The size of the crystal defect density of the polycrystalline silicon film (30, 31) can be measured by the following method. Generally, the polycrystalline silicon film (30, 31) has a high crystal defect density, that is,
If the crystallinity is poor, the level density existing at the grain boundary increases, so that the crystallinity can be evaluated by measuring the level density. At the product stage, Levinson has proposed a method for electrically measuring the level density of grain boundaries inside thin film transistors.
Method is well known (J. of Applied Physics, 53 (2), F
eb., 1982, p1193). This Levinson method, source-gate voltage (V _G) drain current (I _D) were measured, level density from the equation of a thin film transistor (N _t)
Ask for.

[Number 1] _{I D ≒ (W / L)} C ox μ b exp {-q 3 N t 2 t / [8εkTC ox (V G -V th)]} (V G -V th) V D ··· (1) By transforming the equation (1), the following equation (2) is obtained.

[Number 2] _{ln [I D / (V G} -V th)] = [- q 3 N t 2 t / (8εkTC ox)] / (V G -V th) + ln [(W / L) C ox μ _{b V D] ················· (2)} ln linear region of the thin film transistor [I _D / (V _G -
V _th )] and 1 / (V _G −V _th ), and the level density (N _t ) can be obtained from equation (2). Incidentally, the above-mentioned (1) and (2), W is the gate width, L is a gate length, C _ox is the gate capacitance, mu _b grain boundary mobility, q is the electron charge, t is the polycrystalline silicon film Film thickness, ε
The dielectric constant of silicon, k is the Boltzmann constant, T is the absolute temperature, V _th is the threshold voltage, V _D is a source-drain voltage.

In the liquid crystal display device of the present embodiment, T
The FT forming process will be described with reference to FIGS. First, as shown in FIG. 4, on a glass substrate 10, a silicon oxide film is deposited and thermal conductivity varies silicon nitride film 39 with a film thickness of about about 50nm by plasma CVD (C hemical V apor D eposition) After a silicon oxide film is deposited thereon by plasma CVD to a thickness of about 100 nm, the silicon oxide film (the laser of the present invention) is selectively formed in the pixel peripheral regions (2, 3) and the display pixel region 1. An adjustment film 40 for adjusting the irradiation energy of the beam is left. Further, an amorphous silicon film 41 is formed thereon.
The amorphous silicon film was deposited by a plasma CVD method to a thickness of about 50 nm, and the amorphous silicon film was crystallized to form a polycrystalline silicon film by scanning a laser beam in an excimer laser annealing step. The irradiation energy of the laser beam was adjusted to an appropriate energy so that a large grain polycrystalline silicon film having a grain size of about 0.5 μm or more was obtained in the circuit region 4 from which the silicon oxide film 40 was removed. At this time, in the pixel peripheral region (2, 3) and the display pixel region 1, the thermal conductivity of the silicon oxide film 40 is lower than that of the silicon nitride film 39, so that the irradiation energy is higher than appropriate laser energy and the particle size is smaller. A polycrystalline silicon film having a small grain size of 0.1 μm or less was obtained.

FIG. 7 shows the irradiation energy of the laser beam,
4 is a graph showing a relationship between crystal grain sizes of a polycrystalline silicon film. In the graph of FIG. 7, the curve A shows the characteristics when the silicon oxide film 40 is formed as the base film, and the curve B shows the characteristics when the silicon nitride film 39 is formed as the base film. Therefore, when the irradiation energy of the laser beam is the energy indicated by the dotted line D,
In the region where the silicon nitride film 39 is formed as the base film (that is, the circuit region 4 from which the silicon oxide film 40 is removed), the characteristics of the curve B indicate that the particle size is about 0.5 μm or larger. In the region where the polycrystalline silicon film is formed and the silicon oxide film 40 is formed as a base film (that is, the pixel peripheral regions (2, 3) and the display pixel region 1), the particle diameter is 0.1 μm due to the characteristic of the curve A. The following small grain polycrystalline silicon film is obtained.

Next, as shown in FIG. 5, a high-breakdown-voltage TFT and a small-grain polycrystalline silicon film 30 for a pixel TFT and a circuit T are formed by lithography and silicon etching techniques.
After patterning the large grain polycrystalline silicon film 31 for FT, a gate oxide film 32 composed of a silicon oxide film is formed.
The film was deposited to a thickness of about 50 to 100 nm by a plasma CVD method. Next, as shown in FIG. 6, for example, a metal film containing molybdenum as a base material was deposited to a thickness of about 100 to 200 nm, and patterning and processing were performed to form gate electrodes 33 and 34. At this time, the high breakdown voltage TFT
12, the gate length of the circuit TFT 13 was about 1 μm, and the gate length of the pixel TFT was about 2 μm. Thereafter, using this gate electrode as a mask, polycrystalline silicon films 30 and 31 are formed.
Then, an impurity is introduced into the LDD diffusion layer (42, 4) by performing a heat treatment at 600 ° C. or less to activate the impurity.
3) A source diffusion layer (35, 37) and a drain diffusion layer (36, 38) were formed.

The LDD diffusion layers (42, 43),
The source diffusion layers (35, 37) and the drain diffusion layers (36, 38) are formed by a method of selectively implanting impurity ions using a resist mask or a method of selectively introducing impurities by a self-alignment process. It is possible to form. Further, the processing gate length is not limited to the value of the present embodiment, and it goes without saying that a desired value can be set according to the circuit specifications. Next, as shown in FIG. 1, an interlayer insulating film 50 composed of a silicon oxide film is deposited to a thickness of about 500 nm by a plasma CVD method, a contact hole is opened, and aluminum is used as a main material. The high voltage TFT 12, the circuit TFT 13, and the pixel TF (not shown) are provided.
T completed. These electrodes (33, 34, 51)
It was also used as wiring for forming a circuit. afterwards,
The TFT substrate was completed by providing an interlayer film, a transparent pixel electrode, and the like.

In this embodiment, since the crystal grain size of the polycrystalline silicon film of the circuit TFT 13 is as large as about 1.0 μm or more and the crystal defect density can be reduced, the mobility of the TFT is about 300 cm ² / Vs. By further increasing the gate length to about 1 μm, the performance of the data processing circuit and the like can be improved, and the power consumption can be reduced by reducing the power supply voltage to 5V. On the other hand, the crystal grain size of the polycrystalline silicon film of the high-breakdown-voltage TFT 12 and the pixel TFT is set to 0.1 μm or less, the crystal defect density is appropriately increased, and the mobility is 50 cm
^{Since the} voltage was reduced to about ² / Vs, sufficient withstand voltage and high reliability were obtained even at a power supply voltage of 10 V or more, and a leak current was reduced. Furthermore, according to the manufacturing method of the present invention, since the above-described polycrystalline silicon films having different crystal grain sizes and mobilities are formed in the same crystallization step by laser annealing, the energy of laser light can be changed depending on the region, It is not necessary to perform crystallization by two laser annealing steps. Moreover, the silicon oxide film 4 laid under the silicon film
Since a polycrystalline silicon film having a different crystal grain size is separately formed by patterning of 0, a high-breakdown-voltage TFT and a circuit TFT having different crystal grain sizes and mobilities are complicatedly integrated and integrated. Even when only a specific TFT has a different crystal grain size from the surrounding TFTs, it can be formed on the same substrate by a simple method.

In the present embodiment, the silicon oxide film 40 is selectively left in the pixel peripheral area (2, 3) and the display pixel area 1, and the silicon oxide film 40 in the circuit area 4 is selectively removed. As a result, polycrystalline silicon films having different crystal grain sizes were separately formed. Alternatively, conversely, on the contrary, the silicon oxide film 40 is selectively left in the circuit region 4 and the irradiation energy of the laser beam is changed to a large grain polycrystalline silicon film having a grain diameter of about 1.0 μm or more. In addition, if the energy is adjusted appropriately, the pixel peripheral area 2 and the display pixel area 1
In this case, since the thermal conductivity of the silicon nitride film 39 is higher than that of the silicon oxide film 40, the irradiation energy is lower than appropriate laser energy, and a small-grain polycrystalline silicon film having a grain size of about 0.1 μm is obtained. In this way, it is possible to separately produce polycrystalline silicon films having different crystal grain sizes. That is,
In the graph of FIG. 7, when the irradiation energy of the laser beam is the energy indicated by the dotted line C, in the region where the silicon oxide film 40 is formed as the base film (that is, the circuit region 4), the characteristic of the curve A indicates , Particle size is 1.0 μm
A polycrystalline silicon film having a large grain size of about or more, and a region where the silicon nitride film 39 is formed as a base film (that is, a pixel peripheral region (2, 2) where the silicon oxide film 40 is removed)
In 3) and the display pixel region 1), a small grain polycrystalline silicon film having a grain size of 0.1 μm or less is obtained due to the characteristics of the curve B.

As a film to be selectively patterned, a silicon nitride film 39 is selectively left in a desired region.
It is also possible to deposit a silicon oxide film 40 over the entire surface and perform laser annealing to separately produce polycrystalline silicon films having different crystal grain sizes. In the present embodiment, the circuit T
Both the n-channel TFT and the p-channel TFT of the FT are made of a large grain polycrystalline silicon film and have a high breakdown voltage TFT.
Although the n-type channel TFT and the p-type channel TFT are made of polycrystalline silicon films so as to be made of small-grained polycrystalline silicon films, various types are made according to specifications required for circuits. Can be handled. For example, the n-channel TFT of the CMOS circuit can be made of a small grain polycrystalline silicon film, and the p-channel TFT can be made of a large grain polycrystalline silicon film.

Further, as a more complicated case, the high withstand voltage T
The FT n-type channel TFT is made of a polycrystalline silicon film having a small grain size.
The FT n-type and p-type channel TFTs can be separately formed so as to be composed of a large grain polycrystalline silicon film.
In this case, the silicon oxide film 40 is selectively left only in the n-type channel TFT regions of the pixel TFT and the high breakdown voltage TFT,
By selectively removing the silicon oxide film 40 in the p-type channel TFT region and the circuit TFT region of the high-breakdown-voltage TFT and performing crystallization by laser annealing, it is possible to form polycrystalline silicon films having different crystal grain sizes. Can be achieved in the area. Further, in this embodiment, a liquid crystal display device is taken as an example of the display device. However, the present invention can be applied to a TFT organic EL display device with a built-in circuit using an organic EL material instead of liquid crystal.

[Embodiment 2] A TFT forming process in a liquid crystal display device of a TFT type with a built-in circuit according to Embodiment 2 of the present invention will be described with reference to FIGS. In addition,
8 to 11 are process cross-sectional views illustrating a TFT forming process of both n-type channel polycrystalline silicon TFTs in a region where the pixel peripheral region 2 and the circuit region 4 shown in FIG. 2 are adjacent to each other. Although a p-type channel polysilicon TFT is not shown in this figure, the conductivity type of the source / drain impurity diffusion layers is opposite to that of the n-type channel polysilicon TFT. Channel polycrystalline silicon T
The structure is the same as that of the n-channel polycrystalline silicon TFT, except that there is no LDD diffusion layer provided only in the FT. First, as shown in FIG. 8, an amorphous silicon film 61 is deposited on a glass substrate 60 by a plasma CVD method so as to have a thickness of about 50 nm, and is selectively formed in the pixel peripheral regions (2, 3) and the display pixel region 1. The amorphous silicon film (adjustment film for adjusting the irradiation energy of the laser beam of the present invention) 61 was left.

Further, an amorphous silicon film 62 was deposited thereon to a thickness of about 50 nm by a plasma CVD method. As a result, the total thickness of the amorphous silicon film in the pixel peripheral region (2, 3) and the display pixel region 1 is about 100 nm. Next, the amorphous silicon film was crystallized by scanning a laser beam in an excimer laser annealing step to form a polycrystalline silicon film. The irradiation energy of the laser beam is set to an appropriate value so that the amorphous silicon film 62 becomes a large-diameter polycrystalline silicon film having a grain size of about 0.5 μm or more in the circuit region 4 where the thickness of the amorphous silicon film 62 is about 50 nm. Adjusted to energy. At this time, in the pixel peripheral area (2, 3) and the display pixel area 1, the total thickness of the amorphous silicon film is about 10
Since the thickness was as large as about 0 nm, the irradiation energy was less than the appropriate laser energy, and a polycrystalline silicon film having a small grain diameter of about 0.1 μm was obtained.

That is, the relationship between the irradiation energy of the laser beam and the crystal grain size of the polycrystalline silicon film is such that the curve A in the graph of FIG.
When the thickness of the amorphous silicon film is large, the characteristic becomes a curve B in the graph of FIG. Therefore, when the irradiation energy of the laser beam is the energy indicated by the dotted line C, in the region where the thickness of the amorphous silicon film is small (that is, the circuit region 4), the particle diameter is 0.5 μm due to the characteristic of the curve A. In a region where the amorphous silicon film has a large film thickness (that is, a pixel peripheral region (2, 3) and a display pixel region 1) having a grain size of about or larger than that of the polycrystalline silicon film, 0.1 μm diameter
The following small grain polycrystalline silicon film is obtained.

Next, as shown in FIG. 9, a high-breakdown-voltage TFT and a small-grain polycrystalline silicon film 63 for a pixel TFT are formed by lithography and silicon etching techniques.
After patterning the large grain polycrystalline silicon film 64 for FT, a gate oxide film 65 composed of a silicon oxide film was deposited to a thickness of about 50 to 100 nm by a plasma CVD method. Next, as shown in FIG. 10, for example, a metal film containing molybdenum as a base material was deposited to a thickness of about 100 to 200 nm, and patterning and processing were performed to form gate electrodes 70 and 71. At this time, the high breakdown voltage TFT
And the gate length of the circuit TFT should be around 1 μm, and the pixel TFT
Has a gate length of about 2 μm. Thereafter, impurities are introduced into polycrystalline silicon films 63 and 64 using the gate electrode as a mask, and a heat treatment at 600 ° C. or lower is performed to activate the impurities, thereby forming LDD diffusion layers (80, 81) and source diffusion layers. (72, 74) and the drain diffusion layer (7
3,75).

The LDD diffusion layer, source diffusion layer, and drain diffusion layer are formed by a method of selectively implanting impurity ions using a resist mask or a method of selectively introducing impurities by a self-alignment process. It is possible. Next, as shown in FIG. 11, an interlayer insulating film 85 composed of a silicon oxide film is deposited to a thickness of about 500 nm by a plasma CVD method, a contact hole is opened, and aluminum is used as a main material. Electrode 86
To complete the high breakdown voltage TFT 90, the circuit TFT 91, and the pixel TFT (not shown). These electrodes (70, 71, 86) were also used as wiring for forming a circuit. After that, an interlayer film, a transparent pixel electrode and the like were provided to complete a TFT substrate.

In the present embodiment, since the crystal grain size of the polycrystalline silicon film of the circuit TFT 91 is as large as about 0.5 μm or more and the crystal defect density can be reduced, the mobility of the TFT becomes 200 cm ² / Vs or more. Improved, gate length 1μ
By setting the value to about m, it was possible to achieve higher performance of the data processing circuit and the like and lower power by reducing the power supply voltage to 5V. On the other hand, a high breakdown voltage TFT 90 or a pixel TFT
The crystal grain size of the polycrystalline silicon film is set to about 0.1 μm,
Moderately increasing the crystal defect density and increasing the mobility to 50 cm ² / Vs
Since the power supply voltage has been lowered, a sufficient withstand voltage and high reliability can be obtained even at a power supply voltage of 10 V or more, and a leak current can be reduced. Further, according to the manufacturing method of the present invention, since the polycrystalline silicon films having different crystal grain sizes and mobilities are formed in the same crystallization step by laser annealing, the energy of the laser light is changed depending on the region, Or crystallization by the laser annealing step. Moreover, by patterning the amorphous silicon film 61, a polycrystalline silicon film having a different crystal grain size can be separately formed.
Even when T and the circuit TFT are integrated in a complicated manner, they can be formed on the same substrate by a simple method.

In the present embodiment, the amorphous silicon film 61 in the pixel peripheral region (2, 3) and the display pixel region 1 is selectively left, and the amorphous silicon film 61 in the circuit region 4 is selectively removed. As a result, polycrystalline silicon films having different crystal grain sizes were separately formed. As another method, on the contrary, the amorphous silicon film 61 is selectively left in the circuit region 4 and the irradiation energy of the laser beam is changed to a large grain polycrystalline silicon film having a grain size of about 0.5 μm or more. If the energy is adjusted to a proper value, the total thickness of the amorphous silicon film in the pixel peripheral region 2 and the display pixel region 1 is small, and the irradiation energy is higher than the proper laser energy. The following small grain polycrystalline silicon film is obtained. In this way, it is possible to separately produce polycrystalline silicon films having different crystal grain sizes. That is, in the graph of FIG. 7, when the irradiation energy of the laser beam is the energy indicated by the dotted line D, the region where the thickness of the amorphous silicon film is small (that is, the pixel peripheral region (2, 3) and the display pixel region) In 1), curve A
In the region where the thickness of the amorphous silicon film is large (that is, the circuit region 4), the characteristic of the curve B
The resulting polycrystalline silicon film has a large grain size of about 0.5 μm or more.

[Embodiment 3] FIG. 12 is a schematic plan view showing a schematic structure of a TFT type liquid crystal display device with a built-in circuit according to Embodiment 3 of the present invention. The liquid crystal display device of the present embodiment is the same as the liquid crystal display device of the first or second embodiment described above.
This is a liquid crystal display device of a TFT type with a built-in circuit to which FT is applied. As shown in FIG. 12, in the display pixel area 101, each pixel is arranged in a matrix. Note that FIG. 12 shows one pixel 105 in an enlarged manner as an example, and each pixel is provided on the glass substrate 100. The area of the display pixel region 101 has a diagonal length of about 10 cm. Each pixel has an area of approximately 65 μm
□, 1280 horizontal dots and 1024 vertical dots, for a total of 1.31 million dots. Each pixel 105 is composed of a pixel for red display, a pixel for green display, and a pixel for blue display for color display, and includes a pixel TFT region 106 and a pixel circuit region 107, respectively.

In the pixel TFT region 106, a plurality of pixel TFTs having a gate length of about 2 μm for driving liquid crystal are provided. In the pixel circuit region 107, an n-type channel pixel function having a gate length of about 1 μm and a p-type channel pixel function for adding functions such as memory and data processing and improving a display function corresponding to a moving image. TFT
And a pixel circuit composed of both. The pixel peripheral area 102 of the display pixel area 101 includes a pixel TFT
A signal electrode line driving circuit such as a sampling switch, a buffer circuit, and a shift register for driving the pixel electrode, and a scanning electrode line driving circuit such as a buffer circuit and a shift register in the pixel peripheral region 103 have a gate length of one.
It is formed of a high breakdown voltage TFT of about μm. These circuits are CMOS circuits, and are used to drive the liquid crystal.
It is driven by a high power supply voltage of about V. Therefore,
A high voltage of about 10 V is applied to the pixel TFT and the high breakdown voltage TFT. A circuit area 104 such as an arithmetic circuit for processing image data or a frame memory has a gate length of one.
A circuit TFT of about μm is arranged. Circuit area 10
Circuit 4 is also a CMOS circuit, but is driven by a low voltage of 5 V or less, which is necessary for computation and memory.
The voltage applied to T is as low as 5 V or less.

A substrate on which TFTs formed in this embodiment are arranged in a matrix is used as a color liquid crystal display device. Signal electrode lines 110 and scanning electrode lines 111 are formed in a matrix on a glass substrate 100, and pixel TFTs and pixel circuits are connected near intersections thereof. By controlling the reflection of light from an external light source and an auxiliary light source provided in the liquid crystal display device using a liquid crystal layer controlled and voltage-driven by a pixel circuit and a pixel TFT, a TFT-driven color liquid crystal display device is configured. You. In the present embodiment, the crystal grain size of the polycrystalline silicon film of the circuit TFT of the circuit region 104 and the pixel function TFT of the pixel circuit region 107 is set to 0.5 to 1 by the method of the first or second embodiment. .
Since the crystal defect density was reduced by increasing the thickness to about 0 μm or more, the mobility of the TFT was 200 to 300 cm ² / V.
s or more.

That is, as described in the first embodiment, the underlying silicon oxide film 40 is selectively left in the region of the circuit TFT in the circuit region 104 and the region of the pixel function TFT in the pixel circuit region 107. Alternatively, Embodiment 2 described above
As described above, the amorphous silicon film 61 is selectively left in the circuit TFT region of the circuit region 104 and the pixel function TFT region of the pixel circuit region 107. Thereafter, an amorphous silicon film was deposited and crystallized by laser annealing. As described above, the mobility of the circuit TFT and the pixel function TFT is improved, and the gate length is set to about 1 μm, thereby improving the performance of the data processing circuit and the like, and reducing the power consumption by reducing the power supply voltage to 5 V or less. , And a function can be added to the pixel. On the other hand, the high-breakdown-voltage TFTs in the pixel peripheral regions (102, 103) and the polycrystalline silicon film of the pixel TFT have a crystal grain size of about 0.1 μm, the crystal defect density is appropriately increased, and the mobility is about 50 cm ² / Vs. As a result, sufficient withstand voltage and high reliability were obtained even at a power supply voltage of about 10 V, and a leak current was reduced. Although a liquid crystal display device is taken as an example of a display device in this embodiment mode, the present invention can be applied to a TFT organic EL display device with a built-in circuit using an organic EL material instead of liquid crystal. Needless to say.

[Fourth Embodiment] FIG. 13 is a schematic plan view showing a schematic structure of a TFT type liquid crystal display device with a built-in circuit according to a fourth embodiment of the present invention. The liquid crystal display device of the present embodiment is the same as the liquid crystal display device of the first or second embodiment described above.
This is a TFT type liquid crystal display device with a built-in high function circuit to which FT is applied. As shown in FIG. 13, in the display pixel region 121, pixels having an area of approximately 50 μm square are arranged in a matrix of 1600 dots in a horizontal direction and 1200 dots in a vertical direction, for a total of 1.92 million pixels. Each of the pixels is connected to the glass substrate 12.
0, and the display area has a diagonal length of approximately 1
0 cm. The display pixel region 121 includes a pixel TFT having a gate length of about 1 μm for driving liquid crystal, and an n-type channel pixel function having a gate length of about 1 μm for adding functions such as memory and data processing to each pixel. TFT and p
A pixel circuit composed of both the type channel pixel function TFTs is provided. In the pixel peripheral area 122, the pixel T
Signal electrode line driving circuits such as a sampling switch, a buffer circuit, and a shift register for driving the FT, and scanning electrode line driving circuits such as a buffer circuit and a shift register in the pixel peripheral region 123 have respective gate lengths. It is formed of a high breakdown voltage TFT of about 1 μm. These circuits are CMOS circuits, and are driven by a high power supply voltage of about 10 V to drive the liquid crystal. Therefore, a high voltage of about 10 V is applied to the pixel TFT and the high breakdown voltage TFT.

A circuit region 124 in which a signal electrode line driving circuit, an arithmetic circuit for processing image data, a frame memory, and the like are integrated has a high withstand voltage T having a gate length of about 1 μm.
An FT and a circuit TFT having a gate length of about 0.5 μm are arranged in a mixed manner. The circuit in the circuit region 124 is also a CMOS circuit, but the voltage applied to the circuit TFT is a low voltage of about 3 to 5V. Further, in this embodiment, in order to add a high function to the display device, the microprocessor unit 125 and the large-capacity memory unit 12 which perform high-speed operations are provided.
6. Communication unit 127 for data communication with the outside,
A light amount control unit 128 for controlling the amount of auxiliary light source of the display device by sensing the amount of external light is also provided. The CMOS circuit constituting these units has a gate length of 0.5
The circuit size of the TFT is about 0.5 μm, and the bipolar transistor that constitutes the light sensor of the light quantity control unit, the low noise amplifier and the gain control amplifier of the communication unit, etc. also has a crystal grain size of 0.5 to 1 μm. It was formed of a polycrystalline silicon film having a thickness of about 0.0 μm or more. In a circuit requiring a high withstand voltage, such as a power amplifier constituting a part of the communication unit 127, a high withstand voltage TFT formed of a polycrystalline silicon film having a crystal grain size of about 0.1 μm is used. Applied.

As described above, the high performance TFT and the high breakdown voltage T
By making FTs differently, it became possible to cope with various circuit specifications, and a TFT-driven color liquid crystal display device with a built-in circuit to which a high function was added was constructed. In the present embodiment, these high-functional units are configured by TFTs. However, similar high functionality can be obtained even if a part is configured by an LSI and mounted on the glass substrate 120. Although a liquid crystal display device is taken as an example of a display device in the present embodiment, a TFT with a built-in circuit using an organic EL material instead of a liquid crystal.
It goes without saying that the present invention can be implemented in a display device. As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Of course, it is.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, the display pixel region and the circuit region
It is possible to provide a display device in which polycrystalline silicon thin film transistors having different crystal grain sizes and mobilities are mixed. (2) According to the present invention, the display pixel region and the circuit region
A display device in which polycrystalline silicon thin film transistors having different crystal grain sizes and mobilities are mixed can be easily manufactured. (3) According to the present invention, since it is possible to cope with various circuit specifications, it is possible to provide a display device incorporating a high-performance circuit.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a schematic structure of a liquid crystal display device of a TFT type with a built-in circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view illustrating a schematic configuration of a liquid crystal display device of a TFT type with a built-in circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel peripheral area shown in FIG. 2;

FIG. 4 is a diagram for explaining a TFT forming process in the liquid crystal display device of the TFT type with a built-in circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram for explaining a TFT forming process in the liquid crystal display device of the TFT type with a built-in circuit according to the first embodiment of the present invention.

FIG. 6 is a diagram for explaining a TFT forming process in the liquid crystal display device of the TFT type with a built-in circuit according to the first embodiment of the present invention.

FIG. 7 is a graph showing the relationship between the irradiation energy of a laser beam and the crystal grain size of a polycrystalline silicon film.

FIG. 8 is a view for explaining a TFT forming process in the liquid crystal display device of the TFT type with a built-in circuit according to the second embodiment of the present invention.

FIG. 9 is a diagram for explaining a TFT forming process in the circuit-integrated TFT type liquid crystal display device according to the second embodiment of the present invention.

FIG. 10 is a view for explaining a TFT forming process in the liquid crystal display device of the TFT type with a built-in circuit according to the second embodiment of the present invention.

FIG. 11 is a diagram for explaining a TFT forming process in the circuit-integrated TFT type liquid crystal display device according to the second embodiment of the present invention.

FIG. 12 is a schematic plan view illustrating a schematic configuration of a liquid crystal display device of a TFT type with a built-in circuit according to a third embodiment of the present invention.

FIG. 13 is a schematic plan view illustrating a schematic configuration of a liquid crystal display device of a TFT type with a built-in circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

1, 101, 121 ... display pixel area, 2, 3, 102,
103, 122, 123... Pixel peripheral area, 4, 104,
124: circuit area, 5,105: pixel, 10, 60, 1
00, 120: glass substrate, 11: high withstand voltage, low leakage polycrystalline silicon thin film transistor (pixel TFT) for pixel switching, 12, 90: high withstand voltage polycrystalline silicon thin film transistor (high withstand voltage TFT), 13, 91: high performance polycrystalline silicon Thin film transistor (circuit TFT), 20, 11
0: signal electrode line, 21, 111: scanning electrode line, 22: liquid crystal capacity, 23: storage capacity, 24: storage capacity line, 30, 3
1, 63, 64: polycrystalline silicon film, 32, 65: gate oxide film, 33, 34, 70, 71: gate electrode, 3
5, 37, 72, 74: source diffusion layer, 36, 38, 7
3, 75: drain diffusion layer, 39: silicon nitride film, 4
0: silicon oxide film, 41, 61, 62: amorphous silicon film, 42, 43, 80, 81: low-concentration n-type impurity diffusion layer (LDD diffusion layer) for electric field relaxation, 50, 85: interlayer insulating film, 51, 86 ... electrode, 106 ... pixel TFT area, 107 ... pixel circuit area, 125 ... microprocessor unit, 126 ... large capacity memory unit, 127 ...
Communication unit, 128: light amount control unit, 130: signal electrode line clock waveform shaping circuit, 131: signal electrode line shift register circuit, 132: signal electrode line buffer circuit,
133: signal electrode line selection switch circuit, 136: analog signal input line, 140: scan electrode line clock waveform shaping circuit, 141: scan electrode line shift register circuit, 142 ...
Scan electrode line buffer circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8238 H01L 29/78 612B 5G435 27/092 27/08 321C 27/08 331 321N 21/336 29 / 78 618Z 627G (72) Inventor Osamu Okura 3300 Hayano, Mobara City, Chiba Prefecture Within Hitachi, Ltd. Display Group (72) Inventor Naohiro Kamo 7-1-1, Omikamachi, Hitachi City, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research, Ltd. In-house F-term (reference) 2H092 GA59 JA24 KA02 MA30 NA22 5C094 AA13 AA22 AA25 AA43 AA48 AA53 BA03 BA27 BA43 CA19 DA09 DA13 DB01 DB04 EA04 EA10 EB02 FA01 FA02 FB12 FB14 FB15 GB10 5F048 AA05 AB03AC BD10 BF02 5F052 AA02 BB07 CA04 CA09 DA02 DB03 EA11 HA01 JA04 5F110 BB02 BB04 CC02 DD02 DD13 DD14 DD17 EE04 FF02 FF30 GG02 GG13 GG16 GG25 GG28 GG45 HJ13 HJ23 HL03 HM15 NN04 NN23 NN78 PP03 PP05 5G435 AA16 AA17 BB05 BB12 CC09 EE37 HH12 HH13 HH14 KK05

Claims (5)

[Claims] 1. A display device having a display pixel region and a circuit region on a substrate, wherein at least one of the display pixel region and the circuit region includes a source region, a channel formation region, and a drain region. A plurality of first thin film transistors formed of a polycrystalline silicon film, and a plurality of second thin film transistors formed of a source region, a channel forming region, and a drain region formed of a second polycrystalline silicon film are mixedly formed; The display device, wherein the polycrystalline silicon film has an average grain size of a crystal located on the outermost surface larger than an average grain size of a crystal located on the outermost surface of the first polycrystalline silicon film. 2. A display device having a display pixel region and a circuit region on a substrate, wherein at least one of the display pixel region and the circuit region has a first field-effect transistor and a second field-effect transistor. A plurality of transistors are mixedly formed, wherein the first field-effect transistor is a first thin-film transistor in which a channel region is formed of a first polycrystalline silicon film; A second thin film transistor in which a channel region is formed of a second polycrystalline silicon film; wherein the first thin film transistor has a mobility of the channel region smaller than a mobility of the channel region of the second thin film transistor. Characteristic display device. 3. The display device according to claim 2, wherein the display pixel region includes a pixel transistor, and the pixel transistor is configured by the first thin film transistor. 4. The circuit area includes a signal line selection switch circuit, a buffer circuit, and a shift register circuit, and at least one of the circuits is configured by the first thin film transistor. Item 3. The display device according to Item 2. 5. A method of manufacturing a display device having a display pixel region and a circuit region on a substrate, wherein: a step of selectively forming an adjustment film for adjusting irradiation energy of a laser beam on the substrate; Depositing an amorphous silicon film on the substrate; and crystallizing the amorphous silicon film by laser annealing to form a first polycrystalline silicon film and a crystal located on the outermost surface in at least one of a display pixel region and a circuit region. Forming a mixture with a second polycrystalline silicon film having an average particle size larger than the average particle size of the crystals located on the outermost surface of the first polycrystalline silicon film. A method for manufacturing a display device.