JP5682612B2 - Display device - Google Patents

Description

  The invention described in this specification relates to a panel structure of an EL display panel that is driven and controlled by an active matrix driving method. Note that the invention proposed in this specification also has a side surface as an electronic apparatus on which the EL display panel is mounted.

  FIG. 1 shows a general circuit block configuration of an active matrix driving type organic EL panel. As shown in FIG. 1, the organic EL panel 1 includes a pixel array unit 3, a write control line drive unit 5 that is a drive circuit thereof, and a horizontal selector 7. In the pixel array section 3, pixel circuits 9 are arranged at intersections of the signal lines DTL and the write control lines WSL.

  By the way, the organic EL element is a current light emitting element. For this reason, the organic EL panel employs a driving method in which the gradation is controlled by controlling the amount of current flowing through the organic EL element corresponding to each pixel. FIG. 2 shows one of the simplest circuit configurations of this type of pixel circuit 9. The pixel circuit 9 includes a sampling transistor T1, a drive transistor T2, and a storage capacitor Cs.

The sampling transistor T1 has a signal voltage Vsig corresponding to the gradation of the corresponding pixel.
It is a thin film transistor that controls writing to the storage capacitor Cs. The drive transistor T2 is a thin film transistor that supplies the drive current Ids to the organic EL element OLED based on the gate-source voltage Vgs determined according to the signal voltage Vsig held in the holding capacitor Cs. In the case of FIG. 2, the sampling transistor T1 is composed of an N-channel thin film transistor, and the drive transistor T2 is composed of a P-channel thin film transistor.

In the case of FIG. 2, the source electrode of the drive transistor T2 is connected to a power supply line to which a fixed potential (power supply potential Vcc) is applied, and always operates in a saturation region. That is, the drive transistor T2 operates as a constant current source that supplies a drive current having a magnitude corresponding to the signal voltage Vsig to the organic EL element OLED. At this time, the drive current Ids is given by the following equation.
Ids = k · μ · (Vgs -Vth) 2/2

  Incidentally, μ is the mobility of majority carriers of the driving transistor T2. Vth is a threshold voltage of the driving transistor T2. K is a coefficient given by (W / L) · Cox. Here, W is the channel width, L is the channel length, and Cox is the gate capacitance per unit area.

  In addition, it is known that the pixel circuit having this configuration has a characteristic that the drain voltage of the driving transistor T2 changes as the IV characteristic of the organic EL element shown in FIG. 3 changes with time. However, since the gate-source voltage Vgs is kept constant, there is no change in the amount of current supplied to the organic EL element, and the light emission luminance can be kept constant.

  Below, the literature regarding the organic electroluminescent panel display which employ | adopts an active matrix drive system is illustrated.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A Japanese Patent Laid-Open No. 2004-093682

  Incidentally, the circuit configuration shown in FIG. 2 may not be adopted depending on the type of thin film process. That is, in the current thin film process, there are cases where a P-channel type thin film transistor cannot be employed. In such a case, the driving transistor T2 is replaced with an N-channel thin film transistor.

  FIG. 4 shows the configuration of this type of pixel circuit. In this case, the source electrode of the drive transistor T2 is connected to the anode (anode) terminal of the organic EL element OLED. However, in the case of this pixel circuit, there is a problem that the gate-source voltage Vgs varies as the IV characteristic of the organic EL element changes with time. This variation in the gate-source voltage Vgs changes the amount of drive current and changes the light emission luminance.

  In addition, the threshold and mobility of the drive transistor T2 constituting each pixel circuit are different for each pixel. The difference in threshold value and mobility of the drive transistor T2 appears as variations in the drive current value, and the light emission luminance changes for each pixel.

  Therefore, when the pixel circuit shown in FIG. 4 is employed, it is required to establish a driving method that can obtain stable light emission characteristics regardless of changes over time. At the same time, it is required to realize an EL display panel whose manufacturing cost is low.

  Accordingly, the inventors have a pixel array unit in which EL display elements whose light emission states are controlled by an active matrix driving method are arranged in a matrix, and first and first driving each write control line from both sides of the pixel array unit. Proposed is an EL display panel having two write control line drive units and first and second power supply line drive units for driving power supply lines wired along a horizontal line direction from both sides of the pixel array unit. .

However, it is desirable that each of the first and second power supply line driving units be disposed between the first and second write control line driving units and the pixel array unit.
Note that the output buffer circuit located in the final output stage constituting the first and second power supply line driving units is preferably formed so that the direction of the channel length of the thin film transistor is parallel to the signal line.
In addition, the output buffer circuit located in the final output stage constituting the first and second power supply line driving units is preferably formed so that the channel width of the thin film transistor is larger than the length of one pixel in the signal line direction.

  By adopting these arrangement structures, the size of the transistor constituting the buffer circuit can be enlarged with respect to the pixel pitch. In addition, the wiring distance between the power supply line and the main electrode of the transistor can be shortened. Therefore, the resistance value of the buffer circuit is reduced, and the rounding of the waveform of the power supply line potential and the resistance can be reduced.

Note that it is desirable that the writing control line and the power supply line in the pixel array portion are low resistance wiring. For example, aluminum, copper, gold, or an alloy of these metals is desirable. By adopting low-resistance wiring, it is possible to reduce the rounding and resistance of the power line potential.
The inventors also propose an electronic device equipped with the EL display panel having the above-described configuration.
Here, the electronic device includes an EL display panel having the above-described configuration, a system control unit that controls the operation of the entire system, and an operation input unit that receives an operation input to the system control unit.

  In the invention proposed by the inventors, the power supply lines for supplying current to the EL light emitting elements in the respective pixel regions can be simultaneously driven by the power supply line driving units disposed on both sides of the pixel array unit. Thereby, even when the size of the pixel array portion is increased and the driving time of the power supply line is shortened, the dullness of the waveform of the write control line can be reduced, and the occurrence of shading can be effectively suppressed.

  Further, by arranging these pair of power supply line drive units closer to the pixel array unit than the write control line drive unit, the power supply line drive unit can be written with the wiring length of the power supply line extending from the output end of the power supply line drive unit. This can be shortened as compared with the case where it is arranged outside the embedded control line driving unit.

  In addition, by arranging the power supply line drive unit inside the write control line drive unit, the number of times that the power supply line crosses three-dimensionally with the wiring of another drive unit can be reduced. In general, a wiring having a relatively high resistance value is used for the wiring at the intersection due to the process. For this reason, the reduction of the three-dimensional intersection is effective in reducing the load of the power line driver.

  Thereby, the voltage drop in the power supply line during white display can be reduced. This means that the voltage drop difference between white display and black display is reduced. Therefore, it is possible to obtain a uniform image quality without shading as well as crosstalk.

It is a figure explaining the block configuration of an organic electroluminescent panel. It is a figure explaining the connection relation of a pixel circuit and a drive circuit. It is a figure explaining the time-dependent change of the IV characteristic of an organic EL element. It is a figure which shows the other pixel circuit example. It is a figure which shows the external appearance structural example of an organic electroluminescent panel. It is a figure which shows the system structural example of an organic electroluminescent panel. It is a figure explaining the connection relation of a pixel circuit and a drive circuit. It is a figure which shows the structural example of the pixel circuit which concerns on the form example. It is a figure explaining the difference in the potential change which generate | occur | produces according to the positional relationship of a write-in line. It is a figure which shows the internal structure of a write-control line drive part and a power supply line drive part. It is a figure explaining the cross-sectional structure of the broken-line area | region of FIG. It is a figure which shows the drive operation example which concerns on an example. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure which shows the time-dependent change of source potential. It is a figure explaining the operation state of a pixel circuit. It is a figure which shows the difference in a time-dependent change by the difference in mobility. It is a figure explaining the operation state of a pixel circuit. It is a figure which shows the other structural example of the organic electroluminescent panel which concerns on an example. It is a figure explaining the connection relation of a pixel circuit and a drive circuit. It is a figure which shows the structural example of the pixel circuit which concerns on the form example. It is a figure which shows the internal structure of a write-control line drive part and a power supply line drive part. It is a figure which shows the example of a display image. It is a figure which shows the example of a display image. It is a figure which shows the circuit structural example of an output buffer circuit. It is a figure which shows the example of a horizontal layout pattern employ | adopted with the inverter circuit which comprises the last stage of an output buffer circuit. It is a figure which shows the example of a vertical layout pattern employ | adopted as the inverter circuit which comprises the last stage of an output buffer circuit. It is a figure which shows the other connection relation of a pixel circuit and a drive circuit. It is a figure which shows the drive operation example of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure explaining the operation state of a pixel circuit. It is a figure which shows the example of a conceptual structure of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device.

The case where the invention is applied to an active matrix driving type organic EL panel will be described below.
In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification. Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) Appearance Configuration In this specification, not only a display panel in which a pixel array unit and a drive circuit are formed on the same substrate using the same semiconductor process, but also a drive circuit manufactured as an application-specific IC, for example. What is mounted on the substrate on which the pixel array portion is formed is also called an organic EL panel.

FIG. 5 shows an external configuration example of the organic EL panel. The organic EL panel 11 has a structure in which the facing portion 15 is bonded to the formation region of the pixel array portion of the support substrate 13.
The facing portion 15 has a structure in which a transparent member such as glass, plastic film or the like is used as a base material, and an organic EL layer, a protective film, or the like is laminated on the surface thereof.
The organic EL panel 11 is provided with an FPC (flexible printed circuit) 17 for inputting and outputting signals and the like to the support substrate 13 from the outside.

(B) Form 1
(B-1) System Configuration An example of the system configuration of the organic EL panel 11 that prevents variation in the characteristics of the drive transistor T2 and that requires a small number of elements constituting the pixel circuit will be described below. In this embodiment, an organic EL panel having a large screen size is assumed.

  FIG. 6 shows a system configuration example of the organic EL panel 11. The organic EL panel 11 shown in FIG. 6 includes a pixel array unit 21, a write control line drive unit 23 that is a drive circuit thereof, a power supply line drive unit 25, a horizontal selector 27, and a timing generator 29.

  The pixel array unit 21 has a matrix structure in which sub-pixels are arranged at each intersection position between the signal line DTL and the write control line WSL. Incidentally, the sub-pixel is the minimum unit of the pixel structure constituting one pixel. For example, one pixel as a white unit is composed of three sub-pixels (R, G, B) made of different organic EL materials.

  FIG. 7 shows a connection relationship between the pixel circuit 31 corresponding to the sub-pixel and each driving circuit. FIG. 8 shows an internal configuration of the pixel circuit 31 proposed in the first embodiment. The pixel circuit shown in FIG. 8 includes two N-channel thin film transistors T1 and T2 and one storage capacitor Cs.

  Also in this circuit configuration, the write control line drive unit 23 is used to control the opening and closing of the sampling transistor T1 through the write control line WSL and to control the writing of the signal line potential to the storage capacitor Cs. Incidentally, the write control line drive unit 23 is composed of a shift register having the number of output stages corresponding to the number of vertical resolutions.

  In the case of this embodiment, two write control line driving units 23 that operate with the same pulse are arranged on both sides of the pixel array unit 21, and one write control line WSL is simultaneously provided from both sides of the pixel array unit 21. Adopt a driving method.

  When the screen size of the organic EL panel 11 is large, as shown in FIG. 9, the potential change (FIG. 9B) of the write control line WSL at a position far from the write control line driving unit 23 is the write control. It is easier to dull than the potential change (FIG. 9A) of the write control line WSL at a position close to the line drive unit 23. Further, the writing time difference due to the dullness of the waveform makes it difficult to perform a normal signal potential writing operation and causes shading.

On the other hand, when two write control line drive units 23 are arranged on both sides of the pixel array unit 21, the range driven by each write control line drive unit 23 is halved, and the potential change of the write control line WSL changes. Delay and dullness can be minimized.
In the case of the first form example, the write control line drive unit 23 is disposed closer to the pixel array unit 21 than the power supply line drive unit 25.

  The power supply line driving unit 25 binary-controls the power supply line DSL connected to one main electrode of the drive transistor T2 through the power supply line DSL, and the operation content in the pixel circuit is controlled by an interlocking operation with another drive circuit. Used to control. The operation here includes not only light emission / non-light emission of the organic EL element but also a correction operation for characteristic variation. In the case of this embodiment, the correction of the characteristic variation means correction of deterioration of the uniformity based on the variation in the threshold value of the driving transistor T2 and the variation in mobility.

  In the case of this embodiment, two power supply line driving units 25 are also prepared. Two power supply line driving units 25 are arranged on both sides of the pixel array unit 21, and one power supply line DSL is simultaneously driven from both sides of the pixel array unit 21. This is because, when the screen size of the organic EL panel 11 is large, the potential change of the power supply line DSL far from the power supply line driving unit 25 is likely to become dull, and normal timing control becomes difficult.

On the other hand, when two power supply line drive units 25 are arranged on both sides of the pixel array unit 21, the range driven by each power supply line drive unit 25 is halved, and the delay and dullness of potential change of the power supply line DSL is minimized Can be
In the case of the first form example, the power supply line drive unit 25 is disposed outside the write control line drive unit 23.

For reference, an example of a circuit configuration of the write control line drive unit 23 and the power supply line drive unit 25 is shown in FIG. As shown in FIG. 10, the basic configuration of the write control line drive unit 23 and the power supply line drive unit 25 is the same.
That is, the write control line drive unit 23 includes a shift register unit 231, a waveform adjustment circuit 233, and an output buffer circuit 235. On the other hand, the power line driver 25 includes a shift register 251, a waveform adjustment circuit 253, and an output buffer circuit 255.

  In the figure, shaded patterns are power supply wirings for driving each part. Incidentally, the power supply wiring indicated by “Vh” is a wiring for supplying the “H level” power supply potential to the shift register units 231 and 251 and the waveform adjustment circuits 233 and 253. On the other hand, the power supply wiring indicated by “Vl” is a wiring for supplying the “L level” power supply potential to the shift register units 231 and 251 and the waveform adjustment circuits 233 and 253.

  The power supply wiring indicated by “Vcc_ * (where * is ws or ds)” is a wiring for supplying the “H level” power supply potential to the waveform adjustment circuits 233 and 253 and the output buffer circuits 235 and 255. On the other hand, the power supply wiring indicated by “Vss_ * (where * is ws or ds)” is a wiring for supplying the “L level” power supply potential to the waveform adjustment circuits 233 and 253 and the output buffer circuits 235 and 255.

Here, the shift register units 231 and 251 are configured by flip-flop stages that perform an operation of sequentially transferring the sampling pulse SP to the next stage based on the clock pulse CK, and one stage of the flip-flop stage is placed on one stage of the horizontal line. Correspond.
The waveform adjustment circuits 233 and 253 are circuits that adjust the pulse width and pulse height in the time axis direction.

The output buffer circuits 235 and 255 are circuit devices that respectively drive the write control line WSL and the power supply line DSL with the corresponding binary power supply potential. Specifically, it is composed of a circuit in which one or more inverter circuits are connected in series.
Note that all the power supply wirings are wired perpendicular to the horizontal line. On the other hand, all the power supply lines DSL driven by the power supply line driving unit 25 are wired in parallel to the horizontal line.

Therefore, as shown in FIG. 11, the power supply line DSL has a wiring structure that three-dimensionally intersects with the power supply wiring in the write control line drive unit 23.
The power supply wiring is basically made of aluminum. However, aluminum becomes thicker. For this reason, a metal material such as molybdenum, which generally requires a thin film thickness, is used at the three-dimensional intersection.

As a result, in the case of the organic EL panel 11 shown in FIG. 6, the power supply line DSL is formed as a mixed wiring of aluminum and molybdenum.
In the case of the organic EL panel 11 having the structure shown in FIG. 6, three intersections are formed at a total of four locations, one on each side of the pixel array unit 21 for one power line DSL.

The horizontal selector 27 is used to apply a signal potential Vsig corresponding to the pixel data Din or an offset voltage Vofs for threshold correction to the signal line DTL. The horizontal selector 27 includes a shift register having the number of output stages corresponding to the number of horizontal resolutions, a latch circuit corresponding to each output stage, and a D / A conversion circuit.
The timing generator 29 is a circuit device that generates timing pulses necessary for driving the write control line WSL, the power supply line DSL, and the signal line DTL.

(B-2) Driving Operation Example FIG. 12 shows a driving operation example of the pixel circuit shown in FIG. In FIG. 12, of the two types of power supply potentials applied to the power supply line DSL, the higher potential (light emission potential) is represented by Vcc, and the lower potential (non-light emission potential) is represented by Vss.

  First, an operation state in the pixel circuit in the light emission state is shown in FIG. At this time, the sampling transistor T1 is in an off state. On the other hand, the driving transistor T2 operates in the saturation region, and a current Ids determined according to the gate-source voltage Vgs flows (FIG. 12 (t1)).

  Next, the operation state in the non-light emitting state will be described. At this time, the potential of the power supply line DSL is switched from the high potential Vcc to the low potential Vss (FIG. 12 (t2)). At this time, if the low potential Vss is smaller than the sum of the threshold value Vthel of the organic EL element and the cathode potential Vcath, that is, if Vss <Vthel + Vcath, the organic EL element is turned off.

  Note that the source potential Vs of the drive transistor T2 is the same as the potential of the power supply line DSL. That is, the anode electrode of the organic EL element is charged to the low potential Vss. FIG. 14 shows an operation state in the pixel circuit. At this time, as indicated by a broken line in FIG. 14, the charge held in the storage capacitor Cs is drawn out to the power supply line DSL.

  Thereafter, when the write control line WSL changes to a high potential while the potential of the signal line DTL has transitioned to the offset potential Vofs for threshold correction, the gate potential of the drive transistor T2 is offset through the sampling transistor T1 that has been turned on. It changes to Vofs (FIG. 12 (t3)).

  FIG. 15 shows an operation state in the pixel circuit in this case. At this time, the gate-source voltage Vgs of the driving transistor T2 is given by Vofs−Vss. This voltage is set to be larger than the threshold voltage Vth of the driving transistor T2. This is because the threshold value correcting operation cannot be executed unless Vofs−Vss> Vth is satisfied.

  Next, the power supply potential of the power supply line DSL is switched again to the high potential Vcc (FIG. 12 (t4)). By changing the power supply potential of the power supply line DSL to the high potential Vcc, the anode potential Vel of the organic EL element OLED becomes the source potential Vs of the drive transistor T2.

  In FIG. 16, the organic EL element OLED is shown by an equivalent circuit. That is, it is represented by a diode and a parasitic capacitance Cel. At this time, as long as the relationship of Vel ≦ Vcat + Vthel is satisfied (however, the leakage current of the organic EL element is considered to be considerably smaller than the driving current Ids flowing through the driving transistor T2), the driving current Ids flowing through the driving transistor T2 is equal to the storage capacitor. Used to charge Cs and parasitic capacitance Cel.

  As a result, the anode potential Vel of the organic EL element OLED increases with time as shown in FIG. That is, the source potential Vs of the drive transistor T2 starts to rise while the gate potential of the drive transistor T2 is fixed to the offset potential Vofs. This operation is a threshold correction operation.

Eventually, the gate-source voltage Vgs of the drive transistor T2 converges to the threshold voltage Vth. At this time, Vel = Vofs−Vth ≦ Vcat + Vthel is satisfied.
When the threshold correction period ends, the sampling transistor T1 is turned off again (t5 in FIG. 12).

Thereafter, the sampling transistor T1 is again turned on after the timing necessary for the potential of the signal line DTL to transition to the signal potential Vsig (FIG. 12 (t6)). FIG. 18 shows an operation state in the pixel circuit in this case. The signal potential Vsig is a potential given according to the gradation value of the corresponding pixel.
At this time, the gate potential Vg of the driving transistor T2 transitions to the signal potential Vsig. On the other hand, the source potential Vs of the drive transistor T2 rises with time due to the current flowing from the power supply line DSL to the storage capacitor Cs.

  At this time, if the source potential Vs of the driving transistor T2 does not exceed the sum of the threshold voltage Vthel and the cathode voltage Vcat of the organic EL element (if the leakage current of the organic EL element is considerably smaller than the current flowing through the driving transistor T2), driving is performed. The drive current Ids supplied by the transistor T2 is used to charge the storage capacitor Cs and the parasitic capacitor Cel.

  Since the threshold correction operation of the drive transistor T2 has already been completed, the drive current Ids that the drive transistor T2 flows becomes a value that reflects the mobility μ of the drive transistor T2. Specifically, a drive transistor having a higher mobility μ flows a larger drive current Ids, and the source potential Vs rises faster. Conversely, a drive transistor having a smaller mobility μ causes a smaller drive current Ids to flow, and the increase in the source potential Vs becomes slower (FIG. 19).

  As a result, the holding voltage of the holding capacitor Cs is corrected according to the mobility μ of the driving transistor T2. That is, the gate-source voltage Vgs of the driving transistor T2 changes to a voltage in which the mobility μ is corrected.

Finally, when the sampling transistor T1 is turned off and the writing of the signal potential is completed, the light emission period of the organic EL element OLED starts (FIG. 12 (t7)). FIG. 20 shows an operation state in the pixel circuit in this case. Note that the gate-source voltage Vgs of the driving transistor T2 is constant. Accordingly, the drive transistor T2 supplies a constant current Ids ′ to the organic EL element.

Along with this, the anode potential Vel of the organic EL element rises to a potential Vx that causes the current Ids ′ to flow through the organic EL element. Thereby, light emission by the organic EL element is started.
By the way, also in the case of the drive circuit proposed in this embodiment, the IV characteristic of the organic EL element OLED changes as the light emission time becomes longer.

  That is, the source potential Vs of the drive transistor T2 also changes. However, since the gate-source voltage Vgs of the driving transistor T2 is kept constant by the storage capacitor Cs, the amount of current flowing through the organic EL element OLED does not change. As described above, when the pixel circuit and the driving method proposed in this embodiment are employed, the driving current Ids corresponding to the signal potential Vsig can be continuously supplied regardless of the change in the IV characteristic of the organic EL element OLED. it can. Thereby, the light emission luminance of the organic EL element OLED can be kept at the luminance according to the signal potential Vsig.

(B-3) Summary As described above, by adopting the pixel circuit and driving method described in this embodiment, even when the driving transistor T2 is composed of an N-channel thin film transistor, the organic EL panel has no luminance variation for each pixel. Can be realized.

In the case of this embodiment, the write control line drive unit 23 and the power supply line drive unit 25 are arranged on both sides of the pixel array unit 21, respectively, and the write control line WSL and the power supply line DSL are simultaneously driven and controlled from both sides. be able to.
For this reason, even when the size of the pixel array unit 21 is increased and the driving time of the power supply line DSL is shortened, the waveform dullness of the write control line WSL can be reduced, and the occurrence of shading can be effectively suppressed.

  In addition, when the power line DSL is driven from one side of the screen, the voltage difference between both ends of the screen must be increased, but by driving from both sides of the screen, the voltage difference on the power line DSL is reduced. be able to. In particular, since the organic EL element is a current driving element, the voltage difference of the power supply line DSL is directly connected to the difference in driving current (light emission luminance). For this reason, since the voltage difference can be reduced, the influence of the voltage drop during white display (that is, crosstalk) can be reduced.

  As described above, by adopting this embodiment, it is possible to obtain stable light emission characteristics regardless of changes over time while using only an N-channel thin film transistor, and at the same time, a decrease in display quality within the screen is perceived. Difficult organic EL panel can be realized.

(C) Form example 2
(C-1) System Configuration Hereinafter, a panel structure that can further improve the display quality of an organic EL panel having a large screen size will be described.

  FIG. 21 shows a system configuration example of the organic EL panel 11. In FIG. 21, the same reference numerals are given to the corresponding parts to FIG. 6. As shown in FIG. 21, the basic system configuration is the same. That is, the organic EL panel 11 shown in FIG. 21 also includes a pixel array unit 21, a write control line drive unit 23 that is a drive circuit thereof, a power supply line drive unit 41, a horizontal selector 27, and a timing generator 29.

The difference is the positional relationship between the write control line driving unit 23 and the power supply line driving unit 41 in the panel.
First, in this embodiment, the positional relationship between the power supply line drive unit 41 and the write control line drive unit 23 is switched. That is, the power supply line drive unit 41 is disposed closer to the pixel array unit than the write control line drive unit 23.

In this embodiment, the output buffer circuit constituting the power supply line drive unit 41 is enlarged, and the resistance value of the buffer portion is reduced.
FIG. 22 shows a connection relationship between the pixel circuit 31 corresponding to the sub-pixel and each driving circuit. FIG. 23 shows an internal configuration of the pixel circuit 31.

Further, FIG. 24 shows a wiring relationship between the write control line drive unit 23 and the power supply line drive unit 41. As shown in FIG. 24, this time, the write control line WSL that is driven and controlled by the write control line drive unit 23 becomes a mixed wiring, and three-dimensionally intersects at the portion of the power supply wiring that supplies the drive power to the power supply line drive unit 41 .
On the other hand, the power supply line DSL can be composed of only a low resistance metal because the number of three-dimensional intersections with the drive power supply is smaller than in the first embodiment. In the case of this embodiment, the power supply line DSL is made of aluminum.

  In addition, the wiring length of the power supply line DSL is shorter than that of the first embodiment by exchanging the positional relationship of the driving units. For this reason, the wiring resistance of the power supply line DSL is smaller than that of the first embodiment. Therefore, in the case of the panel structure proposed in this embodiment, the possibility that crosstalk and shading are visually recognized can be reduced as compared with Embodiment 1.

On the other hand, in the second embodiment, the resistance value of the write control line WSL is higher than that in the first embodiment. As a result, the maximum value of the writing time difference on the horizontal line is larger than that in the first embodiment.
However, shading caused by the difference in writing time is not visually recognized unless the luminance difference is about 20%. Therefore, even if the write control line drive unit 23 is arranged outside the power supply line drive unit 41, the problem of the write time difference can be suppressed by the both-side drive.

  On the other hand, the crosstalk caused by the voltage drop of the power supply line DSL is visually recognized even when the luminance difference is about 1%. For this reason, the technical effect of reducing the wiring resistance of the power supply line DSL as in the second embodiment is great.

Incidentally, the drive transistor T2 in each pixel circuit operates in a saturation region. For this reason, even if the wiring resistance is small, the influence of the Early effect still exists.
For this reason, when an image of the kind shown in FIG. 25 is input to the organic EL panel 11, a potential difference is generated between the voltage drop of the power line of the white display line and the voltage drop of the power line of the black window display line. End up.

When this potential difference is 1% or more of the luminance difference, crosstalk is visually recognized.
Incidentally, the occurrence of crosstalk depends on the difference in the amount of power supply voltage drop in the display line (horizontal line). That is, the occurrence of crosstalk greatly affects not only the power supply line DSL portion but also the output resistance value of the output buffer circuit 257.

For example, if the output resistance value of the output buffer circuit 257 is large even if the wiring resistance of the power supply line DSL is small, the brightness of the white display line becomes dark due to the voltage drop as shown in FIG. It will be visually recognized.
Therefore, in this embodiment, a power supply line drive unit 41 in which the output resistance value of the output buffer circuit 257 is reduced is proposed.

As an example, FIG. 27 shows an equivalent circuit of the output buffer circuit 257 constituting the power line driver 41. As shown in FIG. 27, the output buffer circuit 257 is configured by two-stage connection of CMOS inverter circuits.
FIG. 28 shows a planar structure of a CMOS inverter circuit constituting the final stage of the output buffer circuit 257.

  In the drawing, regions surrounded by broken lines correspond to P-channel thin film transistors and N-channel thin film transistors, respectively. As shown in the figure, the size of the P-channel thin film transistor is formed to be larger than the size of the N-channel thin film transistor. Specifically, it is formed to be 1.5 times or more, preferably about 10 times. This is to reduce the wiring resistance from the power supply wiring Vcc.

However, the increase in the size of the P-channel thin film transistor is practically limited by the pixel pitch. Moreover, the pixel pitch decreases as the resolution increases. Therefore, it is necessary to devise a method for increasing the size of the P-channel type thin film transistor in a limited layout.
In general, in order to reduce the output resistance of the output buffer circuit 257, it is necessary to increase the channel width of the P-channel thin film transistor.

  Therefore, the last-stage CMOS inverter circuit is formed horizontally as shown in FIG. That is, the channel length direction of the P-channel thin film transistor is formed so as to be parallel to the signal line (perpendicular to the horizontal line direction). At this time, it is desirable that the channel width be larger than the length of one pixel in the signal line direction. By adopting this structure, it becomes possible to flow a large amount of current, and the output resistance can be reduced accordingly.

Further, this horizontal layout has an advantage that the distance between the channel and the power supply wiring Vcc can be shortened as compared with the vertical layout shown in FIG. The distance here is given by the length from the power supply wiring Vcc to the point A shown in FIGS.
Obviously, the horizontal layout can reduce the length of the power supply wiring Vcc and the channel.

(C-2) Summary As described above, in this embodiment, the power supply line drive unit 41 is formed closer to the pixel array unit 21 than the write control line drive unit 23, thereby reducing the wiring length of the power supply line DSL. Shortening and simplification of the wiring structure (reduction of three-dimensional intersection) can be realized, and the wiring resistance can be reduced.

  In addition, the channel direction of the P-channel type thin film transistor of the inverter circuit constituting the final stage of the output buffer circuit 257 of the power supply line drive unit 41 is formed so as to be parallel to the signal line DTL (adopting a horizontal layout). As a result, the wiring resistance in the output buffer circuit 257 can be reduced.

  As a result, the wiring resistance of the power supply line DSL can be reduced as a whole including the output stage of the output buffer circuit 257. Therefore, even if the influence of the Early effect is taken into consideration, the difference in the power supply voltage drop on the power supply line DSL can be made smaller than that in the first embodiment, and the organic EL panel 11 in which the crosstalk is hardly visually recognized can be realized. .

  That is, it is possible to realize the organic EL panel 11 that can expect high image quality in principle. In addition, the channel direction of the output buffer circuit 257 is formed in parallel with the direction of the signal line. Accordingly, it is possible to realize a narrow frame of the organic EL panel 11.

(D) Other Embodiment (D-1) Wiring Material of Power Supply Line DSL In the case of the above-described Embodiment 2, the case where the power supply line DSL is formed of aluminum has been described.
However, aluminum, copper, gold, or an alloy thereof may be used for the power supply line DSL of the second embodiment. The wiring resistance value of these wiring materials can be lower than that of molybdenum. Therefore, it is advantageous for reducing the resistance of the power supply line DSL.

(D-2) Other Pixel Circuit Examples In the case of the above-described embodiment, the case where the pixel circuit 31 includes two thin film transistors has been described. For this reason, a threshold voltage correction reference voltage (hereinafter referred to as “offset voltage”) Vofs is applied through a signal line DTL.

However, a transistor may be arranged exclusively for controlling the application timing of the offset voltage Vofs.
FIG. 30 shows a configuration example of the pixel circuit 51 corresponding to the modification. In the case of the pixel circuit 51, the second sampling transistor T3 is disposed. One main electrode of the second sampling transistor T3 is connected to the gate electrode of the drive transistor T2, and the other main electrode is connected to an offset line OFSL to which an offset voltage Vofs is fixedly supplied.

The on / off control of the second sampling transistor T3 is controlled by the offset line driving unit 53.
In this example, only the signal potential Vsig corresponding to each pixel is applied to the signal line DTL. Incidentally, the positional relationship between the offset line drive unit 53 and the write control line drive unit 23 shown in FIG. 30 may be interchanged.

  FIG. 31 shows an example of driving operation of the pixel circuit described in FIG. In FIG. 31, of the two types of power supply potentials applied to the power supply line DSL, the higher potential (light emission potential) is represented by Vcc, and the lower potential (non-light emission potential) is represented by Vss.

  First, FIG. 32 shows an operation state in the pixel circuit in the light emission state. At this time, the sampling transistor T1 is in an off state. On the other hand, the drive transistor T2 operates in the saturation region, and a current Ids determined according to the gate-source voltage Vgs flows (FIG. 31 (t1)).

  Next, the operation state in the non-light emitting state will be described. At this time, the potential of the power supply line DSL is switched from the high potential Vcc to the low potential Vss (FIG. 31 (t2)). At this time, if the low potential Vss is smaller than the sum of the threshold value Vthel of the organic EL element and the cathode potential Vcath, that is, if Vss <Vthel + Vcath, the organic EL element OLED is turned off.

  Note that the source potential Vs of the drive transistor T2 is the same as the potential of the power supply line DSL. That is, the anode electrode of the organic EL element is charged to the low potential Vss. FIG. 33 shows an operation state in the pixel circuit. At this time, as indicated by a broken line in FIG. 33, the charge held in the storage capacitor Cs is drawn out to the power supply line DSL.

  Thereafter, the second sampling transistor T3 is turned on by the offset line driving unit 53. As a result, the gate potential of the driving transistor T2 changes to the offset potential Vofs (FIG. 31 (t3)).

  FIG. 34 shows an operation state in the pixel circuit in this case. At this time, the gate-source voltage Vgs of the driving transistor T2 is given by Vofs−Vss. This voltage is set to be larger than the threshold voltage Vth of the driving transistor T2. This is because the threshold value correcting operation cannot be executed unless Vofs−Vss> Vth is satisfied.

  Next, the power supply potential of the power supply line DSL is switched again to the high potential Vcc (FIG. 31 (t4)). By changing the power supply potential of the power supply line DSL to the high potential Vcc, the anode potential of the organic EL element OLED is given by the source potential Vs of the drive transistor T2.

  In FIG. 35, the organic EL element OLED is shown by an equivalent circuit. That is, it is represented by a diode and a parasitic capacitance Cel. At this time, as long as the relationship of Vel ≦ Vcat + Vthel is satisfied (however, the leakage current of the organic EL element is considered to be considerably smaller than the driving current Ids flowing through the driving transistor T2), the driving current Ids flowing through the driving transistor T2 is equal to the storage capacitor. Used to charge Cs and parasitic capacitance Cel.

  As a result, the anode voltage Vel of the organic EL element OLED increases with time. That is, the source potential Vs of the drive transistor T2 starts to rise while the gate potential of the drive transistor T2 is fixed to the offset potential Vofs.

Eventually, the gate-source voltage Vgs of the drive transistor T2 converges to the threshold voltage Vth. At this time, Vel = Vofs−Vth ≦ Vcat + Vthel is satisfied.
When the threshold correction period ends, the second sampling transistor T3 is turned off again (FIG. 31 (t5)). FIG. 36 shows an operation state in the pixel circuit in this case.

Thereafter, after the timing necessary for the potential of the signal line DTL to transition to the signal potential Vsig, the first sampling transistor T1 is controlled to be in an on state (FIG. 31 (t6)). FIG. 37 shows an operation state in the pixel circuit in this case. The signal potential Vsig is a potential given according to the gradation value of the corresponding pixel.
At this time, the gate potential Vg of the driving transistor T2 transitions to the signal potential Vsig. On the other hand, the source potential Vs of the drive transistor T2 rises with time due to the current flowing from the power supply line DSL to the storage capacitor Cs.

  At this time, if the source potential Vs of the driving transistor T2 does not exceed the sum of the threshold voltage Vthel and the cathode voltage Vcat of the organic EL element (if the leakage current of the organic EL element is considerably smaller than the current flowing through the driving transistor T2), driving is performed. The drive current Ids supplied by the transistor T2 is used to charge the storage capacitor Cs and the parasitic capacitor Cel.

  Since the threshold correction operation of the drive transistor T2 has already been completed, the drive current Ids that the drive transistor T2 flows becomes a value that reflects the mobility μ of the drive transistor T2. Specifically, a drive transistor having a higher mobility μ flows a larger drive current Ids, and the source potential Vs rises faster. Conversely, a driving transistor having a smaller mobility μ flows a smaller driving current Ids, and the increase in the source potential Vs is delayed.

  As a result, the holding voltage of the holding capacitor Cs is corrected according to the mobility μ of the driving transistor T2. That is, the gate-source voltage Vgs of the driving transistor T2 changes to a voltage in which the mobility μ is corrected.

Finally, when the first sampling transistor T1 is turned off and signal potential writing is completed, the light emission period of the organic EL element OLED starts (FIG. 31 (t7)). FIG. 38 shows an operation state in the pixel circuit in this case. Note that the gate-source voltage Vgs of the driving transistor T2 is constant. Accordingly, the drive transistor T2 supplies a constant current Ids ′ to the organic EL element.

Along with this, the anode potential Vel of the organic EL element rises to a potential Vx that causes the current Ids ′ to flow through the organic EL element. Thereby, light emission by the organic EL element is started.
By the way, also in the case of the drive circuit proposed in this embodiment, the IV characteristic of the organic EL element OLED changes as the light emission time becomes longer.

  That is, the source potential Vs of the drive transistor T2 also changes. However, since the gate-source voltage Vgs of the driving transistor T2 is kept constant by the storage capacitor Cs, the amount of current flowing through the organic EL element OLED does not change. As described above, when the pixel circuit and the driving method proposed in this embodiment are employed, the driving current Ids corresponding to the signal potential Vsig can be continuously supplied regardless of the change in the IV characteristic of the organic EL element OLED. it can. Thereby, the light emission luminance of the organic EL element OLED can be kept at the luminance according to the signal potential Vsig.

(D-3) Product Example (a) Electronic Device In the above description, the invention has been described with an organic EL panel as an example. However, the organic EL panels described above are also distributed in product forms mounted on various electronic devices. Examples of mounting on other electronic devices are shown below.

  FIG. 39 shows a conceptual configuration example of the electronic device 61. The electronic device 61 includes the organic EL panel 63, the system control unit 65, and the operation input unit 67 described above. The processing content executed by the system control unit 65 differs depending on the product form of the electronic device 61. The operation input unit 67 is a device that receives an operation input to the system control unit 65. For the operation input unit 67, for example, a switch, a button, other mechanical interfaces, a graphic interface, or the like is used.

Note that the electronic device 61 is not limited to a device in a specific field as long as it has a function of displaying an image or video generated in the device or input from the outside.
FIG. 40 shows an example of the appearance when the other electronic device is a television receiver. A display screen 77 including a front panel 73, a filter glass 75, and the like is disposed on the front surface of the television receiver 71. The portion of the display screen 77 corresponds to the organic EL panel described in the embodiment.

  Also, for example, a digital camera is assumed as this type of electronic device 61. FIG. 41 shows an example of the appearance of the digital camera 81. FIG. 41A shows an example of the appearance on the front side (subject side), and FIG. 41B shows an example of the appearance on the back side (photographer side).

  The digital camera 81 includes a protective cover 83, an imaging lens unit 85, a display screen 87, a control switch 89, and a shutter button 91. Of these, the display screen 87 corresponds to the organic EL panel described in the embodiment.

For example, a video camera is assumed as this type of electronic device 61. FIG. 42 shows an example of the appearance of the video camera 101.
The video camera 101 includes an imaging lens 105 that images a subject in front of a main body 103, a shooting start / stop switch 107, and a display screen 109. Of these, the display screen 109 corresponds to the organic EL panel described in the embodiment.

  Further, for example, a portable terminal device is assumed as this type of electronic device 61. FIG. 43 shows an example of the appearance of a mobile phone 111 as a mobile terminal device. A cellular phone 111 illustrated in FIG. 43 is a foldable type, and FIG. 43A illustrates an appearance example in a state where the housing is opened, and FIG. 43B illustrates an appearance example in a state where the housing is folded.

  The mobile phone 111 includes an upper housing 113, a lower housing 115, a connecting portion (in this example, a hinge portion) 117, a display screen 119, an auxiliary display screen 121, a picture light 123, and an imaging lens 125. Among these, the display screen 119 and the auxiliary display screen 121 correspond to the organic EL panel described in the embodiment.

Further, for example, a computer is assumed as this type of electronic device 61. FIG. 44 shows an example of the appearance of the notebook computer 131.
The notebook computer 131 includes a lower casing 133, an upper casing 135, a keyboard 137, and a display screen 139. Among these, the display screen 139 corresponds to the organic EL panel described in the embodiment.

  In addition to these, the electronic device 61 may be an audio playback device, a game machine, an electronic book, an electronic dictionary, or the like.

(D-4) Other display device examples In the above-described embodiments, the case where the invention is applied to an organic EL panel has been described.
However, the driving technique described above can also be applied to other EL display devices. For example, the present invention can also be applied to a display device in which LEDs are arranged and other display devices in which light emitting elements having a diode structure are arranged on a screen. For example, it can be applied to an inorganic EL panel.

(D-5) Others Various modifications can be considered for the above-described embodiments within the scope of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

DESCRIPTION OF SYMBOLS 11 Organic EL panel 21 Pixel array part 23 Write control line drive part 25 Power supply line drive part 27 Horizontal selector 29 Timing generator 255 Output buffer circuit 41 Power supply line drive part 257 Output buffer circuit

Claims (10)

A pixel array unit in which pixel circuits constituting pixels are arranged in a matrix, and a drive unit that drives the pixel array unit;
Each pixel circuit includes at least a sampling transistor, a driving transistor, a storage capacitor, and a light emitting element,
The drive unit supplies a predetermined signal to a write control line wired along a horizontal line direction to control conduction or non-conduction of the sampling transistor in each pixel circuit. And a power supply drive unit that controls power supply of a predetermined power supply voltage to the drive transistors of the pixels arranged in a horizontal line direction,
In the pixel circuits, the driving unit includes:
A first correction operation for flowing a current through the driving transistor into the storage capacitor in a state where a video signal is supplied from the signal line to the pixel circuit through the sampling transistor in the conductive state; and
After the first correction operation, a light emitting operation for passing a driving current according to the holding voltage of the holding capacitor to the light emitting element through the driving transistor,
Configured to do at least
During the period of the first correction operation , the write control line driver controls the sampling transistor from a non-conductive state to a conductive state in a state where the potential of the signal line is transitioning to the signal potential of the video signal. Is prescribed to start with
The write control line driving unit and the power supply driving unit supply the predetermined signal and the predetermined power supply voltage from both sides of the pixel array unit to drive each pixel circuit, thereby Configured to suppress variations in the correction operation period in the circuit,
Display device. The first correction operation is:
In the state in which the video signal is supplied from the signal line to the gate of the drive transistor through the sampling transistor in the conductive state, the current through the drive transistor is caused to flow into the storage capacitor, thereby the storage capacitor. In addition, it is an operation of holding the voltage based on the video signal in a state in which the driving capability of the driving transistor is reflected.
The display device according to claim 1. In the pixel circuits, the driving unit includes:
Prior to the first correction operation, an offset voltage is set in the holding capacitor so that the holding capacitor holds a voltage exceeding a threshold voltage of the driving transistor.
The display device according to claim 1. In the pixel circuits, the driving unit includes:
After setting the offset voltage in the holding capacitor, prior to the light emitting period of the light emitting element, a current through the driving transistor is caused to flow into the holding capacitor to reduce a potential difference between the gate and the source of the driving transistor. Configured to perform the second correction operation,
The start of the second correction operation is defined by the timing at which the power supply driving unit starts supplying current to the driving transistor.
The display device according to claim 3. The second correction operation is:
By flowing a current through the driving transistor into the holding capacitor, the potential difference between the gate and the source of the driving transistor is reduced, and the holding capacitor holds a voltage corresponding to the threshold voltage of the driving transistor. is there,
The display device according to claim 4. Each of the pixel circuits further includes a reset transistor for setting the offset voltage to the storage capacitor,
The driving unit further includes an offset line driving unit for controlling conduction or non-conduction of the reset transistor of the pixel circuit by supplying a predetermined signal to an offset line wired along a horizontal line direction. Have
The offset line driving unit is also configured to drive each pixel circuit by supplying a predetermined signal to the offset line from both sides of the pixel array unit.
The display device according to claim 3. On both sides of the pixel array unit, the power supply driving unit is disposed closer to the pixel array unit than the write control line driving unit.
The display device according to claim 1. On both sides of the pixel array unit, the write control line drive unit is disposed closer to the pixel array unit than the offset line drive unit, and the power supply drive unit is connected to the write control line drive unit. Are arranged closer to the pixel array part side,
The display device according to claim 6. The end of the period of the first correction operation and the start of the light emission operation are defined by the timing at which the write control line driving unit switches the sampling transistor from a conductive state to a non-conductive state.
The display device according to any one of claims 1 to 8. The display device is a television receiver.
The display device according to any one of claims 1 to 9.