JP2010048899A - Display panel module and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving technology suitable when heightening precision or heightening a frequency of a display panel. <P>SOLUTION: A self-light emission type display panel module includes (1) a pixel array part formed by arranging in matrix state in a display domain, a pixel domain having a holding capacitor, a driving transistor and a sampling transistor, (2) the first driving part for applying a corresponding potential to a signal line, and (3) the second driving part for driving the first control line connected to a control electrode of the sampling transistor by a binary driving voltage, wherein the second driving part propagates a decline change of a driving potential at a finish time of a writing period of a signal potential corresponding to a pixel gradation to a control electrode of the driving transistor through a coupling structure formed between a control electrode of the driving transistor and the control electrode of the sampling transistor, and lowers the signal potential written just before as much as a coupling voltage portion. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The invention described in this specification relates to a driving technique of a pixel circuit that drives a current-driven self-luminous element. Note that the invention proposed in this specification also includes a display panel module and various aspects of electronic equipment on which the display panel module is mounted.

In the following, a panel structure and an example of its driving operation will be described taking an active matrix driving type organic EL panel module as an example.
FIG. 1 shows a system structure example of an organic EL panel module. The display panel 1 shown in FIG. 1 includes a pixel array unit 3, a signal line drive unit 5 that is a drive circuit thereof, and control line drive units 7 and 9.
In the pixel array unit 3, one pixel constituting the white unit is arranged with a prescribed resolution in the vertical direction and the horizontal direction in the screen.

FIG. 2 shows an arrangement example of the sub-pixels 11 constituting one pixel as a white unit. In the case of FIG. 2, one pixel is configured as an aggregate of R (red) pixel 11, G (green) pixel 11, and B (blue) pixel 11. Therefore, if the vertical resolution of the pixel array unit 3 is M and the horizontal resolution is N, the total number of sub-pixels of the pixel array unit 3 is given by M × N × 3.
FIG. 1 shows a connection relationship between the sub-pixel 11 that is the minimum unit of the pixel structure constituting the pixel array unit 3 and its drive circuit unit.

The signal line driver 5 is a drive device that supplies a signal potential Vsig corresponding to the pixel data Din to the signal line DTL. The individual signal lines DTL are arranged so as to extend in the Y direction, and 3N lines are arranged in the horizontal direction (X direction) of the screen.
The control line drive unit 7 is a drive device that controls line-sequential writing of the signal potential Vsig and the like to the sub-pixel 11 through the write control line WSL (first control line in the claims). In the case of FIG. 1, the control line drive unit 7 performs an operation of designating the write timing of the offset potential Vofs and the signal potential Vsig in a line sequence in units of horizontal lines.

The control line drive unit 9 is a drive device that switches and controls the supply and stop of the drive voltage to the sub-pixels 11 through the lighting control line LSL (second control line in the claims). Specifically, the control line drive unit 9 drives the lighting control line LSL with two values of a high drive voltage (light emission voltage) Vcc and a low drive voltage (non-light emission voltage) VSS.
Here, the write control lines WSL and the lighting control lines LSL are arranged so as to extend in the X direction, and 3M lines are arranged in the vertical direction of the screen.

  FIG. 3 shows a pixel structure of the sub-pixel 11. As shown in FIG. 3, the sub-pixel 11 includes a thin film transistor N1 (hereinafter referred to as “sampling transistor N1”), a thin film transistor N2 (hereinafter referred to as “drive transistor N2”), and a storage capacitor Cs that holds the signal potential Vsig. And an organic EL element OLED.

One main electrode of the sampling transistor N1 is connected to the signal line DTL, and the other main electrode is connected to the control electrode of the driving transistor N2. The control electrode of the sampling transistor N1 is connected to the write control line WSL.
One main electrode of the drive transistor N2 is connected to the lighting control line LSL, and the other main electrode is connected to the anode side of the organic EL element OLED.

In the case of FIG. 3, the thin film transistors are all assumed to be N-channel type. Incidentally, in FIG. 3, the parasitic capacitance Csub formed between the capacitance component Coled of the organic EL element OLED and the substrate is also indicated by a broken line.
JP 2003-271095 A JP 2003-255897 A JP 2005-173434 A JP 2006-215213 A

  FIG. 4 shows an example of the driving operation of the sub-pixel 11 described above. FIG. 4A shows a drive waveform of the write control line WSL. FIG. 4B shows a driving waveform of the signal line DTL. FIG. 4C shows a driving waveform of the lighting control line LSL. FIG. 4D shows a waveform of the gate potential Vg of the driving transistor N2. FIG. 4E shows a waveform of the source potential Vs of the driving transistor N2 (here, the potential of the main electrode functioning as the source electrode during the light emission operation is referred to as the source potential).

As shown in FIG. 4, the driving operation of the sub-pixel 11 is classified into a light emission period and a non-light emission period. The writing of the signal potential Vsig is performed during the non-light emission period. However, when a low-temperature polysilicon process or an amorphous silicon process is used to form the thin film transistor, characteristic variations remain in the threshold characteristic and mobility characteristic of the formed thin film transistor.
For this reason, in the case of FIG. 4, two operation periods for correcting characteristic variations are provided within one horizontal scanning period. These two operations are given in two H level periods of the write control line WSL.

  The first H level period corresponds to the threshold correction period. Before executing the threshold correction, as a preparatory operation, an operation for expanding the gate-source voltage Vgs of the thin film transistor N2 to be equal to or higher than the threshold voltage Vth (that is, an initialization operation) is executed. For this initialization operation, the lighting control line LSL is once controlled to the L level (Vss). When the initialization is completed, the gate-source voltage Vgs of the drive transistor N2 becomes wider than the threshold voltage Vth. Therefore, when the lighting control line LSL is controlled to the drive potential Vcc, the drive current flows out to the drive transistor N2, and the source potential Vs starts to rise.

  At this time, the gate potential Vg of the driving transistor N2 is fixed to the offset potential Vofs. Therefore, the source potential Vs continues to rise until the gate-source voltage Vgs of the drive transistor N2 reaches the threshold voltage Vth. Note that when the gate-source voltage Vgs of the drive transistor N2 reaches the threshold voltage Vth, the drive transistor N2 is automatically cut off. This is the threshold correction operation.

The second H level period corresponds to the mobility correction period. This mobility correction operation also serves as a signal potential Vsig write operation.
The mobility correction is executed by turning on the sampling transistor N1 in a state where the signal potential Vsig is applied to the signal line DTL. The magnitude of the mobility μ represents the current drive capability of the drive transistor N2.

  Accordingly, even when the gate-source voltage Vgs is the same, the drive current Ids of the drive transistor N2 having a high mobility μ is larger than the drive current Ids of the drive transistor N2 having a low mobility μ. Therefore, by the mobility correction, the source potential Vs is increased (the gate-source voltage Vgs is decreased) as the driving transistor N2 has a higher mobility μ, and the signal potential Vsig is the same regardless of the difference in mobility μ. For example, correction is performed so that the drive current Ids of the same magnitude flows.

Incidentally, the time t required for the mobility correction differs depending on the magnitude of the signal potential Vsig.
In general, the drive current Ids at the time of mobility correction is given by the following equation.
Ids = k · μ · {Vsig / [1+ (Vsig · k · μ · t) / C]} ² formula (1)
Here, k is a constant, and C is the total capacity of the pixel circuit (= Cs + Cloed + Csub).

At this time, the optimum mobility correction time t is given by the following equation.
t = C / (k · μ · Vsig) Equation (2)
If equation (2) is substituted into equation (1), it can be seen that the drive current Ids when the correction time is optimized is given by the following equation.
Ids = k · μ · {Vsig / 2} Equation ² (3)

This means that the optimum mobility correction time derived from calculation is given by the time required to raise the source potential Vs of the drive transistor N2 by the potential corresponding to half of the signal potential Vsig. In other words, it means that the mobility correction voltage ΔV is given by half of the signal potential Vsig.
FIG. 5 shows the relationship between the signal potential Vsig and the optimum correction time t. A curve indicated by a thick line in FIG. 5 represents the relationship between the correction voltage ΔV and the correction time when the mobility correction is optimized.

Therefore, at the time of mobility correction, the fall of the second H level period shown in FIG. 4A is changed in accordance with the curve of FIG. 5 so that the mobility correction is executed for each signal potential Vsig without excess or deficiency. I am letting.
FIG. 6 shows a specific example. FIG. 6 shows an example of a signal waveform when the signal potential Vsig is 3V. FIG. 6A shows a drive waveform of the write control line WSL. FIG. 6B shows a driving waveform of the lighting control line LSL. FIG. 6C shows a waveform of the gate potential Vg of the driving transistor N2. FIG. 6D shows a waveform of the source potential Vs of the driving transistor N2.

As shown in FIG. 6D, the source potential Vs of the driving transistor N2 rises by 1.5 V during the mobility correction period. Therefore, the gate-source voltage Vgs of the driving transistor N2 after the mobility correction is 1.5V + Vth.
With these correction operations, threshold correction and mobility correction are optimized. That is, the characteristic variation of the drive transistor N2 can be prevented from being perceived as a light emission luminance difference.

However, in recent display panels, there is a problem that sufficient time cannot be allocated to the mobility correction time. The cause is an increase in panel size and an increase in driving frequency.
As described above, the mobility correction time is determined by the magnitude of the signal potential Vsig. For this reason, as shown in FIG. 5, the mobility correction time becomes longer as the gradation is lower. If mobility correction cannot be completed for this low gradation range, the mobility correction operation is not completed.

That is, the driving time of the pixel circuit cannot be made shorter than the time required for completing mobility correction in the low gradation range.
For this reason, it is difficult to technically cope with an increase in panel size and an increase in driving frequency.

Therefore, the inventors as a self-luminous display panel module,
(A) a storage capacitor, and a drive transistor having a control electrode and one main electrode connected to the two electrodes of the storage capacitor, and supplying a drive current having a magnitude corresponding to the voltage stored in the storage capacitor to the self-luminous element; A pixel array unit having a pixel region having a sampling transistor that controls writing of a potential to the control electrode of the driving transistor, arranged in a matrix in the display region;
(B) a first driver that applies a corresponding potential to the signal line;
(C) a second drive unit for driving the first control line connected to the control electrode of the sampling transistor with a binary drive voltage at the end of the writing period of the signal potential corresponding to the pixel gradation The change in the driving potential drop is propagated to the control electrode of the driving transistor through the coupling structure formed between the control electrode of the driving transistor and the control electrode of the sampling transistor, and the signal potential written immediately before is coupled to the coupling voltage. And a second drive unit that lowers only.

In addition, the inventors as a self-luminous display panel module,
(A) a storage capacitor, and a drive transistor having a control electrode and one main electrode connected to the two electrodes of the storage capacitor, and supplying a drive current having a magnitude corresponding to the voltage stored in the storage capacitor to the self-luminous element; A pixel array unit having a pixel region having a sampling transistor that controls writing of a potential to the control electrode of the driving transistor, arranged in a matrix in the display region;
(B) a first driver that applies a corresponding potential to the signal line;
(C) When the threshold value of the driving transistor is corrected, a lower ON potential is applied to the control electrode of the sampling transistor, and when a signal potential corresponding to the pixel gradation of the driving transistor is written, the higher ON potential is applied to the control electrode of the sampling transistor. A second driving unit to be applied, which drives a drop in driving potential at the end of the signal potential writing period through a coupling structure formed between the control electrode of the driving transistor and the control electrode of the sampling transistor. Proposed is one having a second driver that propagates to the control electrode of the transistor and lowers the signal potential written immediately before it by the coupling voltage.

Note that it is desirable that the signal potential writing period T corresponding to the pixel gradation is set to be shorter than the mobility correction time length t derived by calculation for each signal potential.
The display panel module described above is a third driving unit that applies a low driving voltage or a high driving voltage to the second control line connected to the other main electrode of the driving transistor in time sequence, and does not emit light. A third driving unit that applies a low driving voltage from the start of the period to the start of the characteristic correction period of the driving transistor and further applies a high driving voltage after the start of the characteristic correction period of the driving transistor; It is desirable to have.

  The coupling structure here is preferably realized by a capacitance pattern in which the electrodes are connected to the control electrode of the driving transistor and the control electrode of the sampling transistor. Alternatively, the coupling structure here is preferably realized by a diffusion capacitor formed between the control electrode and the main electrode of the sampling transistor.

The inventors also propose an electronic device equipped with a display panel module having the above-described panel structure.
Here, the electronic device includes a display panel module, a system control unit that controls the operation of the entire system, and an operation input unit that receives an operation input to the system control unit.

  In the case of the invention proposed by the inventors, the gate-source voltage of the drive transistor is optimized by lowering the control electrode potential of the drive transistor after the start of light emission by the coupling operation.

That is, at the time of writing the signal potential, the mobility correction time is shortened by using a signal potential higher than the signal potential necessary for obtaining the potential relationship used in the light emission period, and the mobility correction amount is determined by the subsequent coupling operation. Ensures consistency with the signal potential.
In the case of this driving method, the amount of shortening of the mobility correction time can be adjusted according to the coupling amount. As a result, it is possible to cope with an increase in panel size and an increase in driving frequency.

Hereinafter, the case where the invention is applied to an active matrix driving type organic EL panel module will be described.
In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification. Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) Appearance Configuration In this specification, not only a display panel module in which a pixel array unit and a driving circuit (for example, a signal line driving unit and a control line driving unit) are formed on the same substrate using a semiconductor process, A display circuit module in which a drive circuit manufactured as an application specific IC is mounted on the same substrate as the pixel array portion is also referred to as a display panel module.

FIG. 7 shows an external configuration example of the organic EL panel module. The organic EL panel module 21 has a structure in which the counter substrate 25 is bonded to the formation region of the pixel array portion of the support substrate 23.
The support substrate 23 is made of glass, plastic or other base material. The counter substrate 25 is also made of glass, plastic or other transparent member as a base material.

The counter substrate 25 is a member that seals the surface of the support substrate 23 with a sealing material interposed therebetween.
Note that the transparency of the substrate only needs to be ensured only on the light emission side, and the other substrate side may be an impermeable substrate. In addition, the organic EL panel module 21 is provided with an FPC (flexible printed circuit) 27 for inputting external signals and driving power.

(B) Form 1
(B-1) System Configuration FIG. 8 shows a system configuration example of the organic EL panel module 31 according to this embodiment. In FIG. 8, parts corresponding to those in FIG.
The organic EL panel module 31 shown in FIG. 8 includes a pixel array unit 33, a signal line drive unit 35 that is a drive circuit thereof, and control line drive units 37 and 9.
Below, the structure of the drive circuit peculiar to a form example is demonstrated.

(A) Pixel Array Unit Also in the pixel array unit 33 according to this embodiment, one pixel constituting the white unit is arranged with a specified resolution in the vertical direction and the horizontal direction in the screen. However, in the case of this embodiment, the sub pixel 41 having the structure shown in FIG. 9 is used for one pixel constituting the white unit. In FIG. 9, parts corresponding to those in FIG.

The sub-pixel 41 includes a thin film transistor N1, a thin film transistor N2, and a signal potential Vsig.
Is comprised of a storage capacitor Cs that holds the same, a coupling capacitor Cc, and an organic EL element OLED.
The difference between the sub-pixel 41 (FIG. 9) and the sub-pixel 11 (FIG. 3) is the presence or absence of the coupling capacitor Cc. In the case of this embodiment, a coupling capacitor Cc is arranged between the gate electrode of the sampling transistor N1 and the gate electrode of the drive transistor N2.

  Due to the presence of this coupling capacitor Cc, the potential change when the write control line WSL falls can be propagated to the gate electrode wiring of the drive transistor N2. That is, the signal potential Vsig written by the second ON operation of the sampling transistor N1 can be lowered by the coupling voltage.

(B) Configuration of Signal Line Driver The signal line driver 35 is a drive device that supplies a signal potential Vsig corresponding to the pixel data Din to the signal line DTL.
FIG. 10 shows an internal configuration example of the signal line driving unit 35. The signal line drive unit 35 includes a shift register 51, a latch unit 53, a digital / analog conversion unit 55, and a switch 57.
The shift register 51 is a circuit device that provides the capture timing of the pixel data Din based on the clock signal CK.

The latch unit 53 is a storage circuit that captures the pixel data Din into the corresponding storage area based on the timing signal supplied from the shift register 51.
The digital / analog conversion circuit 55 is a circuit device that converts the pixel data Din captured by the latch unit 53 into an analog signal voltage Vsig. The conversion characteristic of the digital / analog conversion circuit 55 is defined by the H level reference potential VrefH and the L level reference potential VrefL. In the case of this embodiment, as will be described later, a driving method is used in which the gate potential Vg of the driving transistor N2 is lowered through a coupling operation after the signal potential Vsig is written.

  For this reason, the digital / analog conversion circuit 55 adjusts the reference potential so as to obtain a signal amplitude assuming a voltage drop during the coupling drive. Specifically, the H level reference potential VrefH is set to a potential that is higher than the signal amplitude realized after the coupling operation by the coupling voltage. Of course, it is necessary to increase the H level reference potential VrefH as the coupling voltage increases.

  FIG. 11 shows the relationship between the input / output characteristics (shown by broken lines) applied to the signal line DTL and the input / output characteristics (shown by solid lines) finally realized through the coupling operation in this embodiment. In the case of this embodiment, the digital / analog conversion circuit 55 sets the H level reference potential VrefH to 8V so that the same signal amplitude as when the 7V signal amplitude is applied is finally obtained.

As described above, since the signal amplitude of the signal potential Vsig applied to the signal line DTL is larger than the signal amplitude finally realized, the time required for mobility correction is also the movement when the coupling operation is not combined. Less than the degree correction time. In particular, the effect of shortening the mobility correction period in the low gradation range is increased.
The switch 57 is a circuit device that selectively outputs either the signal potential Vsig corresponding to the pixel gradation or the offset potential Vofs for threshold correction to the corresponding signal line DTL. Specifically, the signal potential Vsig is output only during the writing and mobility correction period of the signal potential Vsig.

(C) Configuration of First Control Line Drive Unit The control line drive unit 37 transmits the signal potential Vsig to the sub-pixel 41 through the write control line WSL.
It is a drive device that controls writing such as line-sequentially.
FIG. 12 shows a partial configuration example of the control line drive unit 37. Note that the configuration shown in FIG. 12 is a configuration corresponding to one horizontal line. Therefore, circuits of the configuration shown in FIG. 12 are arranged in the vertical direction in the screen by the number of vertical resolutions.

  In the case of FIG. 12, the control line drive unit 37 connects one main electrode of the P-channel type thin film transistor P11 to the power supply line Vcc1, and connects the other main electrode to the write control line WSL. One main electrode of an N-channel type thin film transistor N11 is connected to the write control line WSL. Note that the other main electrode of the N-channel thin film transistor N11 is connected to the ground power supply VSS.

Incidentally, a common control signal line Scnt1 is connected to the gate electrode of the P-channel type thin film transistor P11 and the gate electrode of the N-channel type thin film transistor N11. Since these two thin film transistors have different channel characteristics, when one is on, the other is off. That is, complementary operations are performed.
In the case of this embodiment, the potential of the control signal line Scnt1 is binary controlled through the output pulse of the corresponding output stage in the shift register located in the previous stage.

As described above, the control line driving unit 37 operates so as to give two H level periods in one horizontal scanning period of the non-light emitting period. Among these, the second H level period is used for the mobility correction period.
Therefore, the time required for charging the storage capacitor Cs with a voltage corresponding to half of the applied signal potential Vsig is the time required for mobility correction. However, in the case of this embodiment, the potential of the signal potential Vsig is set to be high assuming a drop due to coupling driving. Therefore, the second H level period by the control line driving unit 37 is set as a time necessary for charging (signal potential Vsig−coupling voltage) / 2.

FIG. 13 shows the shape of the mobility correction curve used in this embodiment by a bold line. In the case of FIG. 13, it is assumed that the maximum amplitude of the signal potential Vsig applied to the signal line DTL is 8V and the voltage drop due to coupling driving is 1V.
Therefore, in FIG. 13, even when the signal potential Vsig applied to the signal line DTL is 8V, the time required for the mobility correction amount to transition to 3.5V becomes the optimum value of the mobility correction time.

Similarly, even when the signal potential Vsig applied to the signal line DTL is 7V, the time required for the mobility correction amount to transition to 3V becomes the optimum value of the mobility correction time.
Even when the signal potential Vsig applied to the signal line DTL is 6V, the time required for the mobility correction amount to transition to 2.5V becomes the optimum value of the mobility correction time.
Even when the signal potential Vsig applied to the signal line DTL is 5V, the time required for the mobility correction amount to transition to 2V becomes the optimum value of the mobility correction time.

In addition, even when the signal potential Vsig applied to the signal line DTL is 4V, the time required for the mobility correction amount to transition to 1.5V becomes the optimum value of the mobility correction time.
Even when the signal potential Vsig applied to the signal line DTL is 3V, the time required for the mobility correction amount to transition to 1V is the optimum value of the mobility correction time.
Even when the signal potential Vsig applied to the signal line DTL is 2V, the time required for the mobility correction amount to transition to 0.5V becomes the optimum value of the mobility correction time.

A thick line connecting these optimum values is a drive waveform to be applied when the control line drive unit 37 ends the mobility correction.
As can be seen from the mobility correction curve shown in FIG. 13, it can be seen that the mobility correction time corresponding to each signal potential Vsig is shorter than the mobility correction curve described in FIG.
For example, paying attention to the case where the signal potential Vsig for realizing the light emission luminance is 2 V, it can be seen that the mobility correction time, which was 300 μs in the case of FIG. 5, has been shortened to about 0.9 μs.

In FIG. 5, when the signal potential Vsig of 2V is applied, the time for the correction voltage to reach 1V is obtained as the mobility correction time. On the other hand, in FIG. 13, considering the coupling drive of 1V, the time when the correction voltage reaches 1V is obtained as the mobility correction time when the signal potential Vsig of 3V is applied.
As described above, the shortening effect of the correction time is about 2 μs, and the shortening effect as much as 70% is recognized in the 100-minute display.

  In the case of this embodiment, the difference in mobility correction time due to the difference in signal potential Vsig is very small and can be regarded as almost the same. In fact, the difference in correction time is about 300 ns at the maximum. With this time difference, a similar mobility correction curve can be realized by the transient of the drive pulse. For this reason, in the case of this embodiment, the falling waveform of the second drive pulse is also a rectangular wave.

(D) Configuration of Second Control Line Drive Unit The control line drive unit 9 is a drive device that controls the supply and stop of drive power to the sub-pixels 41 line-sequentially through the lighting control line LSL.
In FIG. 14, the example of a partial structure of the control line drive part 9 is shown. Note that the configuration shown in FIG. 14 is a configuration corresponding to one horizontal line. Accordingly, circuits having the configuration shown in FIG. 14 are arranged in the vertical direction in the screen by the number of vertical resolutions.

  In the case of FIG. 14, the second control line drive unit 9 connects one main electrode of the P-channel type thin film transistor P21 to the power supply line Vcc2, and connects the other main electrode to the lighting control line LSL. One main electrode of an N-channel thin film transistor N21 is connected to the lighting control line LSL. Note that the other main electrode of the N-channel thin film transistor N21 is connected to the ground power supply VSS.

Incidentally, a common control signal line Scnt2 is connected to the gate electrode of the P-channel type thin film transistor P21 and the gate electrode of the N-channel type thin film transistor N21. Since these two thin film transistors have different channel characteristics, when one is on, the other is off. That is, complementary operations are performed.
In the case of this embodiment, the potential of the control signal line Scnt2 is binary controlled through the output pulse of the corresponding output stage in the shift register located in the previous stage.

(B-2) Drive Operation Hereinafter, a drive operation example of the organic EL panel module 31 according to this embodiment will be described.
FIG. 15 shows a change in internal potential when focusing on a certain sub-pixel 41. FIG. 15A shows a drive waveform of the write control line WSL. FIG. 15B shows a driving waveform of the signal line DTL. FIG. 15C shows a driving waveform of the lighting control line LSL. FIG. 15D is a waveform showing a change in the gate potential Vg of the drive transistor N2. FIG. 15E is a waveform showing the potential change of the source potential Vs of the drive transistor N2.

(A) Initialization Operation When the light emission period ends and the non-light emission period starts, the initialization operation of the sub-pixel 41 is executed in preparation for the new writing of the signal potential Vsig. At this time, the potential of the lighting control line LSL is controlled to the ground potential (that is, VSS).
FIG. 16 shows an equivalent circuit of the sub-pixel 41 during this operation. As shown in FIG. 16, the sampling transistor N1 is off-controlled.

  At this time, the voltage between the gate electrode of the drive transistor N2 and the lighting control line LSL is larger than the threshold voltage Vth. For this reason, the driving transistor N2 is turned on, and the charge held in the holding capacitor Cs is drawn out. Along with this charge extraction, the source potential Vs of the drive transistor N2 (the potential on the connection side with the organic EL element OLED) becomes the ground potential VSS. In addition, the gate potential Vg of the drive transistor N2 also decreases so as to be dragged by the potential decrease of the source potential Vs.

(B) Threshold correction preparation and threshold correction operation When the initialization operation is completed, the sampling transistor N1 is turned on, and the offset potential Vofs as the reference potential is applied to the gate electrode of the drive transistor N2. FIG. 17 shows an equivalent circuit of the sub-pixel 41 at this time. At this time, the storage capacitor Cs is controlled to a state where a voltage given by Vofs−VSS is applied. This voltage is wider than the threshold voltage Vth (N2) of the driving transistor N2. This potential state completes the threshold correction preparation operation.

  In this potential state, the potential of the lighting control line LSL is switched to the light emission potential Vcc2 corresponding to the intermediate potential of the three potentials to be applied. FIG. 18 shows an equivalent circuit of the sub-pixel 41 at this time. At this time, the drain-source voltage Vds of the driving transistor N2 increases. For this reason, the drive transistor N2 is turned on, a current flows from the lighting control line LSL in the direction of the storage capacitor Cs, and the charge held in the storage capacitor Cs is neutralized. Along with this, the source potential Vs of the drive transistor N2 starts to rise.

The increase in the source potential Vs stops when the voltage held in the holding capacitor Cs reaches the threshold voltage Vth (N2) of the driving transistor N2. This is because the drive transistor N2 is automatically cut off.
When the threshold correction period ends, the sampling transistor N1 is turned off as shown in FIG.

  Strictly speaking, even at the end of the threshold correction period, the gate potential Vg of the drive transistor N2 decreases through the coupling capacitor Cc. However, the drive transistor N2 is in a cutoff state. At this time, the source electrode of the drive transistor N2 (the positive electrode of the organic EL element OLED) is also in a floating state. Therefore, although the source potential Vs decreases in conjunction with the decrease in the gate potential Vg, the gate-source voltage Vgs held in the storage capacitor Cs maintains the threshold voltage Vth.

(C) Signal Potential Writing / Mobility Correction Operation When the threshold correction operation is completed, the potential of the signal line DTL is switched from the offset potential Vofs to the signal potential Vsig. Thereafter, write control line WSL is controlled to H level, and sampling transistor N1 is turned on. FIG. 20 shows an equivalent circuit of the sub-pixel 41 at this time. By the writing of the signal potential Vsig, the voltage of the storage capacitor Cs is expanded again from the threshold voltage Vth (N2), and the driving transistor N2 is controlled to be turned on.

  Thereby, supply of the drive current Ids is started. The drive current Ids flows so as to charge the capacitance Cel and the like parasitic on the organic EL element OLED. As a result, the anode potential of the organic EL element OLED (source potential Vs of the drive transistor N2) increases by the mobility correction voltage ΔV. The mobility correction time T given by the drive pulse is common to all signal potentials Vsig. However, a transient as shown in FIG. 13 appears in the actual waveform of the drive pulse due to the influence of the wiring capacity or the like.

For this reason, the mobility correction time for the low luminance gradation is longer than the mobility correction time for the high luminance gradation.
In any case, the mobility correction time T used is the signal potential Vsig that is actually written.
Is shorter than the mobility correction time t required for calculation.
Further, the mobility correction voltage ΔV here takes a value smaller than half of the signal potential Vsig that is actually applied in consideration of the coupling operation to be executed subsequently.

Needless to say, the mobility correction voltage ΔV here is determined not to exceed the threshold voltage Vth (oled) of the organic EL element OLED.
Therefore, the organic EL element OLED is not turned on during the mobility correction operation. That is, the organic EL element OLED remains unlit even during the mobility correction operation.

(D) Light emission operation (including coupling operation)
When the mobility correction operation is completed, the sampling transistor N1 is turned off. FIG. 21 shows an equivalent circuit of the sub-pixel 41 at this time.
At this time, the drive pulse of the write control line WSL changes from the H level (Vcc1) to the L level (VSS).

By this potential change, the sampling transistor N1 is turned off, and the electrical connection between the signal line DTL and the gate electrode of the driving transistor N2 is disconnected.
At the same time, the potential change (= Vcc1−VSS) during the off-control of the sampling transistor N1 propagates to the gate potential Vg of the drive transistor N2 in the floating state through the coupling capacitor Cc.

That is, the gate potential Vg of the driving transistor N2 drops from the signal potential Vsig to Vsig−ΔVg. On the other hand, the source potential Vs of the driving transistor N2 is fixedly given by a potential charged in a capacitor or the like parasitic on the organic EL element OLED.
Therefore, by the coupling operation, the gate-source voltage Vgs ′ of the driving transistor N2 changes from Vgs when the signal potential Vsig is written to Vgs−ΔVg.

When this coupling operation is completed, the anode potential of the organic EL element OLED continues to rise through charging of parasitic capacitance or the like by the drive current Ids ′ supplied through the drive transistor N2.
As the anode potential increases, the source potential Vs of the drive transistor N2 increases. As the source potential Vs of the driving transistor N2 increases, the gate potential Vg of the driving transistor N2 also increases due to the bootstrap operation.

FIG. 22 shows an equivalent circuit of the sub-pixel 41 at this time. Thereafter, when the source potential Vs reaches the threshold voltage Vth (oled) of the organic EL element OLED, the organic EL element OLED is turned on, and the driving current determined according to the voltage Vgs ′ held in the holding capacitor Cs. Light emission is started at a luminance level corresponding to Ids ′.
In FIG. 22, the gate potential Vg of the drive transistor N2 at the start of light emission is Vx.

  Finally, with reference to FIG. 23, it will be described that the potential relationship after the coupling operation is appropriate. FIG. 23A shows a drive waveform of the write control line WSL, and FIG. 23B shows a drive waveform of the lighting control line LSL. FIG. 23C shows the waveform of the potential change of the gate potential Vg of the driving transistor N2, and FIG. 23D shows the waveform of the potential change of the source potential Vs of the driving transistor N2.

Note that FIG. 23 shows the case where the actually supplied signal potential Vsig is 4V (when the signal potential Vsig to be substantially realized is 3V).
As shown in FIG. 23, the mobility correction time T is set shorter than the calculated mobility correction time t. Therefore, the calculated mobility correction voltage when the signal potential Vsig is 4V is 2V. In this example, the mobility correction period ends when the mobility correction voltage reaches 1.5V. At this time, the gate-source voltage Vgs of the driving transistor N2 is 2.5V + Vth.

In this state, the potential change of the write control line WSL is propagated to the gate electrode of the drive transistor N2 by capacitive coupling. In the case of this embodiment, it is 1 V regardless of the magnitude of the signal potential Vsig.
Then, the gate potential Vg of the drive transistor N2 is lowered to 3V due to the influence of the coupling drive.

That is, the gate-source voltage Vgs of the driving transistor N2 is reduced to 1.5V + Vth.
This potential state is exactly the same as that in the case where the mobility correction operation is executed in a state where the signal potential Vsig of 3 V is applied to the signal line DTL from the beginning (FIG. 6).

(B-3) Effect of Embodiment In the case of this embodiment, the coupling capacitor Cc is connected between the gate electrodes of the sampling transistor N1 and the drive transistor N2, and the holding capacitor Cs is held by the potential change at the end of the mobility correction period. A driving method for reducing the voltage Vgs is adopted.
By adopting this driving method, the signal amplitude applied to the signal line DTL can be made larger than the signal amplitude when the coupling operation is not considered. As a result, the mobility correction time can be shortened compared to the case where the coupling operation is not employed.

  In addition, the mobility correction voltage corresponding to the potential relationship after the coupling operation can be smaller than the calculated mobility correction voltage for the signal potential Vsig applied to the signal line DTL. For this reason, the mobility correction time for obtaining the required mobility correction voltage is further shortened. As a result, the mobility correction time can be greatly shortened as compared with the case where the coupling operation is not employed.

As a result, it is possible to realize an organic EL panel that can easily cope with an increase in panel size and an increase in driving frequency.
In addition, in the case of the mobility correction method adopting the coupling operation in the minus direction (the direction in which the gate-source voltage Vgs is compressed), it is only necessary to generate a rectangular pulse, and the circuit configuration of the control line driving unit 37 is It can be simplified. Therefore, the control line driving unit 37 can be formed in the pixel array unit 33 on the same panel as the sub-pixel using the same process.
Thereby, further cost reduction and power consumption reduction of the organic EL panel can be realized.

(C) Form example 2
(C-1) System Configuration FIG. 24 shows a system configuration example of the organic EL panel module 61 according to the second embodiment. In FIG. 24, the same reference numerals are given to the corresponding parts in FIG. 1 and FIG.
An organic EL panel module 61 shown in FIG. 24 includes a pixel array unit 3, a signal line drive unit 35 that is a drive circuit thereof, and control line drive units 63 and 9.
Below, the structure of the drive circuit peculiar to a form example is demonstrated.

(A) Pixel Array Unit The pixel array unit 3 according to this embodiment is the same as the pixel array unit 3 having the conventional structure described in FIG. Therefore, the sub-pixel 11 has the same pixel structure as shown in FIG. 3, as shown in FIG. That is, the subpixel 11 includes a thin film transistor N1, a thin film transistor N2, a storage capacitor Cs that holds the signal potential Vsig, and an organic EL element OLED.

(B) Configuration of Signal Line Drive Unit The signal line drive unit 35 described in the first embodiment is used. This is also in the case of this embodiment in order to superimpose a negative coupling voltage on the gate potential Vg of the drive transistor N2 at the end of the mobility correction operation. For this reason, also in the case of this embodiment, the signal line driving unit 35 in which the signal amplitude of the signal potential Vsig applied to the signal line DTL is expanded by a preset coupling voltage is used.

(C) Configuration of First Control Line Driving Unit The control line driving unit 63 transmits the signal potential Vsig to the sub-pixel 11 through the write control line WSL.
It is a drive device that controls writing such as line-sequentially. However, in the case of this embodiment, the control line drive unit 63 controls driving of the write control line WSL with a ternary potential. The ternary potential is a ternary value of an off potential VSS, a lower on potential Vcc11, and a higher on potential Vcc12.

FIG. 26 shows a partial configuration example of the first control line driving unit 63. Note that the configuration shown in FIG. 26 corresponds to one horizontal line. Accordingly, in the vertical direction in the screen, circuits having the configuration shown in FIG. 26 are arranged by the number of vertical resolutions.
The first control line driving unit 63 shown in FIG. 26 connects one main electrode of the P-channel type thin film transistor P31 to the scan power supply line Vccp and connects the other main electrode to the write control line WSL.

One main electrode of an N-channel type thin film transistor N31 is connected to the write control line WSL. Note that the other main electrode of the N-channel thin film transistor N31 is connected to the ground power supply VSS.
A common control signal line Scnt11 is connected to the gate electrode of the P-channel type thin film transistor P31 and the gate electrode of the N-channel type thin film transistor N31. Since these two thin film transistors have different channel characteristics, when one is on, the other is off. That is, complementary operations are performed.

In the case of this embodiment, the potential of the control signal line Scnt11 is binary controlled through the output pulse of the corresponding output stage in the shift register located in the previous stage.
On the other hand, the potential of the scan power supply line Vccp is also binary controlled through the output pulse of the corresponding output stage in the shift register located in the previous stage.

  In this embodiment, driving is performed with two values of a low ON potential Vcc11 for the threshold correction period and a high ON potential Vcc12 (> Vcc11) for the mobility correction period. Of course, both potentials are sufficient for the on-control of the sampling transistor N1. By the way, the two types of on-potentials are used properly in order to increase the potential change of the write control line WSL at the end of the mobility correction period.

  By increasing the potential difference between the on potential and the off potential, a method of propagating the potential change of the write control line WSL to the gate electrode wiring of the drive transistor N2 while using the parasitic capacitance for the sampling transistor N1 is adopted. For this reason, in this embodiment, the coupling capacitor Cc is not arranged. Of course, the coupling capacitor Cc can be arranged, but in this case, the size of the coupling capacitor Cc can be made smaller than that of the first embodiment. Of course, since the same operation principle as in Embodiment 1 is used, the application period (mobility correction period) of the higher on-potential Vcc12 is significantly shorter than that in the case where the minus-direction coupling operation is not employed. .

(D) Configuration of Second Control Line Drive Unit The control line drive unit 9 used in the first embodiment is used. Also in this embodiment, the control line drive unit 9 controls the supply and stop of the drive power to the sub-pixels 11 line-sequentially through the lighting control line LSL.

(C-2) Drive Operation Hereinafter, a drive operation example of the organic EL panel module 61 according to this embodiment will be described.
FIG. 27 shows a change in internal potential when focusing on a certain sub-pixel 11. FIG. 27A shows a drive waveform of the write control line WSL. FIG. 27B shows a driving waveform of the signal line DTL. FIG. 27C shows a driving waveform of the lighting control line LSL.

FIG. 27D is a waveform showing a change in the gate potential Vg of the driving transistor N2. FIG. 27E is a waveform showing changes in the source potential Vs of the drive transistor N2.
In this embodiment, the basic operation is the same as that in Embodiment 1.

(A) Initialization Operation When the light emission period ends and the non-light emission period starts, the initialization operation of the sub-pixel 11 is executed in preparation for the new writing of the signal potential Vsig. At this time, the potential of the lighting control line LSL is controlled to the ground potential (that is, VSS).

  At this time, the voltage between the gate electrode of the drive transistor N2 and the lighting control line LSL is larger than the threshold voltage Vth. For this reason, the driving transistor N2 is turned on, and the charge held in the holding capacitor Cs is drawn out. Along with this charge extraction, the source potential Vs of the drive transistor N2 (the potential on the connection side with the organic EL element OLED) becomes the ground potential VSS. In addition, the gate potential Vg of the drive transistor N2 also decreases so as to be dragged by the potential decrease of the source potential Vs.

(B) Threshold correction preparation and threshold correction operation When the initialization operation is completed, the sampling transistor N1 is turned on, and the offset potential Vofs as the reference potential is applied to the gate electrode of the drive transistor N2. That is, the lower potential ON potential Vcc11 is applied to the write control line WSL. At this time, the storage capacitor Cs is controlled to a state where a voltage given by Vofs−VSS is applied. This voltage is wider than the threshold voltage Vth (N2) of the driving transistor N2. This potential state completes the threshold correction preparation operation.

  In this potential state, the potential of the lighting control line LSL is switched to the light emission potential Vcc2 corresponding to the intermediate potential of the three potentials to be applied. At this time, the drain-source voltage Vds of the driving transistor N2 increases. For this reason, the drive transistor N2 is turned on, a current flows from the lighting control line LSL in the direction of the storage capacitor Cs, and the charge held in the storage capacitor Cs is neutralized. Along with this, the source potential Vs of the drive transistor N2 starts to rise.

The increase in the source potential Vs stops when the voltage held in the holding capacitor Cs reaches the threshold voltage Vth (N2) of the driving transistor N2. This is because the drive transistor N2 is automatically cut off.
When the threshold correction period ends, the sampling transistor N1 is turned off. That is, the off potential VSS is applied to the write control line WSL.

  Strictly speaking, even at the end of this threshold correction period, the potential change of the write control line WSL propagates to the gate potential Vg of the drive transistor N2 through the parasitic capacitance of the sampling transistor N1. However, the potential difference between the lower ON potential Vcc11 and the OFF potential VSS is small. For this reason, the influence can be almost ignored.

(C) Signal Potential Writing / Mobility Correction Operation When the threshold correction operation is completed, the potential of the signal line DTL is switched from the offset potential Vofs to the signal potential Vsig. Thereafter, the write control line WSL is controlled to the high potential ON potential Vcc12, and the sampling transistor N1 is controlled to be ON.
By the writing of the signal potential Vsig, the voltage of the storage capacitor Cs is expanded again from the threshold voltage Vth (N2), and the driving transistor N2 is controlled to be turned on.

  Thereby, supply of the drive current Ids is started. The drive current Ids flows so as to charge the capacitance Cel and the like parasitic on the organic EL element OLED. As a result, the anode potential of the organic EL element OLED (source potential Vs of the drive transistor N2) increases by the mobility correction voltage ΔV. The mobility correction time T given by the drive pulse is common to all signal potentials Vsig. However, a transient as shown in FIG. 13 appears in the actual waveform of the drive pulse due to the influence of the wiring capacity or the like.

For this reason, the mobility correction time for the low luminance gradation is longer than the mobility correction time for the high luminance gradation. Of course, the mobility correction time is set to be optimized for the signal potential Vsig after the coupling drive in the minus direction.
Accordingly, the mobility correction time T here can be shorter than the mobility correction time t obtained by calculation for the signal potential Vsig actually written.
Further, the mobility correction voltage ΔV here takes a value smaller than half of the signal potential Vsig that is actually applied in consideration of the coupling operation to be executed subsequently.

Needless to say, the mobility correction voltage ΔV here is determined not to exceed the threshold voltage Vth (oled) of the organic EL element OLED.
Therefore, the organic EL element OLED is not turned on during the mobility correction operation. That is, the organic EL element OLED remains unlit even during the mobility correction operation.

(D) Light emission operation (including coupling operation)
When the mobility correction operation is completed, the sampling transistor N1 is turned off. That is, the applied potential of the write control line WSL is controlled to be switched from the higher potential ON potential Vcc12 to the OFF potential VSS. FIG. 28 shows an equivalent circuit of the sub-pixel 11 at this time.
The potential change at this time is much larger than at the end of the threshold correction operation. Of course, the higher potential ON potential Vcc12 is determined in consideration of the magnitude of the coupling voltage desired to propagate.

By this potential change, the sampling transistor N1 is turned off, and the electrical connection between the signal line DTL and the gate electrode of the driving transistor N2 is disconnected.
At the same time, the potential change (= Vcc12−VSS) during the OFF control of the sampling transistor N1 propagates to the gate potential Vg of the driving transistor N2 in the floating state through the parasitic capacitance of the sampling transistor N1.

That is, the gate potential Vg of the driving transistor N2 drops from the signal potential Vsig to Vsig−ΔVg. On the other hand, the source potential Vs of the driving transistor N2 is fixedly given by a potential charged in a capacitor or the like parasitic on the organic EL element OLED.
Therefore, by the coupling operation, the gate-source voltage Vgs ′ of the driving transistor N2 changes from Vgs when the signal potential Vsig is written to Vgs−ΔVg.

When this coupling operation is completed, the anode potential of the organic EL element OLED continues to rise through charging of parasitic capacitance or the like by the drive current Ids ′ supplied through the drive transistor N2.
As the anode potential increases, the source potential Vs of the drive transistor N2 increases. As the source potential Vs of the driving transistor N2 increases, the gate potential Vg of the driving transistor N2 also increases due to the bootstrap operation.

  Thereafter, when the source potential Vs reaches the threshold voltage Vth (oled) of the organic EL element OLED, the organic EL element OLED is turned on, and the driving current determined according to the voltage Vgs ′ held in the holding capacitor Cs. Light emission is started at a luminance level corresponding to Ids ′.

(C-3) Effect of Embodiment In the case of this embodiment, the higher-side on potential Vcc12 applied to the write control line WSL is increased during the mobility correction period. That is, as described above, the potential change when switching from the on potential Vcc12 to the off potential VSS is increased. As a result, even when the coupling capacitor Cc is not provided, the same effect as that of the first embodiment can be realized.

That is, the mobility correction time can be greatly shortened compared to the case where the coupling operation is not employed.
As a result, it is possible to realize an organic EL panel that can easily cope with an increase in panel size and an increase in driving frequency.

  In addition, in the case of the mobility correction method adopting the coupling operation in the minus direction (the direction in which the gate-source voltage Vgs is compressed), it is only necessary to generate a rectangular pulse, and the circuit configuration of the control line driving unit 63 is reduced. It can be simplified. Therefore, the control line driving unit 63 can be formed in the pixel array unit 3 on the same panel as the sub-pixel 11 using the same process. Thereby, further cost reduction and power consumption reduction of the organic EL panel can be realized.

In the case of this embodiment, since it is not necessary to arrange the coupling capacitor Cc in the sub-pixels 11 constituting the pixel array unit 3, the pixel size can be reduced. Therefore, it is advantageous for high definition.
In this embodiment, the coupling capacitor Cc is not used. Needless to say, the coupling capacitor Cc can be combined.

(D) Other configuration examples (D-1) Other configuration examples of the control line drive unit (1)
In the above-described second embodiment, two types of on potentials to be applied to the write control line WSL are prepared. However, the ON potential may be set to only the higher potential ON potential Vcc12.

  However, the ON potential Vcc12 is required to apply a negative coupling voltage to the gate electrode wiring of the drive transistor N2 through the parasitic capacitance of the sampling transistor N1, as described above. FIG. 29 shows a corresponding operation example. 29A to 29E correspond to FIGS. 27A to 27E. Note that this driving method is advantageous for simplifying the circuit configuration of the control line driving unit 37. Of course, also in this case, the coupling capacitance Cc can be combined.

(D-2) Another configuration example of the control line driving unit (2)
In the case of the above-described second embodiment, the control line driving unit 63 having the circuit configuration shown in FIG. 26 is exemplified as the driving unit for the write control line LSL.
However, similar control can be realized by other circuit configurations. FIG. 30 shows another configuration example of the control line drive unit 63 suitable for driving the write control line WSL.

The control line driving unit 63 shown in FIG. 30 employs a configuration in which one switch (thin film transistor) is arranged for each of the three potentials VSS, Vcc11, and Vcc12 applied to the write control line WSL.
In the case of the control line drive unit 63 shown in FIG. 30, P-channel type thin film transistors P41 and P42 are connected in parallel to the write control line WSL.
Among these, one main electrode of the thin film transistor P41 is connected to the power supply line to which the lower ON potential Vcc11 is applied, and the other main electrode is connected to the write control line WSL. Further, one main electrode of the thin film transistor P42 is connected to a power supply line to which a higher on potential Vcc12 is applied, and the other main electrode is connected to the write control line WSL.

An N-channel type thin film transistor N41 is connected in series to these two thin film transistors P41 and P42, and the other main electrode is connected to the ground power supply VSS.
In the case of the control line drive unit 63 shown in FIG. 30, dedicated control signal lines Scnt21, Scnt22, and Scnt23 are connected to the gate electrodes of the individual thin film transistors P41, P42, and N41, respectively.
Incidentally, the control signal line Scnt21 is connected to the gate electrode of the thin film transistor P41, the control signal line Scnt22 is connected to the gate electrode of the thin film transistor P42, and the control signal line Scnt23 is connected to the gate electrode of the thin film transistor N41.

The potentials of these control signal lines Scnt21, Scnt22, and Scnt23 are also binary controlled through the output pulse of the corresponding output stage in the shift register located in the preceding stage.
In the case of this circuit configuration, first, while the control signal line Scnt23 is at the H level, the N-channel thin film transistor N41 is turned on to control the potential of the write control line WSL to the L level.

  Next, the control signal line Scnt23 is switched to the L level, and in conjunction with this switching, the control signal line Scnt21 is changed from the H level to the L level. At this time, the P-channel type thin film transistor P41 is turned on, and a lower ON potential Vcc11 is output to the write control line WSL.

  Subsequently, the control signal line Scnt23 is again switched to the H level, and in conjunction with this switching, the control signal line Scnt22 changes from the H level to the L level. At this time, the P-channel type thin film transistor P42 is turned on, and a high ON potential Vcc12 is output to the write control line WSL. By this operation, the same potential change as the circuit configuration shown in FIG. 26 can be realized.

(D-3) Another configuration example of the control line driving unit (3)
In the case of the embodiment described above, the falling waveform of the control pulse instructing execution of the mobility correction operation is a rectangular wave.
However, when it is desired to further improve the accuracy of mobility correction, the falling waveform of the control pulse may be controlled so that the mobility correction curve shown in FIG. 13 is obtained. Hereinafter, a configuration example of the control line drive unit 37 that can generate a drive pulse with this type of correction curve will be described.

  FIG. 31 shows a partial configuration example of the control line drive unit 37. Note that the configuration shown in FIG. 31 corresponds to one horizontal line. Accordingly, in the vertical direction in the screen, circuits having the configuration shown in FIG. 31 are arranged by the number of vertical resolutions.

Hereinafter, this partial circuit is also referred to as a control line drive unit 37. The control line driving unit 37 includes a shift register 71, a buffer circuit composed of two-stage inverter circuits 73, 75, a level shifter 77, and an output buffer circuit composed of one-stage inverter circuit 79.
The correction curve for realizing the mobility correction time according to the signal potential Vsig is realized by the waveform level of the power supply voltage pulse WSP supplied to the inverter circuit 79.
FIG. 32 shows a waveform example of the power supply voltage pulse WSP.

As shown in FIG. 32, the portion of the mobility correction curve is set at a timing synchronized in phase with the mobility correction period of each horizontal line.
In the case of this embodiment, the shape of the mobility correction curve is set so that overcorrection is applied to the applied signal potential Vsig. That is, the shape of the mobility correction curve is set so that the correction time for each signal potential Vsig is shorter than the correction time calculated based on Equation (2).

FIG. 33 shows a configuration of a circuit device that generates the power supply voltage pulse WSP supplied to the control line drive unit 37.
The power supply voltage pulse WSP is generated by the timing generator 81 and the drive power supply generator 83. The timing generator 81 is a circuit device that supplies drive pulses (rectangular waves) not only to the control line drive unit 37 but also to other control line drive units. The falling timing of the drive pulse is set to a timing delayed by a predetermined time with respect to the mobility correction start timing.

The drive power generation unit 83 is a circuit device that generates a drive voltage pulse WSP in which the waveform at the time of falling is bent in two stages based on a rectangular-wave drive pulse.
FIG. 34 shows a circuit example of the drive power generation unit 83. A drive power generation unit 83 shown in FIG. 34 is a configuration example of a circuit device that generates a pseudo drive voltage pulse WSP that approximates a mobility correction curve. The drive power supply generation unit 83 shown in FIG. 34 includes two transistors, one capacitor, three fixed resistors, and two variable resistors.

  The drive power supply generation unit 83 performs analog processing on the drive pulse, and generates a power supply voltage pulse WSP whose waveform at the time of falling is bent in two stages. That is, the power supply voltage pulse WSP having a large inclination angle of the first-stage falling waveform and a small inclination of the second-stage falling waveform is generated. Of course, if a circuit configuration capable of generating a waveform that falls in multiple stages is employed, the power supply voltage pulse WSP closer to the ideal mobility correction curve can be generated.

(D-4) Other Configurations of Signal Line Drive Unit In the description of the above-described embodiment, the signal amplitude of the digital / analog conversion circuit 55 of the signal line drive unit 35 is assumed assuming a coupling voltage in the minus direction. It was made larger than the signal amplitude to be finally realized. However, the configuration of the signal line driving unit 35 can use the signal line driving unit 5 that is currently generally used as it is.

(D-5) Other structure of sub-pixel (1)
In the case of the first embodiment described above, the case where the coupling capacitor Cc is physically formed between the gate electrode and the main electrode of the sampling transistor N1 has been described.
However, the same operating state can be realized by increasing the parasitic capacitance of the sampling transistor N1.

  In general, when the ratio of the channel width W to the channel length L of the thin film transistor (that is, W / L) is increased, the parasitic capacitance between the gate electrode and the main electrode can be increased. Therefore, by increasing at least the W / L of the sampling transistor N1, the coupling capacitance Cc can be eliminated from within the sub-pixel. FIG. 35 illustrates a structural example of a thin film transistor included in a subpixel.

FIG. 35A is a diagram illustrating a transistor size example of the driving transistor N2, and FIG. 35B is a diagram illustrating a transistor size example of the sampling transistor N1.
FIG. 35 shows an example in which the transistor size of the sampling transistor N1 is larger than the transistor size of the drive transistor N2.

(D-6) Other structure of sub-pixel (2)
In the case of the first embodiment described above, the case where the coupling capacitor Cc is physically formed between the gate electrode and the main electrode of the sampling transistor N1 has been described.
However, the same operating state can be realized by increasing the parasitic capacitance of the sampling transistor N1.

  For example, the parasitic capacitance can be increased by increasing the overlap length between the gate electrode and the drain / source electrode constituting the sampling transistor N1. FIG. 36 illustrates a cross-sectional structure example corresponding to a bottom-gate thin film transistor.

  The sampling transistor N1 has a structure in which the surface of a gate electrode 93 formed on the surface of an insulating substrate (for example, a glass panel) 91 is covered with an interlayer insulating film, and further, a channel region 95, a source region 97, and a drain region 99 are formed on the upper surface. have. Note that the metal wiring 101 is connected to the source region 97, and the metal wiring 103 is connected to the drain region 99. Here, each overlap amount of the channel region 95 and the metal wiring is an overlap length. Of course, it is only necessary to form an overlap only in the main electrode region on the side connected to the driving transistor N2.

(D-7) Other Pixel Structures In the case of the first and second embodiments, the case where the number of thin film transistors constituting the sub-pixel is two has been described.
However, the sub-pixel configuration can be applied to cases other than these. For example, the number of thin film transistors may be three or more.

FIG. 37 shows a structural example of a subpixel including four thin film transistors. Note that, in FIG. 37, the same reference numerals are given to the portions corresponding to FIG. There are three new components in the subpixel shown in FIG.
The first new component is that driving power is supplied through the fixed power line VCC. The second new component is that a lighting control transistor N51 is connected in series between the fixed power supply line VCC and the drive transistor N2.

  In the case of FIG. 37, the lighting control transistor N51 is formed of an N-channel thin film transistor. The lighting control transistor N51 is controlled to be opened / closed by a lighting control line LSL, and driving power is supplied from the fixed power line VCC during on-control, and driving power supply is stopped during off-control. The off control here is selected when the light is turned off during the non-light emitting period and the light emitting period.

  The third new component is a reset transistor N53 connected in parallel with the organic EL element OLED. The reset transistor N53 is also formed of an N-channel thin film transistor. The reset transistor N53 is controlled to be opened and closed by a reset control line RSL. The reset transistor N53 is on-controlled during initialization, and is off-controlled during other periods.

  FIG. 38 shows a change in internal potential corresponding to this pixel structure. Incidentally, FIG. 38A shows a drive waveform of the write control line WSL. FIG. 38B shows a driving waveform of the signal line DTL. FIG. 38C shows a driving waveform of the lighting control line LSL. FIG. 38D shows a drive waveform of the reset control line RSL. FIG. 38E is a waveform showing a change in the gate potential Vg of the drive transistor N2. FIG. 38F is a waveform showing changes in the source potential Vs of the drive transistor N2.

The basic driving operation is the same as that of the second embodiment. The unique operation is the operation of the lighting control transistor N51 related to the initialization operation and the connection between the drive transistor N2 and the fixed power supply line VCC.
Here, the driving operation will be described focusing on the differences. For example, at the time of initialization, the lighting control transistor N51 is turned off and the reset transistor N53 is turned on. At this time, one electrode of the storage capacitor Cs is connected to the ground potential VSS, the charge held in the storage capacitor Cs is drawn to the ground potential VSS, and initialization is executed.

  When the initialization operation is completed, the lighting control transistor N51 is turned on and the reset transistor N53 is turned off. Thereafter, the operation of the equivalent circuit of the subpixel shown in FIG. 37 is the same as that of the first embodiment.

(D-8) Product Example (a) Electronic Device In the above description, the invention has been described for the organic EL panel module. However, the organic EL panel module described above is also distributed in the form of products mounted on various electronic devices. Examples of mounting on other electronic devices are shown below.

  FIG. 39 illustrates a conceptual configuration example of the electronic device 111. The electronic device 111 includes a display panel module 113 on which the drive circuit described above is mounted, a system control unit 115, and an operation input unit 117. The processing content executed by the system control unit 115 differs depending on the product form of the electronic device 111. The operation input unit 117 is a device that receives an operation input to the system control unit 115. For the operation input unit 117, for example, a switch, a button, other mechanical interfaces, a graphic interface, or the like is used.

FIG. 40 shows an example of an external appearance when the electronic device is a television receiver. A display screen 127 including a front panel 123, a filter glass 125, and the like is disposed on the front surface of the housing of the television receiver 121. The portion of the display screen 127 corresponds to the display panel module 113 in FIG.
Also, for example, a digital camera is assumed as this type of electronic apparatus. FIG. 41 shows an example of the appearance of the digital camera 131. FIG. 41A shows an example of the appearance on the front side (subject side), and FIG. 41B shows an example of the appearance on the back side (photographer side).

The digital camera 131 includes a protective cover 133, an imaging lens unit 135, a display screen 137, a control switch 139, and a shutter button 141. Of these, the display screen 137 corresponds to the display panel module 113 of FIG.
In addition, for example, a video camera is assumed as this type of electronic apparatus. FIG. 42 shows an example of the appearance of the video camera 151.
The video camera 151 includes an imaging lens 155 that images a subject in front of the main body 153, a shooting start / stop switch 157, and a display screen 159. Of these, the display screen 159 corresponds to the display panel module 113 of FIG.

Moreover, for example, a portable terminal device is assumed as this type of electronic apparatus. FIG. 43 shows an example of the appearance of a mobile phone 161 as a mobile terminal device. A cellular phone 161 illustrated in FIG. 43 is a foldable type, and FIG. 43A illustrates an appearance example in a state where the housing is opened, and FIG. 43B illustrates an appearance example in a state where the housing is folded.
The mobile phone 161 includes an upper housing 163, a lower housing 165, a connecting portion (in this example, a hinge portion) 167, a display screen 169, an auxiliary display screen 171, a picture light 173, and an imaging lens 175. Of these, the display screen 169 and the auxiliary display screen 171 correspond to the display panel module 113 of FIG.

Also, for example, a computer is assumed as this type of electronic apparatus. FIG. 44 shows an example of the appearance of a notebook computer 181.
The notebook computer 181 includes a lower casing 183, an upper casing 185, a keyboard 187, and a display screen 189. Among these, the display screen 189 corresponds to the display panel module 113 of FIG.
In addition to these, an audio playback device, a game machine, an electronic book, an electronic dictionary, and the like are assumed as electronic devices.

(D-9) Other Display Device Examples In the above-described embodiments, the case where the invention is applied to the organic EL panel module has been described.
However, the configuration of the power supply circuit described above can also be applied to other self-luminous display panel modules.
For example, the present invention can be applied to a display device in which LEDs are arranged in a matrix or a display panel module in which light emitting elements having a diode structure are arranged on a screen. For example, it can be applied to an inorganic EL panel.

(D-10) Others Various modifications can be considered for the above-described embodiments within the scope of the gist of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

It is a figure explaining the system structure of an organic electroluminescent panel module. It is a figure explaining the pixel arrangement of a sub pixel. It is a figure explaining the structural example of a sub pixel. It is a figure explaining the drive waveform example of a sub pixel. It is a figure explaining the shape of the mobility correction curve derived | led-out by calculation. It is a figure explaining the voltage change which appears between the gate-source of a drive transistor. It is a figure which shows the external appearance structural example of an organic electroluminescent panel module. It is a figure which shows the system structural example of the organic electroluminescent panel module which concerns on the example 1 of a form. It is a figure explaining the structural example of the sub pixel used in the example 1 of a form. It is a figure which shows the structural example of a signal line drive part. It is a figure explaining the relationship between the input-output characteristic (shown with a broken line) applied to a signal line, and the input-output characteristic (shown with a continuous line) implement | achieved after coupling drive. It is a figure explaining the circuit structural example of the control line drive part which drives a write-control line. It is a figure which shows the example of a shape of the mobility correction | amendment curve used in the example 1 of a form. It is a figure explaining the circuit structural example of the control line drive part which drives a lighting control line. It is a figure explaining the drive waveform example which concerns on the example 1 of a form. It is a figure which shows the equivalent circuit of the sub pixel at the time of initialization operation | movement. It is a figure which shows the equivalent circuit of the sub pixel at the time of threshold value correction preparatory operation. It is a figure which shows the equivalent circuit of the sub pixel at the time of threshold value correction | amendment operation | movement. It is a figure which shows the equivalent circuit of the sub pixel after the threshold value correction operation is completed. It is a figure which shows the equivalent circuit of a sub pixel at the time of signal potential writing and mobility correction | amendment operation | movement. It is a figure which shows the equivalent circuit of a sub pixel in case the coupling operation | movement of a minus direction is performed. It is a figure which shows the equivalent circuit of the sub pixel at the time of light emission operation | movement. It is a figure explaining the voltage change which appears between the gate-source of a drive transistor at the time of application of the drive operation concerning a form example. It is a figure which shows the system structural example of the organic electroluminescent panel module which concerns on the example 2 of a form. It is a figure explaining the structural example of the sub pixel used in the example 2 of a form. It is a figure explaining the circuit structural example of the control line drive part which drives a write-control line. It is a figure explaining the drive waveform example which concerns on the example 2 of a form. It is a figure which shows the equivalent circuit of a sub pixel in case the coupling operation | movement of a minus direction is performed. It is a figure which shows the other example of a drive waveform. It is a figure explaining the other circuit structural example of the control line drive part which drives a write-control line. It is a figure explaining the other circuit structural example of the control line drive part which drives a write-control line. It is a figure explaining the example of a waveform of a power supply voltage pulse. It is a figure which shows the structural example of the circuit device which generate | occur | produces a power supply voltage pulse. It is a figure which shows the structural example of a drive power generation part. It is a figure explaining transistor size. It is a figure explaining the amount of overlap. It is a figure explaining the other structural example of a sub pixel. It is a figure which shows the example of a drive waveform of the sub pixel shown in FIG. It is a figure which shows the example of a conceptual structure of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device.

Explanation of symbols

3 pixel array unit 31 organic EL panel module 33 pixel array unit 35 signal line drive unit 37 control line drive unit 61 organic EL panel module 63 control line drive unit

Claims (12)

A storage capacitor, a drive transistor having a control electrode and one main electrode connected to the two electrodes of the storage capacitor, and supplying a drive current having a magnitude corresponding to the voltage stored in the storage capacitor to the self-luminous element; A pixel array section in which a pixel region having a sampling transistor for controlling writing of a potential to a control electrode of the drive transistor is arranged in a matrix in the display region;
A first driver that applies a corresponding potential to the signal line;
A second driving unit for driving the first control line connected to the control electrode of the sampling transistor with a binary driving voltage, the driving potential at the end of the writing period of the signal potential corresponding to the pixel gradation; Is propagated to the control electrode of the driving transistor through a coupling structure formed between the control electrode of the driving transistor and the control electrode of the sampling transistor, and the signal potential written immediately before is coupled to the coupling voltage. A self-luminous display panel module having a second drive unit that lowers by a corresponding amount. The display panel module according to claim 1,
A display panel module in which a signal potential writing period T corresponding to a pixel gradation is set to be shorter than a mobility correction time length t derived by calculation for each signal potential. The display panel module according to claim 2,
A third driving unit for sequentially applying a low driving voltage or a high driving voltage to a second control line connected to the other main electrode of the driving transistor in a time sequence, from the start of a non-light emitting period; A display panel module further comprising: a third driving unit that applies a low driving voltage until the start of the characteristic correction period and applies a high driving voltage after the start of the characteristic correction period of the driving transistor. The display panel module according to claim 3,
The display panel module, wherein the coupling structure is realized by a capacitance pattern in which each electrode is connected to a control electrode of the driving transistor and a control electrode of the sampling transistor. The display panel module according to claim 3,
The display panel module according to claim 1, wherein the coupling structure is realized by a diffusion capacitor formed between a control electrode and a main electrode of the sampling transistor. A storage capacitor, a drive transistor having a control electrode and one main electrode connected to the two electrodes of the storage capacitor, and supplying a drive current having a magnitude corresponding to the voltage stored in the storage capacitor to the self-luminous element; A pixel array section in which a pixel region having a sampling transistor for controlling writing of a potential to a control electrode of the drive transistor is arranged in a matrix in the display region;
A first driver that applies a corresponding potential to the signal line;
A low ON potential is applied to the control electrode of the sampling transistor during threshold correction of the driving transistor, and a high ON potential is applied to the control electrode of the sampling transistor when writing a signal potential corresponding to the pixel gradation of the driving transistor. A coupling portion formed between the control electrode of the drive transistor and the control electrode of the sampling transistor, wherein the change in the drive potential drop at the end of the signal potential writing period A self-luminous display panel module comprising: a second drive unit that propagates to the control electrode of the drive transistor through the structure and lowers the signal potential written immediately before by a coupling voltage. The display panel module according to claim 6,
A display panel module, wherein a signal potential writing period T corresponding to a pixel gradation is set to be shorter than a mobility correction time length t calculated for each signal potential. The display panel module according to claim 7,
A third driving unit for sequentially applying a low driving voltage or a high driving voltage to a second control line connected to the other main electrode of the driving transistor in a time sequence, from the start of a non-light emitting period; A display panel module further comprising: a third driving unit that applies a low driving voltage until the start of the characteristic correction period and applies a high driving voltage after the start of the characteristic correction period of the driving transistor. The display panel module according to claim 8,
The display panel module, wherein the coupling structure is realized by a capacitance pattern in which each electrode is connected to a control electrode of the driving transistor and a control electrode of the sampling transistor. The display panel module according to claim 8,
The display panel module according to claim 1, wherein the coupling structure is realized by a diffusion capacitor formed between a control electrode and a main electrode of the sampling transistor. A storage capacitor, a drive transistor having a control electrode and one main electrode connected to the two electrodes of the storage capacitor, and supplying a drive current having a magnitude corresponding to the voltage stored in the storage capacitor to the self-luminous element; A pixel array section in which a pixel region having a sampling transistor for controlling writing of a potential to a control electrode of the drive transistor is arranged in a matrix in the display region;
A first driver that applies a corresponding potential to the signal line;
A second driving unit for driving the first control line connected to the control electrode of the sampling transistor with a binary driving voltage, wherein the driving potential at the end of the writing period of the signal potential corresponding to the pixel gradation Is propagated to the control electrode of the driving transistor through a coupling structure formed between the control electrode of the driving transistor and the control electrode of the sampling transistor, and the signal potential written immediately before is coupled to the coupling voltage. A self-luminous display panel module having a second drive unit that is reduced by
A system controller that controls the operation of the entire system;
And an operation input unit that receives an operation input to the system control unit. A storage capacitor, a drive transistor having a control electrode and one main electrode connected to the two electrodes of the storage capacitor, and supplying a drive current having a magnitude corresponding to the voltage stored in the storage capacitor to the self-luminous element; A pixel array section in which a pixel region having a sampling transistor for controlling writing of a potential to a control electrode of the drive transistor is arranged in a matrix in the display region;
A first driver that applies a corresponding potential to the signal line;
A low ON potential is applied to the control electrode of the sampling transistor during threshold correction of the driving transistor, and a high ON potential is applied to the control electrode of the sampling transistor when writing a signal potential corresponding to the pixel gradation of the driving transistor. A second driving unit to be applied to the first driving unit, wherein a change in driving potential drop at the end of the writing period of the signal potential is transmitted through a coupling structure formed between the control electrode of the driving transistor and its own control electrode. A self-luminous display panel module having a second drive unit that propagates to the control electrode of the drive transistor and reduces the signal potential written immediately before by a coupling voltage;
A system controller that controls the operation of the entire system;
And an operation input unit that receives an operation input to the system control unit.