JP5668529B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a technique for displaying an image using an electro-optical device such as a liquid crystal panel.

  As is well known, an electro-optical device such as a liquid crystal panel is provided with a pixel circuit corresponding to each intersection of a plurality of signal lines and a plurality of scanning lines. In such an electro-optical device, it is necessary to complete the writing of image signals to all pixel circuits associated with one scanning line within one horizontal scanning period. Therefore, when the number of pixel circuits associated with one scanning line increases, the time available for writing an image signal to one pixel circuit is shortened, and the required display quality is realized. It becomes difficult.

  Therefore, the following technique has been adopted as a means for realizing high definition of the electro-optical device without degrading display quality. That is, a plurality of signal lines of the electro-optical device are divided into a plurality of wiring blocks each including a predetermined number of signal lines, and gradation signals are applied by sequentially selecting each signal line in the wiring block for each wiring block. Technology.

  According to this technique, since the application of gradation voltages to a plurality of signal lines in a wiring block is performed in parallel in a plurality of blocks within one horizontal scanning period, the number of signal lines as the entire electro-optical device is reduced. Even when there are many, the application time of the gradation voltage per signal line can be made sufficiently long. Therefore, high definition of the electro-optical device can be realized without degrading display quality.

  However, when this technique is adopted, the following problems occur. That is, when selecting each signal line in the wiring block in one horizontal scanning period and applying the gradation voltage according to the image signal of each pixel, the gradation voltage corresponding to the image signal of the same value is applied. Even when applied to each signal line, the transmittance of the liquid crystal of each pixel circuit connected to each signal line is not strictly the same value, and display unevenness occurs in the display image of the electro-optical device.

  Therefore, as means for solving this problem, for example, Patent Document 1 discloses a driving condition of each pixel circuit by a driving circuit, specifically, a gradation voltage to each signal line in a wiring block within one horizontal scanning period. A technique has been proposed in which the application order is switched in synchronization with the vertical scanning period or in synchronization with the horizontal scanning period.

JP 2004-45967 A

  As disclosed in Patent Document 1, when the update control of the application order of the gradation voltage to each signal line in the wiring block is performed in synchronization with, for example, the vertical scanning period, when viewed through a plurality of vertical scanning periods Further, the transmittance of the liquid crystal of each pixel circuit is made uniform between the signal lines. For this reason, display unevenness appearing in the display image of the electro-optical device is reduced. The same applies to the case where the application order of gradation voltages to each signal line is updated in synchronization with the horizontal scanning period. As described above, when attention is paid to one electro-optical device, the technique of updating the application order of gradation voltages to each signal line has an effect of reducing display unevenness.

  However, in an electronic apparatus that displays an image using a plurality of electro-optical devices (liquid crystal light valves), such as a projection display device, for example, each electro-optical device controls update of driving conditions of a driving circuit independently of each other. Specifically, update control of the application order of gradation voltages to each signal line in the wiring block is executed. Accordingly, a phase shift occurs in the update control of the application order of gradation voltages between the liquid crystal light valves. In the liquid crystal light valve corresponding to the R color in a certain horizontal scanning cycle, each signal line in the wiring block is connected to, for example, While the gradation voltage is applied by selecting the first signal line, the second signal line, the third signal line, and the fourth signal line in this order, in the liquid crystal light valve corresponding to G color in the same horizontal scanning period, the wiring There may be a case where the gradation voltage is applied by selecting each signal line in the block in the order of the third signal line, the fourth signal line, the first signal line, and the second signal line.

  In this case, in the liquid crystal light valve corresponding to the R color and the liquid crystal light valve corresponding to the G color, the application timing of the gradation voltage to the first signal line and the gradation to the third signal line within one horizontal scanning period. The voltage application timing and the positional relationship are reversed. For this reason, for example, in the portion corresponding to the first signal line in the projected image, the R color is more easily emphasized than the G color, and in the portion corresponding to the third signal line, the G color is more easily emphasized than the R color. Can happen. As described above, when the application order of the gradation voltage to each signal line in the wiring block is different among the liquid crystal light valves corresponding to the respective colors of R, G, and B, the color balance of the projected image corresponding to each signal line is changed. Different between the signal lines, the projected image is colored.

  Such a problem also occurs in devices other than the projection display device. For example, there is an electro-optical device having a configuration in which a pixel portion is divided into a plurality of regions and a signal line driver circuit that is different for each region drives a signal line in each region. In such an electro-optical device, a plurality of signal lines to be driven by each signal line driving circuit are divided into a plurality of wiring blocks, and the signal line driving circuit sequentially selects each signal line in the wiring block for each wiring block. It can be considered that the image signal is supplied and the application order of the gradation voltage to each signal line is switched in synchronization with, for example, the vertical scanning period. In this case, if the application order of the gradation voltage to each signal line in the wiring block in the two signal line driving circuits for driving two adjacent regions is different, the display image of the electro-optical device is displayed. Display unevenness occurs.

  In addition to the examples described above, for the purpose of improving the display quality, update control of the driving conditions of each pixel circuit by the driving circuit may be performed independently between the plurality of electro-optical devices, for example. In this case as well, the same problem occurs when a so-called phase shift occurs in the drive condition update control between the electro-optical devices due to, for example, noise.

  The present invention has been made in view of the circumstances described above, and is driven between drive circuits in an electro-optical device or an electronic apparatus in which update control of drive conditions of a pixel unit by a plurality of drive circuits proceeds independently of each other. It is an object of the present invention to provide a technical means for preventing inconsistencies in conditions.

  In order to solve the above-described problem, the present invention has a plurality of scanning lines and a plurality of signal lines intersecting each other, and is arranged corresponding to each intersection of the plurality of scanning lines and the plurality of signal lines. And a plurality of pixel circuits that sequentially select the plurality of scanning lines within one vertical scanning period and are associated with each intersection of the selected scanning line and the plurality of signal lines. A scanning line driving circuit for connecting the plurality of signal lines to the plurality of signal lines and the plurality of signal lines are divided into a plurality of wiring blocks, and each signal line belonging to the wiring block is sequentially selected for each wiring block within one horizontal scanning period. And a signal line driving circuit for applying a gradation voltage to the selected signal line, and periodic update control of the application order of the gradation voltage to the plurality of signal lines in the wiring block in the plurality of wiring blocks. Control circuit and A plurality of electro-optical devices, and an operation for simultaneously initializing the update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices. And synchronizing means for synchronizing the update control of the application order of the gradation voltages to the plurality of signal lines in the wiring block in each of the plurality of electro-optical devices Provide electronic equipment.

  According to such an electronic apparatus, the synchronization unit repeatedly repeats the operation of simultaneously initializing the update control of the application order of the gradation voltages to the plurality of signal lines in the wiring block by each of the plurality of control circuits at intervals. By executing, the update control of the application order of the gradation voltage to the plurality of signal lines in the wiring block by each of the plurality of control circuits is synchronized. Accordingly, it is possible to prevent a mismatch in the order in which the gradation voltages are applied to the plurality of signal lines in the wiring block between the electro-optical devices.

  In a preferred aspect, the synchronization means has a length that is an integral multiple of a cycle of update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices. The operation of simultaneously initializing periodic update control of the application sequence of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices is repeated at a cycle.

  According to this aspect, in each electro-optical device, the wiring block between the electro-optical devices can be obtained without losing the periodicity of the periodic update control of the gradation voltage application sequence to the plurality of signal lines in the wiring block as much as possible. It is possible to prevent a mismatch in the order in which the gradation voltages are applied to the plurality of signal lines.

  In addition, the present invention includes a plurality of scanning lines and a plurality of signal lines intersecting each other, and a plurality of pixel circuits respectively disposed corresponding to the intersections of the plurality of scanning lines and the plurality of signal lines. Each of the plurality of pixel portions and the plurality of scanning lines in each pixel portion of the plurality of pixel portions are sequentially selected within one vertical scanning period, corresponding to each intersection of the selected scanning line and the plurality of signal lines Scanning line driving means for connecting the plurality of attached pixel circuits to the plurality of signal lines, and a plurality of signal line driving circuits respectively associated with the plurality of pixel units, wherein The signal lines are divided into a plurality of wiring blocks, and for each wiring block, each signal line belonging to the wiring block is sequentially selected within one horizontal scanning period, and a plurality of signal lines are driven to apply a gradation voltage to the selected signal line. A circuit and the plurality of signal lines; A plurality of control circuits that periodically update the application order of gradation voltages to a plurality of signal lines in the wiring block in each of the plurality of wiring blocks in each of the dynamic circuits; and in the wiring block in the plurality of control circuits An electro-optical device comprising: synchronization means for repeatedly performing an operation for simultaneously initializing periodic update control of the application order of gradation voltages to a plurality of signal lines at intervals of time. provide.

  According to such an electro-optical device, the synchronizing unit initializes the update operation of the application order of the gradation voltages to the plurality of signal lines in the wiring block by each of the plurality of control circuits all at once. By repeatedly executing the control, the update control of the application order of the gradation voltages to the plurality of signal lines in the wiring block by each of the plurality of control circuits is synchronized. Accordingly, it is possible to prevent a mismatch in the order in which the gradation voltages are applied to the plurality of signal lines in the wiring block between the plurality of pixel portions.

  Further, the following inventions can be grasped from the embodiments. According to the present invention, a plurality of pixel units, a plurality of drive circuits that respectively drive the plurality of pixel units, and periodic update control of driving conditions of the pixel unit by each of the plurality of drive circuits are executed independently of each other. The drive condition update control by each of the plurality of control circuits is performed by repeatedly executing a plurality of control circuits and an operation for simultaneously initializing drive condition update control by each of the plurality of control circuits at intervals. There is provided an electronic device comprising synchronization means for synchronizing the devices.

  According to such an electronic device, the synchronization unit repeatedly executes the operation for simultaneously updating the drive condition update control by each of the plurality of control circuits with a time interval, whereby the drive condition by each of the plurality of control circuits is determined. Update control is synchronized. Therefore, it is possible to prevent a mismatch in driving conditions between the driving circuits.

  In a preferred aspect, the synchronization means updates the driving condition by each of the plurality of control circuits in a cycle having a length that is an integral multiple of the periodic update control period of the driving condition by each of the plurality of control circuits. Repeat the operation to initialize the control all at once.

  Here, when the operation for simultaneously updating the drive condition update control is performed by the synchronization means, the drive conditions of the plurality of drive circuits are in the initial state, and then the plurality of control circuits are driven from the initial state to the drive condition. Update control is advanced. When the drive condition update control by each control circuit proceeds without any trouble, when the time corresponding to one cycle of the drive condition update control elapses after initialization, the drive conditions of the plurality of drive circuits are in the same initial state. Return to. At this time, an operation for simultaneously initializing the drive condition update control is performed by the synchronization means. At this time, the drive condition of each drive circuit is in the initial state. The operation of each drive circuit is not affected at all. Therefore, the periodicity of the drive condition update control of each drive circuit is not impaired. On the other hand, after the initialization, if a malfunction occurs in the drive condition update control by one of the control circuits due to, for example, noise, this corresponds to one cycle of the drive condition update control from the initialization. Drive time under the control of the control circuit that did not malfunction among the plurality of drive circuits returns to the initial state, but the drive condition of the drive circuit under control of the malfunctioned control circuit Does not return to the initial state. At this time, when the synchronization unit performs an operation for simultaneously initializing the drive condition update control operation, the drive conditions of all the drive circuits are in the initial state. Therefore, according to this aspect, it is possible to prevent the drive conditions from being inconsistent between the drive circuits without losing the periodicity of the drive condition update control of the drive circuits as much as possible.

It is a schematic diagram which shows the structure of the projection type display apparatus which is 1st Embodiment of this invention. It is a block diagram which shows the electrical structure of the projection type display apparatus. It is a block diagram which shows the structure of the pixel part of the electro-optical apparatus, the drive circuit, and the control circuit in the projection type display apparatus. FIG. 3 is a circuit diagram illustrating a configuration of a pixel circuit of the electro-optical device. FIG. 2 is a block diagram illustrating a configuration of a signal line driving circuit of the electro-optical device. 3 is a block diagram illustrating a configuration of a control circuit of the electro-optical device. FIG. It is a figure which illustrates the content of the selection pattern data memorize | stored in the pattern generator of the control circuit. It is a time chart which shows operation | movement of the embodiment. It is a figure which illustrates the mode of the update control of the application order of the gradation voltage to the several signal line in the wiring block performed in the same embodiment. 6 is a time chart illustrating an initialization procedure of update control of the application order of gradation voltages performed between the host CPU and each control circuit of a plurality of electro-optical devices in the embodiment. 10 is a time chart illustrating an initialization procedure of gradation voltage application sequence update control performed between a host CPU and each control circuit of a plurality of electro-optical devices according to the second embodiment of the invention. 10 is a time chart illustrating an initialization procedure of gradation voltage application order update control performed between a host CPU and each control circuit of a plurality of electro-optical devices in a third embodiment of the invention. 14 is a time chart illustrating an initialization procedure of gradation voltage application sequence update control performed between a host CPU and each control circuit of a plurality of electro-optical devices in a fourth embodiment of the invention. 14 is a time chart illustrating an initialization procedure for gradation voltage application order update control performed between a host CPU and each control circuit of a plurality of electro-optical devices in a fifth embodiment of the invention. It is a schematic diagram which shows the structure of the projection type display apparatus which is 6th Embodiment of this invention. 6 is a time chart illustrating an initialization procedure of update control of the application order of gradation voltages performed between the host CPU and each control circuit of a plurality of electro-optical devices in the embodiment. It is a time chart which illustrates the initialization procedure of the update control of the application order of the gradation voltage performed between host CPU and each control circuit of a several electro-optical apparatus in 7th Embodiment of this invention. It is a time chart which illustrates the initialization procedure of the update control of the application order of the gradation voltage performed between host CPU and each control circuit of a several electro-optical apparatus in 8th Embodiment of this invention. It is a block diagram which shows the structure of the electro-optical apparatus which is 9th Embodiment of this invention. It is a perspective view which shows the form (personal computer) of the other electronic device which is an example of application of this invention. It is a perspective view which shows the form (cellular phone) of the other electronic device which is an example of application of this invention.

<1. First Embodiment>
FIG. 1 is a schematic diagram showing a configuration of a projection display device (three-plate projector) 4000 which is a first embodiment of an electronic apparatus according to the present invention. The projection display device 4000 includes three electro-optical devices 100 (100R, 100G, and 100B) respectively corresponding to different display colors R, G, and B. The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device (light source) 4002 to the electro-optical device 100R, the green component g to the electro-optical device 100G, and the blue component b to the electro-optical device 100B. To supply. Each electro-optical device 100 functions as a light modulator (light valve) that modulates each monochromatic light supplied from the illumination optical system 4001 according to a display image. The projection optical system 4003 synthesizes the emitted light from each electro-optical device 100 and projects it on the projection surface 4004.

  FIG. 2 is a block diagram showing an electrical configuration of the projection type display device 4000. As shown in FIG. 2, the projection display device 4000 includes electro-optical devices 100R, 100G, and 100B, an image input unit 70 that captures image signals from the outside, and a host CPU 60 that controls them. Each of the electro-optical devices 100 </ b> R, 100 </ b> G, and 100 </ b> B includes a pixel unit 10, a drive circuit 20, and a control circuit 30. Here, the control circuit 30 is a circuit that controls each part in the electro-optical device such as the drive circuit 20 in accordance with various control signals supplied from the host CPU 60.

  The host CPU 60 supplies the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC to the image input unit 70 and also supplies the control circuits 30 of the electro-optical devices 100R, 100G, and 100B. The image input unit 70 generates image signals VID_R, VID_G, and VID_B for each color of R, G, and B for one frame based on an image signal captured from the outside every time the vertical synchronization signal VSYNC is given. The image input unit 70 supplies the image signal VID_R of each pixel for one line to the control circuit 30 of the electro-optical device 100R in synchronization with the pixel clock PCLK_R every time the horizontal synchronization signal HSYNC is given. The image signal VID_G of each pixel is supplied to the control circuit 30 of the electro-optical device 100G in synchronization with the pixel clock PCLK_G, and the image signal VID_B of each pixel for one line is synchronized with the pixel clock PCLK_B. To the control circuit 30.

  A three-wire (CS, SDI, SCK) serial interface is provided between the host CPU 60 and each of the electro-optical devices 100R, 100G, and 100B. When there is data to be transmitted to the control circuit 30 of the electro-optical device 100R, the host CPU 60 sets the chip select signal CS_R to the L level which is an active level, and outputs serial data SDI in synchronization with the serial clock SCK during that time. To do. The control circuit 30 of the electro-optical device 100R takes in the serial data SDI with the serial clock SCK because the chip select signal CS_R is at the active level. Similarly, when there is data to be transmitted to the control circuit 30 of the electro-optical device 100G (100B), the host CPU 60 sets the chip select signal CS_G (CS_B) to the L level which is an active level, and the serial clock SCK during that time. Synchronize and output serial data SDI. Since the chip select signal CS_G (CS_B) is at the active level, the control circuit 30 of the electro-optical device 100G (100B) takes in the serial data SDI with the serial clock SCK.

  In addition, the host CPU 60 has a function of supplying an initialization synchronization signal ISYNC to each control circuit 30 of the electro-optical devices 100R, 100G, and 100B at predetermined intervals. The role of the initialization synchronization signal ISYNC will be described later.

  FIG. 3 is a block diagram illustrating configurations of the pixel unit 10, the drive circuit 20, and the control circuit 30 in one electro-optical device 100. As shown in FIG. 3, the pixel unit 10 is formed by arranging a plurality of pixel circuits PIX in a planar shape. The drive circuit 20 is a circuit that drives each pixel circuit PIX, and includes a scanning line drive circuit 22 and a signal line drive circuit 24.

  In the pixel portion 10, M scanning lines 12 and N signal lines 14 that intersect with each other are formed (M and N are natural numbers). The plurality of pixel circuits PIX are provided corresponding to the intersections of the scanning lines 12 and the signal lines 14 and are arranged in a matrix of vertical M rows × horizontal N columns. The N signal lines 14 in the pixel unit 10 are divided into J wiring blocks B [1] to B [J] in units of K adjacent to each other (K is a natural number of 2 or more). (J = N / K).

  FIG. 4 is a circuit diagram showing a configuration of each pixel circuit PIX. As shown in FIG. 4, each pixel circuit PIX includes a liquid crystal element 42 and a selection switch 44. The liquid crystal element 42 is an electro-optical element that includes pixel electrodes 421 and a common electrode 423 that face each other and a liquid crystal 425 between the two electrodes. The transmittance of the liquid crystal 425 changes according to the voltage applied between the pixel electrode 421 and the common electrode 423. In the following description, for the sake of convenience, the voltage applied to the liquid crystal element 42 when the pixel electrode 421 has a higher potential than the common electrode 423 is expressed as positive polarity, and the pixel electrode 421 has a low potential. The applied voltage is expressed as negative polarity.

The selection switch 44 is composed of an N-channel type thin film transistor having a gate connected to the scanning line 12, and is interposed between the liquid crystal element 42 (pixel electrode 421) and the signal line 14 to electrically connect them ( (Conduction / non-conduction) is controlled. Accordingly, the pixel circuit PIX (the liquid crystal element 42) displays a gradation corresponding to the voltage of the signal line 14 (a gradation voltage VG described later) when the selection switch 44 is in the ON state.
The above is the configuration of each pixel circuit PIX in FIG.

  In FIG. 3, the scanning line driving circuit 22 outputs scanning signals G [1] to G [M] for each scanning line 12 in one horizontal scanning period in response to the output of the internal horizontal synchronization signal HS from the control circuit 3. The active level is sequentially increased by H, and each of the M scanning lines 12 is sequentially selected. Here, during the period in which the scanning signal G [m] corresponding to the m-th row is at the active level, the selection switches 44 of the N pixel circuits PIX in the m-th row are in the ON state, and each of these selection switches 44 is turned on. N signal lines 14 are connected to the respective pixel electrodes 421 of the N pixel circuits PIX in the m-th row.

  The signal line driving circuit 24 is a circuit that drives each of the N signal lines 14 in synchronization with the selection of each scanning line 12 by the scanning line driving circuit 22. FIG. 5 is a block diagram showing the configuration of the signal line driving circuit 24. As shown in FIG. As described above, the N signal lines 14 in the pixel unit 10 are divided into J wiring blocks B [1] to B [J]. In the signal line driving circuit 24, J demultiplexers 57 [1] to 57 [J] and J drives are associated with the J wiring blocks B [1] to B [J], respectively. Voltage generation circuits 56 [1] to 56 [J] and J multiplets 53 [1] to 53 [J] are provided. The signal line drive circuit 24 is provided with an image signal storage unit 51. The image signal storage unit 51 is composed of N registers (not shown) each storing digital image signal VIDs for N pixels constituting one line. The N registers are associated with J wiring blocks B [1] to B [J], and register blocks 52 [1] to 52 [J] each including K (= N / J) registers. It is divided into.

  Each of the multiplexers 53 [j] (j = 1 to J) includes K switches 54 [1] to 54 [K]. Here, focusing on one multiplexer 53 [j] corresponding to the j-th wiring block B [j], one contact of each of the K switches 54 [1] to 54 [K] Each of the image signals for K pixels stored in the j-th register block 52 [j] is supplied via the K signal lines 17. The other contacts of the K switches 54 [1] to 54 [K] are commonly connected to one signal line 16, and the j-th drive voltage generation circuit 56 is connected to the signal line 16. [J] is connected to the input terminal.

  The ON / OFF of the K switches 54 [1] to 54 [K] of each multiplexer 53 [j] (j = 1 to J) is set to K selection signals SELa [1] to 54 output from the control circuit 30. Each is switched by SELa [K]. Here, when one selection signal SELa [k] is at the active level and the other K−1 selection signals SELa [k ′] (k ′ ≠ k) are at the inactive level, the multiplexer 53 [ j] (j = 1 to J), only J switches 54 [k] belonging to each are turned ON. Accordingly, each of the multiplexers 53 [j] (j = 1 to J) is the image signal of the jth pixel among the image signals for K pixels in the horizontal direction stored in the corresponding register block 52 [j]. Is selected as the image signal D [j] and supplied to the corresponding drive voltage generation circuit 56 [j] via the signal line 16.

  The drive voltage generation circuits 56 [1] to 56 [J] have a function of generating a precharge voltage and gradations corresponding to the image signals D [1] to D [J] supplied via the signal line 16, respectively. A function of generating a voltage. The drive voltage generation circuits 56 [1] to 56 [J] divide one horizontal scanning period H into a precharge period TPRE and a write period TWRT. The precharge period TPRE has a precharge voltage, and the write period TWRT has an image. The gradation voltages corresponding to the signals D [1] to D [J] are output to the J signal lines 15 as signal line drive signals C [1] to C [J], respectively.

  Each of the demultiplexers 57 [j] (j = 1 to J) includes K switches 58 [1] to 58 [K]. Here, focusing on one demultiplexer 57 [j] corresponding to the j-th wiring block B [j], one contact of each of the K switches 54 [1] to 54 [K] is The signal line 15 is connected in common and is connected to the output terminal of the j-th drive voltage generation circuit 56 [j] via the signal line 15. The other contacts of the K switches 54 [1] to 54 [K] are respectively connected to K signal lines 14 constituting the jth wiring block B [j].

ON / OFF of the K switches 58 [1] to 58 [K] of each demultiplexer 57 [j] (j = 1 to J) is determined by K selection signals SELb [1] output from the control circuit 30. .. SELb [K] to switch each. Here, when one selection signal SELb [k] is at an active level and the other K−1 selection signals SELb [k ′] (k ′ ≠ k) are at an inactive level, the demultiplexer 57. Only J switches 58 [k] belonging to [j] (j = 1 to J) are turned ON. Therefore, each of the demultiplexers 57 [j] (j = 1 to J) has signal line drive signals C [1] to C [J] output from the drive voltage generation circuits 56 [1] to 56 [J]. Are output to the k-th signal line 14 of each of the wiring blocks B [1] to B [J].
The above is the configuration of the signal line driver circuit 24 in FIG.

  In FIG. 3, the control circuit 30 includes an image signal VID, a polarity signal POL, a selection signal SELa [k] (k = 1 to K), SELb [k] (k = 1 to K), and each unit in the electro-optical device 100. It is a circuit that generates various control signals for controlling. FIG. 6 is a block diagram showing a part of the configuration of the control circuit 30. As shown in FIG. 6, the control circuit 30 includes a control signal processing unit 31, counters 32 and 33, an adder 34, and a pattern generator 35.

  The control signal processing unit 31 is supplied with a chip select signal CS, serial data SDI, and serial clock SCK from the host CPU 60 (see FIG. 2) via a 3-wire serial interface. The control signal processing unit 31 takes in the serial data SDI in synchronization with the serial clock SCK while the chip select signal CS is at the L level which is the active level. The data supplied as the serial data SDI includes various commands for instructing the setting of the driving conditions of the driving circuit 20. The control signal processing unit 31 is supplied with a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC from the host CPU 60 (see FIG. 2). The control signal processing unit 31 is supplied with the image signal VID of each pixel constituting the screen from the image input unit 70 (see FIG. 2) in synchronization with the pixel clock PCLK. The control signal processing unit 31 takes in the image data VID by the pixel clock PCLK.

  The control signal processing circuit 31 outputs the internal vertical synchronization signal VS in response to the supply of the vertical synchronization signal VSYNC. Further, the control signal processing circuit 31 outputs the internal horizontal synchronization signal HS in response to the horizontal synchronization signal HSYNC being supplied. The control signal processing circuit 31 outputs the image signal VID of each pixel for one line (N pixels) fetched from the host CPU 60 to the signal line driving circuit 24 every time the internal horizontal synchronization signal HS is output. In the signal line driving circuit 24, the image signal VID for N pixels is divided into J blocks each including image signals for K pixels, and stored in the register blocks 52 [1] to 52 [J] described above. The

  The counter 32 is a counter that increases the count value CNT1 by the step value STP1 given from the control signal processing unit 31 every time the rising edge of the internal horizontal synchronizing signal HS occurs. The counter 33 is a counter that increases the count value CNT2 by the step value STP2 given from the control signal processing unit 31 every time the rising edge of the internal vertical synchronizing signal VS occurs. Here, the step values STP1 and STP2 are set according to a command received from the host CPU 60. The adder 34 adds the count value CNT1 of the counter 32 and the count value CNT2 of the counter 33, and outputs a pattern number PN indicating the addition result CNT1 + CNT2 to the pattern generator 35.

  The counters 32 and 33 are configured to be able to initialize the count value. The control signal processing unit 31 initializes the count value CNT2 of the counter 33 to “0” and the function of generating the first initialization signal RES1 for initializing the count value CNT1 of the counter 32 to “0”. For generating a second initialization signal RES2.

  When one vertical scanning period ends and a new vertical scanning period starts, the control signal processing unit 31 generates the first initialization signal RES1 and initializes the count value CNT1 of the counter 32 to “0”. .

  When the above-described initialization synchronization signal ISYNC is supplied from the host CPU 60, the control signal processing unit 31 generates the second initialization signal RES2 and initializes the count value CNT2 of the counter 33 to “0”. Details of the transmission of the initialization synchronization signal ISYNC between the host CPU 60 and the control signal processing unit 31 will be described later.

  The pattern generator 35 divides the horizontal scanning period H into a precharge period TPRE and a writing period TWRT, and the selection signal SELa [1] to SELa [K] and the selection signal SELb [1] to It is a circuit that performs switching control of SELb [K].

  In the precharge period TPRE of each horizontal scanning period H, the pattern generator 35 sets the selection signals SELa [1] to SELa [K] to the L level and the selection signals SELb [1] to SELb [K] to the H level.

  In the writing period TWRT of each horizontal scanning period H, the pattern generator 25 sequentially applies gradation voltages to the K signal lines 14 of the wiring blocks B [1] to B [J]. The selection signals SELa [1] to SELa [K] and the selection signals SELb [1] to SELb [K] are controlled to be switched.

  In order to enable switching control of the selection signal within the writing period TWRT, the pattern generator 35 stores, for example, K types of selection pattern data. FIG. 7 illustrates the contents of the K types of selection pattern data. The K types of selected pattern data are associated with pattern numbers PN from 0 to K-1.

  The individual selection pattern data is data for designating the application order of the gradation voltages to the K signal lines 14 constituting each of the wiring blocks B [1] to B [K] in the writing period TWRT. For example, the selected pattern data corresponding to the pattern number PN = “0” is the gradation voltage applied to the first signal line 14 of each wiring block in the first gradation voltage application period U [1] in the writing period TWRT. Application of gradation voltage to the second signal line 14 in the second gradation voltage application period U [2],..., Kth signal line in the last gradation voltage application period U [K] 14 is instructed to apply a gradation voltage. Further, the selected pattern data corresponding to the pattern number PN = “1” is the gradation voltage applied to the Kth signal line 14 of each wiring block in the first gradation voltage application period U [1] in the writing period TWRT. Application of the gradation voltage to the first signal line 14 in the second gradation voltage application period U [2],..., K−1th in the last gradation voltage application period U [K]. The application of the gradation voltage to the signal line 14 is instructed.

  The pattern generator 35 selects the selection signals SELa [1] to SELa [K] and the selection signal SELb [according to the selection pattern data corresponding to the pattern number PN given from the adder 34 in the writing period TWRT of each horizontal scanning period H. 1] to SELb [K] are changed.

When K types of selected pattern data are stored in the pattern generator 35, the counters 32 and 33 are counters that count in the range of 0 to K-1. Further, as the adder 34, one having a configuration in which a remainder obtained by multiplying the above-described addition result CNT1 + CNT2 by K is output as a pattern number PN is used.
The above is the configuration of the control circuit 30.

  FIG. 8 is a time chart illustrating an operation example of the electro-optical device 100. FIG. 8 illustrates the waveform of each part in a certain vertical scanning period V1 and the waveform of each part in the next vertical scanning period V2. In the present embodiment, the control circuit 30 inverts the polarity signal POL every time the vertical scanning period is switched. The polarity signal POL in the example shown in FIG. 8 indicates negative polarity (−) in the vertical scanning period V1, and indicates positive polarity (+) in the vertical scanning period V2. Here, in the vertical scanning period V1 in which the polarity signal POL indicates the negative polarity (−), a positive voltage is applied to the common electrode 423, and the vertical scanning period V2 in which the polarity signal POL indicates the positive polarity (+). Then, a negative voltage is applied to the common electrode 423 described above.

  In each vertical scanning period, the scanning line driving circuit 22 sequentially selects and selects the M scanning lines 12 in synchronization with the control signal processing circuit 31 of the control circuit 30 generating the internal horizontal synchronization signal HS. The scanning signal G [j] corresponding to the scanning line 12 is set to the H level which is the active level over one horizontal scanning period H.

  In the precharge period TPRE of each horizontal scanning period H, the pattern generator 35 of the control circuit 30 sets all of the selection signals SELa [1] to SELa [K] to the L level and outputs the multiplexers 53 [1] to 53 [J]. All the switches 54 [1] to 54 [K] are turned OFF and all the selection signals SELb [1] to SELb [K] are set to the H level so that all the demultiplexers 57 [1] to 57 [J] Turn on the switches 58 [1] to 58 [K]. In the precharge period TPRE of each horizontal scanning period H, the drive voltage generation circuits 56 [1] to 56 [J] output the precharge voltage having the polarity indicated by the polarity signal POL. The precharge voltage output from one drive voltage generation circuit 56 [j] is supplied to the wiring block B [j] via the K switches 58 [1] to 58 [J] of the demultiplexer 57 [j]. Applied to K signal lines 14. Accordingly, the precharge voltage is applied to all the signal lines 14 of the pixel portion 10 in the precharge period TPRE.

  In the writing period TWRT of each horizontal scanning period H, the pattern generator 35 selects the selection signals SELa [1] to SELa [K] and the selection signals SELb [1] to SELb according to the selection signal pattern data corresponding to the pattern number PN at that time. SELb [K] is changed.

  On the lower left side of FIG. 8, selection signals SELa [1] to SELa [generated in a horizontal scanning period H (for example, the mth horizontal scanning period H in the vertical scanning period V1) having the vertical scanning period V1. Waveforms of K] and selection signals SELb [1] to SELb [K] are illustrated. In this example, in the gradation voltage application period U [1], only the set of the selection signals SELa [1] and SELb [1] is set to the H level, and the switches 54 [ 1] and the switch 58 [1] in the demultiplexers 57 [1] to 57 [J] is turned ON. As a result, the image signal VID of the first pixel in each of the register blocks 52 [1] to 52 [J] passes through the switches 54 [1] of the multiplexers 53 [1] to 53 [J], and the image signal D [1] to D [J] are supplied to the drive voltage generation circuits 56 [1] to 56 [J], respectively. At this time, since the polarity signal POL indicates negative polarity (−), the drive voltage generation circuits 56 [1] to 56 [J] are supplied to each within a range of negative polarity with respect to the reference potential VREF. The gradation voltages VG corresponding to the designated gradations of the image signals D [1] to D [J] to be output are output. The gradation voltages VG output from the drive voltage generation circuits 56 [1] to 56 [J] pass through the switches 58 [1] in the demultiplexers 57 [1] to 57 [J], respectively, and the signal line drive signal. C [1] to C [J] are applied to the first signal line 14 of each of the wiring blocks B [1] to B [J].

  In the gradation voltage application period U [2], only the set of the selection signals SELa [2] and SELb [2] is set to the H level, and the switches 54 [2] in the multiplexers 53 [1] to 53 [J] The switch 58 [2] in the demultiplexers 57 [1] to 57 [J] is turned ON. As a result, each gradation voltage VG corresponding to the image signal VID of the second pixel in each of the register blocks 52 [1] to 52 [J] is generated, and the switches in the demultiplexers 57 [1] to 57 [J]. 58 [2], respectively, and applied to the second signal line 14 of each of the wiring blocks B [1] to B [J] as signal line drive signals C [1] to C [J].

The same applies hereinafter, and in the gradation voltage application period U [3], each gradation voltage VG corresponding to the image signal of the third pixel in each register block is applied to the third signal line 14 of each wiring block. In the adjustment voltage application period U [4], each gradation voltage VG corresponding to the image signal of the fourth pixel in each register block is applied to the fourth signal line 14 of each wiring block,..., The last gradation voltage application In the period U [K], each gradation voltage VG corresponding to the image signal of the Kth pixel in each register block is applied to the Kth signal line 14 of each wiring block.
The above is the operation of each unit within the m-th horizontal scanning period H of the vertical scanning period V1.

  On the lower right side of FIG. 8 is a selection signal SELa [generated in the same horizontal scanning period H of the vertical scanning period V2 following the vertical scanning period V1 (that is, the mth horizontal scanning period H in the vertical scanning period V2). 1] to SELa [K] and select signals SELb [1] to SELb [K] are shown.

  Here, the count value CNT1 of the counter 32 in the m-th horizontal scanning period H in the vertical scanning period V2 is the same as the count value CNT1 of the counter 32 in the m-th horizontal scanning period H in the vertical scanning period V1. This is because the count value CNT1 of the counter 32 is initialized to “0” every time the vertical scanning period is switched. However, when the vertical scanning period V1 is switched to the vertical scanning period V2, the count value CNT2 of the counter 33 is incremented by the step value STP2 by the internal vertical synchronization signal VS output from the control signal processing unit 31. Therefore, in the m-th horizontal scanning period H in the vertical scanning period V2, the pattern number PN given to the pattern generator 35 is different from the pattern number PN given in the m-th horizontal scanning period H in the vertical scanning period V1. It becomes. Accordingly, in the writing period TWRT of the m-th horizontal scanning period H in the vertical scanning period V2, the K of each wiring block is different in the order different from the writing period TWRT of the m-th horizontal scanning period H in the vertical scanning period V1. A gradation voltage is applied to the signal line 14.

  In the example shown on the lower right side of FIG. 8, in the gradation voltage application period U [1] of the writing period TWRT, each gradation voltage VG corresponding to the image signal of the Kth pixel in each register block is K in each wiring block. Each gradation voltage VG corresponding to the image signal of the first pixel in each register block is applied to the first signal line 14 of each wiring block in the gradation voltage application period U [2]. In the last gradation voltage application period U [K], each gradation voltage VG corresponding to the image signal of the (K-1) th pixel in each register block is applied to the (K-1) th signal line 14 in each wiring block. Applied.

  In the vertical scanning period V2, since the polarity signal POL indicates positive polarity (+), the drive voltage generation circuits 56 [1] to 56 [J] have a positive polarity range with respect to the reference potential VREF. Thus, the gradation voltage VG corresponding to the designated gradation of the image signal supplied to each is output.

  As described above, in the m-th horizontal scanning period H of the vertical scanning period V1 and the m-th horizontal scanning period H of the vertical scanning period V2, the levels of the wiring blocks to the K signal lines 14 in different orders. A regulated voltage is applied. As described above, in this embodiment, the order in which the gradation voltages are applied to the K signal lines 14 of each wiring block is changed according to the switching of the vertical scanning period. It changes according to the change of. FIG. 9 exemplifies a change in the application order of the gradation voltages to the K signal lines 14 in each wiring block when both the step values STP1 and STP2 are “1”. In FIG. 9, the vertical direction corresponds to the transition direction of the horizontal scanning period H, and the horizontal direction is a sequence of K gradation voltage application periods U [1] to U [K] generated in the horizontal scanning period H. It corresponds. In the example shown in FIG. 9, the order in which the gradation voltage is applied to each signal line 14 in the wiring block within the same vertical scanning period is rotated backward by one every time the horizontal scanning period H is switched. Shifted. In the example shown in FIG. 9, when attention is paid to the same horizontal scanning period H in each vertical scanning period, the vertical scanning period switches the order in which the gradation voltage is applied to each signal line 14 in the wiring block. Rotate shift backward one by one.

  Therefore, when viewed through a plurality of horizontal scanning periods and a plurality of vertical scanning periods, the time average value of the application order of the gradation voltages in each horizontal scanning period is made uniform between the signal lines 14. Accordingly, display unevenness is reduced when viewed as a single electro-optical device.

  By the way, in the projection type display device according to the present embodiment, the update control of the application order of the gradation voltage to each signal line 14 is independently performed in each of the three electro-optical devices 100R, 100G, and 100R. It is advanced. Here, if the count value CNT1 of the counter 32 and the count value CNT2 of the counter 33 of each of the electro-optical devices 100R, 100G, and 100R are initialized at the time of power-on of the projection display device, for example, three electro-optical devices. The update control of the application order of gradation voltages to each signal line 14 can be started simultaneously from the initial state between 100R, 100G, and 100R. However, there is a difference in the count value CNT1 of the counter 32 or the count value CNT2 of the counter 33 among the three electro-optical devices 100R, 100G, and 100R due to the influence of noise and the like generated during operation of the projection display device. there is a possibility. In this case, the application order of the gradation voltage to each signal line 14 differs among the three electro-optical devices 100R, 100G, and 100R. As a result, the display image is colored as described above.

  The feature of this embodiment is that, in order to prevent the occurrence of such a problem, update control of the application order of gradation voltages to the plurality of signal lines 14 in each wiring block is performed between the electro-optical devices 100R, 100G, and 100R. The projection display device is provided with means for synchronizing with the projector. In other words, in the present embodiment, the host CPU 60 periodically supplies the above-described initialization synchronization signal ISYNC to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, thereby updating the application order of gradation voltages. Control is synchronized between the electro-optical devices 100R, 100G, and 100R.

  FIG. 10 is a time chart showing the generation timing of the initialization synchronization signal ISYNC in the present embodiment. As shown in FIG. 10, the host CPU 60 applies an integral multiple of the cycle of applying the gradation voltage application control cycle, that is, to the K signal lines 14 in the wiring block in each horizontal scanning period in one vertical scanning period. It occurs at a timing that occurs in a period that is an integral multiple of the period required for the gradation voltage application sequence to be updated again in the same sequence, and in synchronization with the vertical synchronization signal VSYNC. For example, in the example shown in FIG. 9, in the vertical scanning cycle for displaying the screen with the frame number FN = FN0, the grayscale voltages to the K signal lines 14 in the wiring block in each horizontal scanning period within one vertical scanning period. To the K signal lines 14 in the wiring block in each horizontal scanning period in one vertical scanning period in the vertical scanning period in which the screen of frame number FN = FN0 + K−1 is displayed. The application order of the gray scale voltages is again the same order. Therefore, in this case, the update control cycle of the application order is a cycle that is K times as long as the vertical scanning period, and the host CPU 60 is initially initialized with a cycle of L × K times (L is an integer), for example. The synchronizing signal ISYNC is supplied to the control circuit 30 of each of the electro-optical devices 100R, 100G, and 100B.

  The control signal processing circuit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B sets the second initialization signal RES2 to an active level in response to the initialization synchronization signal ISYNC from the host CPU 60, The count value CNT2 of the counter 33 is initialized to “0”.

  As described above, according to the present embodiment, the electro-optical devices 100R, 100G, and 100B are generated from the host CPU 60 at a timing that occurs at an integral multiple of the application order update control cycle and that is synchronized with the vertical synchronization signal VSYNC. An initialization synchronization signal ISYNC is supplied to each control circuit 30, and the count value CNT2 of the counter 33 of each electro-optical device 100R, 100G, and 100B is initialized to “0”. Accordingly, after the subsequent vertical scanning period, the gradation voltages are applied to the K signal lines 14 in the wiring block in the same application order between the electro-optical devices 100R, 100G, and 100B, and coloring occurs. Is prevented.

<2. Second Embodiment>
Also in the present embodiment, as in the first embodiment, the host CPU 60 initializes the count value CNT2 of the counter 33 of each of the electro-optical devices 100R, 100G, and 100B at a cycle that is an integral multiple of the cycle of the application order update control. To process. The difference between the present embodiment and the first embodiment lies in the procedure for exchanging signals between the host CPU 60 and each control circuit 30 for the initialization. The same applies to third to eighth embodiments described later.

  FIG. 11 is a time chart showing the operation of the projection display device according to the present embodiment. In the present embodiment, the host CPU 60 first sends the control circuits 30 of the electro-optical devices 100R, 100G, and 100B to a timing that is a predetermined time before the switching timing of a cycle that is an integral multiple of the cycle of the application order update control. On the other hand, an initialization command for instructing initialization of the count value CNT2 is sent. Specifically, the chip select signal CS_R is set to an active level, serial data SDI composed of bits constituting the initialization command is output in synchronization with the serial clock SCK, and this serial data SDI is output to the control circuit 30 of the electro-optical device 100R. Receive. Next, after returning the chip select signal CS_R to the inactive level, the chip select signal CS_G is set to the active level, and the serial data SDI composed of the configuration bits of the initialization command is output in synchronization with the serial clock SCK. Is received by the control circuit 30 of the electro-optical device 100G. Next, after returning the chip select signal CS_G to the inactive level, the chip select signal CS_B is set to the active level, and the serial data SDI consisting of the configuration bits of the initialization command is output in synchronization with the serial clock SCK. Is received by the control circuit 30 of the electro-optical device 100B.

After the initialization commands are received by the control circuits 30 of the electro-optical devices 100R, 100G, and 100B in this way, the host CPU 60 has a switching timing of a cycle that is an integral multiple of the cycle of the application order update control, An initialization synchronization signal ISYNC is supplied to each control circuit 30 at a timing synchronized with the vertical synchronization signal VSYNC. In the present embodiment, the control signal processing unit 31 in the control circuit 30 interprets the initialization synchronization signal ISYNC as an instruction to execute a command received in advance. In this case, since the control signal processing units 31 of the electro-optical devices 100R, 100G, and 100B fetch the initialization command before the initialization synchronization signal ISYNC is supplied, the initialization command is executed, and the counter 33 The count value CNT2 is initialized to “0”.
Also in this embodiment, the same effect as the first embodiment can be obtained.

<3. Third Embodiment>
FIG. 12 is a time chart showing the operation of the projection display apparatus according to the present embodiment. In the present embodiment, the control circuit 30 of the electro-optical device 100R uses the serial data SDI having a predetermined number of bits transmitted in synchronization with the serial clock SCK after the chip select signal CS_R changes from the inactive level to the active level. Is recognized as a command addressed to the control circuit 30 and received. Similarly, the control circuit 30 of the electro-optical device 100G (100B) uses a predetermined number of bits transmitted in synchronization with the serial clock SCK after the chip select signal CS_G (CS_B) changes from the inactive level to the active level. The serial data SDI is recognized as a command addressed to the control circuit 30 and received.

  Accordingly, when the host CPU 60 comes a predetermined time before the switching timing of a cycle that is an integral multiple of the cycle of the application order update control, the control circuits 30 of the electro-optical devices 100R, 100G, and 100B are as follows. Send an initialization command to the address. First, the host CPU 60 sets the chip select signal CS_R to an active level, sends serial data SDI composed of constituent bits of the initialization command in synchronization with the serial clock SCK, and sends the initialization command to the control circuit 30 of the electro-optical device 100R. Receive. Next, the host CPU 60 sets the chip select signal CS_G to the active level in a state where the chip select signal CS_R is maintained at the active level, and sends the serial data SDI composed of the configuration bits of the initialization command in synchronization with the serial clock SCK. The initialization command is received by the control circuit 30 of the electro-optical device 100G. At this time, since the control circuit 30 of the electro-optical device 100R receives an initialization command having a predetermined number of bits after the chip select signal CS_R becomes active level, an initial address for the control circuit 30 of the electro-optical device 100G is received. The command is not received in error. Next, the host CPU 60 sets the chip select signal CS_B to the active level in a state where the chip select signals CS_R and CS_G are maintained at the active level, and sends the serial data SDI composed of the configuration bits of the initialization command in synchronization with the serial clock SCK. Then, the control circuit 30 of the electro-optical device 100B receives the initialization command.

  After causing the control circuits 30 of the electro-optical devices 100R, 100G, and 100B to receive the initialization command in this manner, the host CPU 60 simultaneously changes the chip select signals CS_R, CS_G, and CS_B from the active level to the inactive level. In the present embodiment, the control signal processing unit 31 of the control circuit 30 of the electro-optical device 100R interprets the change from the active level to the inactive level of the chip select signal CS_R as an instruction to execute the initialization command, and sets the count value CNT2 Perform initialization. Similarly, the control signal processing unit 31 of the control circuit 30 of the electro-optical device 100G (100B) interprets the change from the active level to the inactive level of the chip select signal CS_G (CS_B) as an instruction to execute the initialization command. The count value CNT2 is initialized. Accordingly, in the present embodiment, the count value CNT2 in each of the electro-optical devices 100R, 100G, and 100B is simultaneously initialized at the timing when the chip select signals CS_R, CS_G, and CS_B are simultaneously changed from the active level to the inactive level. .

In this embodiment, the host CPU 60 sends the vertical synchronization signal so that the simultaneous change timing of the chip select signals CS_R, CS_G, and CS_B from the active level to the inactive level is synchronized with the vertical synchronization signal VSYNC. An initialization command is sent to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B at a timing that is a predetermined time before the VSYNC generation timing.
Also in this embodiment, the same effect as the first and second embodiments can be obtained.

<4. Fourth Embodiment>
FIG. 13 is a time chart showing the operation of the projection display apparatus according to the fourth embodiment of the present invention. In the second embodiment (FIG. 11), the host CPU 60 sends an initialization command to each control circuit 30 of the electro-optical devices 100R, 100G, and 100B, and then is an integer of the update control cycle of the gradation voltage application order. The initialization synchronization signal ISYNC is transmitted to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B at the timing that is generated with a double cycle and synchronized with the vertical synchronization signal VSYNC. On the other hand, in the present embodiment, the host CPU 60 transmits the initialization synchronization signal ISYNC before the timing synchronized with the vertical synchronization signal VSYNC. Each control signal processing unit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B counts the counter 33 in synchronization with the vertical synchronization signal VSYNC after receiving the initialization command and the initialization synchronization signal ISYNC. CNT2 is initialized.

  Also in this embodiment, the same effect as the first to third embodiments can be obtained. In this embodiment, the control signal processing units 31 of the electro-optical devices 100R, 100G, and 100B initialize the count value CNT2 of the counter 33 in synchronization with the vertical synchronization signal VSYNC. There is an advantage that strict time accuracy is not required for the transmission timing of the signal ISYNC.

<5. Fifth Embodiment>
FIG. 14 is a time chart showing the operation of the projection display apparatus according to the fifth embodiment of the present invention. In the third embodiment (FIG. 12), the host CPU 60 sends an initialization command to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, and then is an integer of the update control cycle of the gradation voltage application order. The chip select signals CS_R, CS_G, and CS_B are simultaneously changed from the active level to the inactive level at a timing that occurs at a double cycle and that is synchronized with the vertical synchronization signal VSYNC. On the other hand, in this embodiment, the host CPU 60 changes the chip select signals CS_R, CS_G, and CS_B from the active level to the inactive level all at once before the timing synchronized with the vertical synchronization signal VSYNC. After each control signal processing unit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B receives an initialization command and detects a change from the active level to the inactive level of the chip select signal for each of the control signals 30 The count value CNT2 of the counter 33 is initialized in synchronization with the vertical synchronization signal VSYNC.
Also in this embodiment, the same effect as the fourth embodiment can be obtained.

<6. Sixth Embodiment>
FIG. 15 is a block diagram showing an electrical configuration of a projection display apparatus 4000a according to the sixth embodiment of the present invention. FIG. 16 is a time chart showing the operation of this embodiment. In the first to fifth embodiments, the host CPU 60 supplies individual chip select signals CS_R, CS_G, and CS_B to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, respectively. In contrast, in the present embodiment, the host CPU 60 supplies a common chip select signal CS to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B. Then, the host CPU 60 initializes the count value CNT2 in each of the electro-optical devices 100R, 100G, and 100B when a predetermined time before the switching timing of a cycle that is an integral multiple of the cycle of the application sequence update control occurs. The following processing to make it start is started.

  First, as shown in FIG. 16, the host CPU 60 sets the chip select signal CS to an active level, and serial data SDI indicating three initialization commands for the control circuits 30 of the electro-optical devices 100R, 100G, and 100B. The data is sequentially transmitted in synchronization with the serial clock SCLK. The control circuit 30 of the electro-optical device 100R selects and receives the first initialization command from the serial data SDI transmitted in synchronization with the serial clock SCLK. Next, the control circuit 30 of the electro-optical device 100G selects and receives the second initialization command from the serial data SDI transmitted in synchronization with the serial clock SCLK. Next, the control circuit 30 of the electro-optical device 100B selects and receives the third initialization command from the serial data SDI transmitted in synchronization with the serial clock SCLK.

  After the initialization command is received by the control circuits 30 of the electro-optical devices 100A, 100B, and 100C in this way, the host CPU 60 has a switching timing of a cycle that is an integral multiple of the cycle of the application order update control. At a timing synchronized with the vertical synchronization signal VSYNC, an initialization synchronization signal ISYNC is supplied to the control circuits 30 of the electro-optical devices 100A, 100B, and 100C.

The control signal processing unit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B executes the initialization command received in advance when the initialization synchronization signal ISYNC is given, and initializes the count value CNT2. I do.
Also in this embodiment, the same effect as the first to third embodiments can be obtained.

<7. Seventh Embodiment>
FIG. 17 is a time chart showing the operation of the projection display apparatus according to the seventh embodiment of the present invention. In the sixth embodiment (FIG. 16), the host CPU 60 sends an initialization command to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, and then is an integral multiple of the cycle of update control of the gradation voltage application order. The initialization synchronization signal ISYNC is transmitted to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B at the timing that occurs in the cycle of the timing and in synchronization with the vertical synchronization signal VSYNC. In the present embodiment, the host CPU 60 does not transmit the initialization synchronization signal ISYNC. Instead, the host CPU 60 sets the chip select signal CS to an active level, sends an initialization command to each control circuit 30 of the electro-optical devices 100R, 100G, and 100B, and then performs update control of the application order of gradation voltages. The chip select signal CS is set to an inactive level at a timing that occurs at a cycle that is an integral multiple of the cycle and that is synchronized with the vertical synchronization signal VSYNC.

After receiving the initialization command, the control signal processing unit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B is initialized at the timing when the change from the active level to the inactive level of the chip select signal for each is detected. The count command CNT2 of the counter 33 is initialized.
Also in this embodiment, the same effect as the third embodiment can be obtained.

<8. Eighth Embodiment>
FIG. 18 is a time chart showing the operation of the projection display apparatus according to the eighth embodiment of the present invention. In the seventh embodiment (FIG. 17), the host CPU 60 sends an initialization command to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, and then is an integral multiple of the cycle of update control of the gradation voltage application order. The chip select signal CS is changed from the active level to the inactive level at a timing that occurs in the period of 1 and that is synchronized with the vertical synchronization signal VSYNC. In contrast, in the present embodiment, the host CPU 60 sets the chip select signal CS to an active level, sends an initialization command to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, and then the vertical synchronization signal VSYNC. The chip select signal CS is set to an inactive level at a timing prior to the timing synchronized with.

The control signal processing unit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B receives the initialization command and detects a change from the active level to the inactive level of the chip select signal for each of the control signals. An initialization command is executed at a timing synchronized with the vertical synchronization signal VSYNC, and the count value CNT2 of the counter 33 is initialized.
In this embodiment, the same effect as in the fifth and sixth embodiments can be obtained.

  A modification from the seventh embodiment (FIG. 17) to the eighth embodiment (FIG. 18) may be applied to the sixth embodiment (FIG. 16). In other words, the host CPU 60 sends an initialization command to the control circuits 30 of the electro-optical devices 100R, 100G, and 100B, and then occurs at a cycle that is an integral multiple of the cycle of the gradation voltage application sequence update control. Thus, the initialization synchronization signal ISYNC is transmitted before the timing synchronized with the vertical synchronization signal VSYNC. The control signal processing unit 31 of each control circuit 30 of the electro-optical devices 100R, 100G, and 100B receives an initialization command and synchronizes with the vertical synchronization signal VSYNC after receiving the initialization synchronization signal ISYNC. The count value CNT2 of the counter 33 is initialized.

<9. Ninth Embodiment>
FIG. 19 is a block diagram showing the configuration of the electro-optical device according to the ninth embodiment of the invention. In the present embodiment, the entire pixel portion is divided into two pixel portions 10a and 10b. A driving circuit 20a including a scanning line driving circuit 22a and a signal line driving circuit 24a is provided to drive the pixel portion 10a, and a scanning line driving circuit 22b and a signal line driving circuit are provided to drive the pixel portion 10b. A drive circuit 20b composed of 24b is provided. A control circuit 30a is provided for controlling the drive circuit 20a, and a control circuit 30b is provided for controlling the drive circuit 20b. In the control circuits 30a and 30b, the update control of the application order of the gradation voltages to the plurality of signal lines in the wiring block similar to that described in the first embodiment is performed.

  Here, in the control circuits 30a and 30b, for example, using the circuit comprising the counters 32 and 33, the adder 34, and the pattern generator 35 shown in FIG. . Therefore, for example, due to the influence of noise or the like, there is a phase shift between the update control of the gradation voltage application order for the pixel portion 10a and the update control of the gradation voltage application order for the pixel portion 10b. May occur. When such a phase shift occurs, display unevenness occurs at the boundary between the pixel portion 10a and the pixel portion 10b.

  Therefore, in the present embodiment, a synchronization control unit (not shown) (for example, one corresponding to the host CPU 60 in the first to eighth embodiments) switches at a timing at which the cycle is an integral multiple of the cycle of the application sequence update control. At the timing synchronized with the vertical synchronization signal VSYNC, the application sequence update control in each of the control circuits 30a and 30b is initialized. Thereby, the update control of the application order of the gradation voltage is synchronized between the pixel portion 10a and the pixel portion 10b, and it is possible to prevent display unevenness from occurring at the boundary between the pixel portion 10a and the pixel portion 10b.

<10. Modification>
The first to ninth embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.

(1) In the first to eighth embodiments, the host CPU 60 sends an initialization command to each control circuit 30 of the electro-optical devices 100A, 100B, and 100C, and then instructs the execution timing of the initialization command. The synchronization signal ISYNC for initialization is supplied or the chip select signal CS is raised. However, instead of doing so, the control circuits 30 of the electro-optical devices 100A, 100B, and 100C may execute the initialization command in the first vertical synchronization signal VSYNC after receiving the initialization command. Also in this aspect, the same effects as those in the above embodiments can be obtained.

(2) In the first embodiment, since the count value CNT1 of the counter 32 is initialized every time the internal vertical synchronization signal VS is generated, the control signal processing unit 31 executes the counter 33 when the initialization command is executed. Only the count value CNT2 was initialized. However, there may be a configuration in which the count value CNT1 of the counter 32 is not initialized when the internal vertical synchronization signal VS is generated. In this case, the control signal processing unit 31 may be configured to initialize both the count value CNT2 of the counter 33 and the count value CNT1 of the counter 32 when the initialization command is executed.

(3) In each of the embodiments described above, the period of the update control of the application order of the gradation voltages to the plurality of signal lines in the wiring block is a period that is an integral multiple of the vertical scanning period. However, in the projection display device and the electro-optical device, the grayscale voltage applied to the plurality of signal lines in the wiring block is not an integer multiple of the vertical scanning period, but an integral multiple of the horizontal scanning period. There may be a case where periodic update control of the application order is performed. In such a case, the host CPU 60 synchronizes the gradation voltage applied to the plurality of signal lines in the wiring block in each of the plurality of drive circuits in synchronization with a cycle that is an integral multiple of the horizontal scanning period that is the cycle of the update control. Initialization of the application sequence update control may be performed.

(4) In each of the above embodiments, the update control of the application order of the gradation voltages performed by the plurality of drive circuits independently of each other is the object of synchronization. However, the application target of the present invention is not limited to this. In the case where periodic update control of some drive condition that is performed independently by each other, a plurality of drive circuits that drive the pixel unit may be subjected to synchronization.

(5) The liquid crystal element 42 is merely an example of an electro-optical element. The electro-optic element applied to the present invention is driven by distinguishing between a self-luminous type that emits light itself and a non-luminous type that changes the transmittance or reflectance of external light (for example, the liquid crystal element 42), or by supplying current. There is no distinction between the current driven type and the voltage driven type driven by applying an electric field (voltage). For example, an organic EL element, an inorganic EL element, an LED (Light Emitting Diode), a field electron emission element (FE (Field-Emission) element), a surface conduction electron emission element (SE (Surface Conduction Electron Emitter) element), a ballistic electron The present invention is applied to the electro-optical device 100 using various electro-optical elements such as a emitting element (BS (Ballistic Electron Emitting) element), an electrophoretic element, and an electrochromic element. That is, the electro-optic element is an electro-optic material (for example, a liquid crystal 425) whose gradation (optical characteristics such as transmittance and luminance) changes in accordance with an electrical action such as supply of current or application of voltage (electric field). As a driven element (typically, a display element whose gray scale is controlled according to a gray scale signal).

<11. Application example>
The present invention can be used for various electronic devices other than the projection display device. 20 and 21 illustrate specific modes of electronic devices to which the present invention is applied.

  FIG. 20 is a perspective view of a portable personal computer employing an electro-optical device. The personal computer 2000 includes an electro-optical device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed. Among such personal computers 2000, there is a configuration in which the electro-optical device 100 includes a plurality of pixel units, and performs the above-described update control of the gradation voltage application order for each pixel unit. By applying the present invention to such a personal computer 2000, it is possible to prevent the occurrence of the vertical noise described above.

  FIG. 21 is a perspective view of a mobile phone. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled. The present invention is also applicable to such a mobile phone.

  Electronic devices to which the present invention is applied include, in addition to the devices illustrated in FIG. 1, FIG. 20, and FIG. 21, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, car navigation systems. Equipment, on-vehicle display (instrument panel), electronic notebook, electronic paper, calculator, word processor, workstation, videophone, POS terminal, printer, scanner, copier, video player, equipment with touch panel, etc. .

100, 100R, 100G, 100B... Electro-optical device, 10, 10a, 10b... Pixel portion, PIX... Pixel circuit, 12 .. scanning line, 14... Signal line, 20, 20a, 20b. , 22, 22a, 22b... Scanning line drive circuit, 24, 24a, 24b... Signal line drive circuit, 30, 30a, 30b... Control circuit, 42. ] To 57 [J] ... demultiplexer, 53 [1] to 53 [J] ... multiplexer, 56 [1] to 56 [J] ... drive voltage generation circuit, 60 ... host CPU, 70 ... ... Image input unit, 31... Control signal processing unit, 32 and 33... Counter, 34.

Claims (10)

A pixel unit having a plurality of scanning lines and a plurality of signal lines intersecting with each other, and having a plurality of pixel circuits respectively arranged corresponding to each intersection of the plurality of scanning lines and the plurality of signal lines;
A plurality of scanning lines are sequentially selected within one vertical scanning period, and a plurality of pixel circuits associated with each intersection of the selected scanning line and the plurality of signal lines are connected to the plurality of signal lines. A drive circuit;
The signal lines for dividing the plurality of signal lines into a plurality of wiring blocks, sequentially selecting each signal line belonging to the wiring block within one horizontal scanning period for each wiring block, and applying a gradation voltage to the selected signal line A drive circuit;
A plurality of electro-optic devices each comprising: a control circuit that performs periodic update control of the application order of gradation voltages to a plurality of signal lines in the plurality of wiring blocks in the plurality of wiring blocks;
By repeating the operation of simultaneously initializing the update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices, the plurality of the plurality of electro-optical devices An electronic apparatus comprising: synchronization means for synchronizing update control of an application order of gradation voltages to a plurality of signal lines in the wiring block in each of the electro-optical devices.   The synchronization means has a cycle having a length that is an integral multiple of the cycle of update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices. 2. The operation of simultaneously initializing periodic update control of the application order of gradation voltages to a plurality of signal lines in the wiring block in each control circuit of a plurality of electro-optical devices is performed. Electronic equipment described in 1. Each control circuit of the plurality of electro-optical devices performs periodic update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in a cycle having an integral multiple of the vertical scanning period. Run,
The synchronization means has a cycle having a length that is an integral multiple of the cycle of update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices. Periodically updating the application order of gradation voltages to a plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices in synchronization with a vertical synchronization signal instructing switching of a vertical scanning period The electronic apparatus according to claim 2, wherein the operation for simultaneously initializing the control is repeated. A host CPU that supplies various control information to the control circuits of the plurality of electro-optical devices functions as the synchronization unit;
The host CPU has a cycle having a length that is an integral multiple of the cycle of update control of the application sequence of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices. An initialization synchronization signal for instructing the initialization is transmitted to each control circuit of the plurality of electro-optical devices in synchronization with a vertical synchronization signal for instructing switching of a scanning period, and each control of the plurality of electro-optical devices is transmitted. 4. The electronic device according to claim 3, wherein the circuit initializes update control of an application order of gradation voltages to a plurality of signal lines in the wiring block at a reception timing of the initialization synchronization signal. 5. . A host CPU that supplies various control information to the control circuits of the plurality of electro-optical devices functions as the synchronization unit;
The host CPU transmits an initialization command instructing the initialization in advance to each control circuit of the plurality of electro-optical devices, and then transmits a plurality of signals in the wiring block in each control circuit of the plurality of electro-optical devices. The timing at which the grayscale voltage is applied to the line is updated at a cycle having an integral multiple of the cycle of the update control cycle, and the initial timing is synchronized with the vertical synchronization signal instructing switching of the vertical scanning period. The synchronization signal for initialization is transmitted to each control circuit of the plurality of electro-optical devices, and each control circuit of the plurality of electro-optical devices receives the initialization command and receives the initialization synchronization signal at the reception timing of the synchronization signal for initialization. 4. The electronic apparatus according to claim 3, wherein update control of the application order of gradation voltages to a plurality of signal lines in the wiring block is initialized. A host CPU that supplies various control information to the control circuits of the plurality of electro-optical devices functions as the synchronization unit;
The host CPU sets the chip select signal for each of the control circuits of the plurality of electro-optical devices in advance to an active level and causes the control circuits of the plurality of electro-optical devices to receive an initialization command instructing the initialization. A timing that occurs at a cycle having a length that is an integral multiple of the cycle of the update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices, At a timing synchronized with a vertical synchronization signal instructing switching of the vertical scanning period, a chip select signal for each of the control circuits of the plurality of electro-optical devices is simultaneously changed from an active level to an inactive level,
The control circuits of the plurality of electro-optical devices are configured to output gradation voltages to the plurality of signal lines in the wiring block when the chip select signal changes from an active level to an inactive level after receiving the initialization command. 4. The electronic apparatus according to claim 3, wherein update control of the application order is initialized. A host CPU that supplies various control information to the control circuits of the plurality of electro-optical devices functions as the synchronization unit;
The host CPU sets the chip select signal for each of the control circuits of the plurality of electro-optical devices in advance to an active level, causes the control circuits of the plurality of electro-optical devices to receive an initialization command instructing the initialization, and then A timing that occurs at a cycle having a length that is an integral multiple of the cycle of the update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices, A synchronization signal for initialization is transmitted to the control circuits of the plurality of electro-optical devices, a predetermined time before a timing synchronized with a vertical synchronization signal instructing switching of the vertical scanning period,
The control circuits of the plurality of electro-optical devices are configured to perform gradations on the plurality of signal lines in the wiring block at a timing synchronized with the initial vertical synchronization signal after receiving the initialization command and the initialization synchronization signal. The electronic device according to claim 3, wherein update control of a voltage application order is initialized. A host CPU that supplies various control information to the control circuits of the plurality of electro-optical devices functions as the synchronization unit;
The host CPU sets the chip select signal for each of the control circuits of the plurality of electro-optical devices in advance to an active level, causes the control circuits of the plurality of electro-optical devices to receive an initialization command instructing the initialization, and then A timing that occurs at a cycle having a length that is an integral multiple of the cycle of the update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in each control circuit of the plurality of electro-optical devices, A chip select signal for each of the control circuits of the plurality of electro-optical devices is simultaneously changed from an active level to an inactive level at a predetermined time before a timing synchronized with a vertical synchronization signal instructing switching of the vertical scanning period. Change
The control circuits of the plurality of electro-optical devices receive the initialization command, and at a timing synchronized with a first vertical synchronization signal after a change from an active level to an inactive level of the chip select signal, 4. The electronic apparatus according to claim 3, wherein update control of the application order of gradation voltages to a plurality of signal lines in the wiring block is initialized. A plurality of pixel units each having a plurality of scanning lines and a plurality of signal lines intersecting each other, and each having a plurality of pixel circuits arranged corresponding to each intersection of the plurality of scanning lines and the plurality of signal lines When,
The plurality of scanning lines in each pixel portion of the plurality of pixel portions are sequentially selected within one vertical scanning period, and a plurality of pixel circuits associated with each intersection of the selected scanning line and the plurality of signal lines are provided. Scanning line driving means connected to the plurality of signal lines;
A plurality of signal line driving circuits respectively associated with the plurality of pixel units, wherein the plurality of signal lines of each pixel unit are divided into a plurality of wiring blocks, and each wiring block is subjected to the processing within one horizontal scanning period. A plurality of signal line drive circuits for sequentially selecting each signal line belonging to the wiring block and applying a gradation voltage to the selected signal line;
A plurality of control circuits that periodically update the application order of gradation voltages to a plurality of signal lines in the wiring block in each of the plurality of wiring blocks in each of the plurality of signal line driving circuits;
Synchronization means for repeatedly performing the operation of simultaneously initializing periodic update control of the application sequence of gradation voltages to the plurality of signal lines in the wiring block in the plurality of control circuits at intervals. An electro-optical device. The synchronization means has a period that is an integral multiple of the period of update control of the application order of gradation voltages to the plurality of signal lines in the wiring block in the plurality of control circuits in the plurality of control circuits. The electro-optical device according to claim 9, wherein the operation of simultaneously initializing periodic update control of the application order of gradation voltages to a plurality of signal lines in the wiring block is repeated.

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