JP2011027892A - Electrooptical device, electronic device, and method and circuit for driving electrooptical device - Google Patents

Electrooptical device, electronic device, and method and circuit for driving electrooptical device Download PDF

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JP2011027892A
JP2011027892A JP2009171937A JP2009171937A JP2011027892A JP 2011027892 A JP2011027892 A JP 2011027892A JP 2009171937 A JP2009171937 A JP 2009171937A JP 2009171937 A JP2009171937 A JP 2009171937A JP 2011027892 A JP2011027892 A JP 2011027892A
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Shinsuke Fujikawa
紳介 藤川
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To appropriately reverse a polarity of a voltage applied to an electrooptical device without needing any electric discharging operation in a configuration where a potential of a common electrode is varied. <P>SOLUTION: A reversal potential LCCOMX sequentially varied from one of a high-side potential VH and a low-side potential VL to the other by unit period F is supplied to a reversal potential line 24. A pixel circuit PIX includes a liquid crystal element 50 including a pixel electrode 52 and a common electrode 54, and a first control switch TC1 interposed between the pixel electrode 52 and the reversal potential line 24. A common potential LCCOM obtained by reversing a potential of the reversal potential LCCOMX is supplied to the common electrode 54. A driving circuit controls the first control switch TC1 to an ON state during a reversal period W where the common potential LCCOM is varied after application of a voltage VA to the liquid crystal element 50, and the first control switch TC1 to an OFF state during a reversal period W where the common potential LCCOM is varied after application of a voltage VB (VB<VA) to the liquid crystal element 50. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、液晶素子などの電気光学素子を駆動する技術に関する。   The present invention relates to a technique for driving an electro-optical element such as a liquid crystal element.

液晶素子などの電気光学素子の駆動には、画素電極と共通電極(対向電極)との間の電圧の極性を順次に反転させる交流駆動が採用される。例えば特許文献1には、共通電極の電位を変動させて液晶素子の印加電圧の極性を反転させることで、指定階調に応じて信号線から画素電極に供給される電位(以下「階調電位」という)の振幅を低減する技術が開示されている。   For driving an electro-optical element such as a liquid crystal element, an AC drive that sequentially reverses the polarity of the voltage between the pixel electrode and the common electrode (counter electrode) is employed. For example, in Patent Document 1, by changing the potential of the common electrode and inverting the polarity of the voltage applied to the liquid crystal element, the potential supplied from the signal line to the pixel electrode in accordance with the specified gradation (hereinafter referred to as “gradation potential”). ")" Is disclosed.

しかし、特許文献1の技術では、共通電極の電位に連動して画素電極の電位が変動するから、信号線と画素電極との接続を制御する選択スイッチの抵抗が低下する可能性がある。例えば、選択スイッチをNチャネル型のトランジスタで構成した場合、共通電極の電位に連動して画素電極の電位が低下すると、選択スイッチのゲート−ソース間の電圧が上昇してオン状態に遷移する。したがって、電気光学素子に保持された電荷が放電されるという問題がある。以上の問題を回避するには、選択スイッチのゲート(走査線)の電位の振幅を充分に確保することで、選択スイッチの書込み能力(低いオン抵抗)と絶縁能力(高いオフ抵抗)とを担保する必要が生じる。   However, in the technique of Patent Document 1, since the potential of the pixel electrode varies in conjunction with the potential of the common electrode, the resistance of the selection switch that controls the connection between the signal line and the pixel electrode may be reduced. For example, in the case where the selection switch is formed of an N-channel transistor, when the potential of the pixel electrode is decreased in conjunction with the potential of the common electrode, the voltage between the gate and the source of the selection switch is increased to be turned on. Therefore, there is a problem that the electric charge held in the electro-optical element is discharged. In order to avoid the above problems, by ensuring sufficient amplitude of the potential of the gate (scanning line) of the selection switch, the writing capability (low on-resistance) and insulation capability (high off-resistance) of the selection switch are ensured. Need to do.

特許文献1の問題を解決するための技術として、特許文献2には、各液晶素子に対する階調電位の供給後で共通電極の電位の反転前の期間(全走査線選択期間)内に、各液晶素子に保持された電荷を放電する動作(以下「放電動作」という)を実行する技術が開示されている。   As a technique for solving the problem of Patent Document 1, Patent Document 2 describes that each period within the period (all scanning line selection periods) after the supply of the gradation potential to each liquid crystal element and before the inversion of the potential of the common electrode. A technique for performing an operation (hereinafter referred to as “discharge operation”) for discharging electric charges held in a liquid crystal element is disclosed.

特開平8−334741号公報Japanese Patent Laid-Open No. 8-334741 特開2004−109824号公報JP 2004-109824 A 特開2006−84846号公報JP 2006-84846 A

しかし、特許文献2の技術では、共通電極の電位の反転前に各電気光学素子の電荷が放電されるから、電荷を放電しない構成と比較して画像のコントラスト(明暗差)が低下するという問題がある。例えば、ノーマリ−ブラックモードの液晶素子を電気光学素子として採用した構成では、最高階調(例えば白色)に制御された各電気光学素子が放電動作で最低階調(例えば黒色)に制御されるから、実際に観察者が知覚する階調は、目標の階調と比較して低い階調となる。   However, in the technique of Patent Document 2, since the charge of each electro-optical element is discharged before the potential of the common electrode is inverted, the contrast (brightness difference) of the image is reduced as compared with a configuration in which the charge is not discharged. There is. For example, in a configuration employing a normally-black mode liquid crystal element as an electro-optic element, each electro-optic element controlled to the highest gradation (for example, white) is controlled to the lowest gradation (for example, black) by the discharge operation. The gradation actually perceived by the observer is a lower gradation than the target gradation.

なお、例えば特許文献3に開示されるように、電気光学素子の点灯/消灯を指示するデータを保持する記憶回路が画素回路に内蔵された構成によれば、放電動作を実行することなく電気光学素子の印加電圧の極性を適切に反転することが可能である。しかし、多数の素子が必要な記憶回路を画素回路に内蔵する必要があるから、画素の高精細化が制限されるという問題がある。   For example, as disclosed in Patent Document 3, according to the configuration in which the storage circuit that holds data for instructing on / off of the electro-optical element is built in the pixel circuit, the electro-optic is performed without performing the discharge operation. It is possible to appropriately reverse the polarity of the voltage applied to the element. However, since it is necessary to incorporate a memory circuit that requires a large number of elements in the pixel circuit, there is a problem that high definition of the pixel is limited.

また、閾値電圧が高いトランジスタを選択スイッチとして利用すれば、共通電極の電位に連動して画素電極の電位が変動した場合でも選択スイッチをオフ状態に維持することが可能である。しかし、選択スイッチを制御する走査信号の振幅を増加させる必要があるから、高耐圧の駆動回路が必要になるという問題や、駆動回路の消費電力が増大するという問題が発生し得る。   Further, if a transistor having a high threshold voltage is used as a selection switch, the selection switch can be maintained in an OFF state even when the potential of the pixel electrode varies in conjunction with the potential of the common electrode. However, since it is necessary to increase the amplitude of the scanning signal for controlling the selection switch, there may arise a problem that a high-breakdown-voltage drive circuit is required and a problem that the power consumption of the drive circuit increases.

以上の事情を考慮して、本発明は、共通電極の電位を変動させる構成のもとで放電動作を必要とせずに電気光学素子の印加電圧の極性を適切に反転させることを目的とする。   In view of the above circumstances, an object of the present invention is to appropriately reverse the polarity of the voltage applied to the electro-optic element without requiring a discharge operation under a configuration in which the potential of the common electrode is varied.

以上の課題を解決するために、本発明に係る電気光学装置は、高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、反転用電位が高位側電位となる単位期間にて低位側電位に設定されて反転用電位が低位側電位となる単位期間にて高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子と、画素電極と反転用電位線との接続を制御する第1制御スイッチ(例えば図2や図13の第1制御スイッチTC1)とを具備する。以上の態様においては、共通電極の共通電位とは高低が逆転した反転用電位が供給される反転用電位線と画素電極との導通/非導通が第1制御スイッチで制御される。したがって、電気光学素子の両電極間に対する電圧の印加以後に第1制御スイッチをオン状態に制御する(画素電極に反転用電位を供給する)ことで、共通電位を反転させて電気光学素子の両電極間の電圧の極性を反転させた場合でも電気光学素子の階調は維持される。以上の構成においては、特許文献2の技術で必要となる放電動作が不要であるから、放電動作に起因したコントラストの低下が抑制されるという利点がある。なお、本発明により放電動作が原理的に不要になるとは言え、本発明の構成のもとで放電動作を実行する態様を本発明の範囲から排除する趣旨ではない。   In order to solve the above-described problems, an electro-optical device according to the present invention includes an inversion potential line to which an inversion potential that is sequentially changed every unit period is supplied from one of a high-side potential and a low-side potential to the other. A common electrode supplied with a common potential that is set to a low potential in a unit period in which the inversion potential is a high potential and is set to a high potential in a unit period in which the inversion potential is a low potential An electro-optical element including a pixel electrode and a first control switch (for example, the first control switch TC1 in FIGS. 2 and 13) for controlling the connection between the pixel electrode and the inversion potential line are provided. In the above aspect, the first control switch controls conduction / non-conduction between the inversion potential line to which the inversion potential whose level is inverted from the common potential of the common electrode is supplied and the pixel electrode. Therefore, the first control switch is controlled to be in an ON state after the voltage is applied between both electrodes of the electro-optic element (the inversion potential is supplied to the pixel electrode), so that the common potential is reversed and both the electro-optic elements are turned on. Even when the polarity of the voltage between the electrodes is reversed, the gradation of the electro-optical element is maintained. In the above configuration, since the discharge operation required in the technique of Patent Document 2 is unnecessary, there is an advantage that a decrease in contrast due to the discharge operation is suppressed. Although the discharge operation is not necessary in principle according to the present invention, the aspect of executing the discharge operation under the configuration of the present invention is not intended to exclude from the scope of the present invention.

本発明の好適な態様に係る電気光学装置は、駆動回路を具備し、駆動回路は、指定階調に応じた階調電位を単位期間にて画素電極に供給する一方、電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオン状態に制御し、電気光学素子の両電極間の電圧が第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオフ状態に制御する。以上の態様においては、電気光学素子に第1電圧を印加した場合の共通電位の変動時に第1制御スイッチがオン状態に制御され、電気光学素子に第2電圧を印加した場合の共通電位の変動時に第1制御スイッチがオフ状態に制御される。したがって、第1電圧の印加時および第2電圧の印加時の何れにおいても、電気光学素子の階調を維持したまま印加電圧の極性を反転させることが可能である。なお、第1電圧は、例えば、ノーマリーブラックモードの白色に対応する電圧やノーマリーホワイトモードの黒色に対応する電圧であり、第2電圧は、例えば、ノーマリーブラックモードの黒色に対応する電圧やノーマリーホワイトモードの白色に対応する電圧である。   An electro-optical device according to a preferred aspect of the present invention includes a drive circuit, and the drive circuit supplies a gradation potential corresponding to a specified gradation to the pixel electrode in a unit period, while both electrodes of the electro-optic element. In the case where a gray-scale potential whose voltage is the first voltage is supplied, the first control switch is controlled to be in an on state in a period including a time point when the common potential fluctuates after the supply of the gray-scale potential. When a gradation potential is supplied such that the voltage between the two electrodes is a second voltage different from the first voltage, the first control switch is turned on during a period including the time when the common potential fluctuates after the supply of the gradation potential. Control to off state. In the above aspect, the first control switch is controlled to be on when the common potential is changed when the first voltage is applied to the electro-optic element, and the common potential is changed when the second voltage is applied to the electro-optic element. Sometimes the first control switch is controlled to the off state. Accordingly, it is possible to reverse the polarity of the applied voltage while maintaining the gradation of the electro-optic element both when the first voltage is applied and when the second voltage is applied. The first voltage is, for example, a voltage corresponding to white in the normally black mode or a voltage corresponding to black in the normally white mode, and the second voltage is, for example, a voltage corresponding to black in the normally black mode. Or a voltage corresponding to white in normally white mode.

本発明の好適な態様に係る電気光学装置は、第1制御スイッチを制御する制御信号が供給される制御線と、第1制御スイッチのゲートと制御線との接続を制御する第2制御スイッチ(例えば図2や図13の第2制御スイッチTC2)と、第1制御スイッチのゲートの電位を保持する第1制御用容量(例えば図2や図13の制御用容量C1)とを具備する。以上の態様においては、第1制御スイッチを制御する制御信号の電位が第1制御用容量に保持されるから、共通電位の変動時を含む期間にて第1制御スイッチを継続的にオン状態またはオフ状態に維持することが可能である。さらに好適な態様に係る電気光学装置は、共通電位が供給される共通電位線と、共通電位線と画素電極との間に介在する保持容量と、第1制御スイッチのゲートと共通電位線との間に介在する第2制御用容量(例えば図13の制御用容量C2)とを具備し、第1制御用容量は、第1制御スイッチのゲートと反転用電位線との間に介在する。以上の態様においては、第1制御スイッチのゲートの電位に対する共通電位の作用と反転用電位の作用とが相殺されるから、第1制御スイッチのゲートの電位が有効に保持される。他方、第1制御用容量における第1制御スイッチとは反対側の電極は反転用電位線に接続され、第2制御用容量における第1制御スイッチとは反対側の電極は共通電位線に接続されるから、第1制御スイッチのゲートの電位の保持に専用される配線(例えば図2の容量線26)は不要である。したがって、電気光学装置の構成が簡素化されるという利点がある。   The electro-optical device according to a preferred aspect of the present invention includes a control line to which a control signal for controlling the first control switch is supplied, and a second control switch for controlling connection between the gate of the first control switch and the control line ( For example, the second control switch TC2) of FIG. 2 or 13 and a first control capacitor (for example, the control capacitor C1 of FIG. 2 or 13) that holds the potential of the gate of the first control switch are provided. In the above aspect, since the potential of the control signal for controlling the first control switch is held in the first control capacitor, the first control switch is continuously turned on in a period including the time when the common potential changes. It can be kept off. The electro-optical device according to a more preferable aspect includes a common potential line to which a common potential is supplied, a storage capacitor interposed between the common potential line and the pixel electrode, a gate of the first control switch, and the common potential line. A second control capacitor (for example, a control capacitor C2 in FIG. 13) is provided between the first control switch and the inversion potential line. In the above aspect, since the action of the common potential and the action of the inversion potential with respect to the potential of the gate of the first control switch are canceled, the potential of the gate of the first control switch is effectively held. On the other hand, the opposite electrode of the first control capacitor to the first control switch is connected to the inversion potential line, and the opposite electrode of the second control capacitor to the first control switch is connected to the common potential line. Therefore, a wiring dedicated for holding the potential of the gate of the first control switch (for example, the capacitor line 26 in FIG. 2) is unnecessary. Therefore, there is an advantage that the configuration of the electro-optical device is simplified.

本発明の好適な態様に係る電気光学装置は、相交差する走査線および信号線と、走査線の選択時に信号線と画素電極とを接続する選択スイッチとを具備し、選択スイッチと第2制御スイッチとは共通の信号(例えば走査信号Y[m])で制御される。以上の態様においては、選択スイッチと第2制御スイッチとが共通の信号で制御されるから、双方が別個の信号で制御される構成と比較して電気光学装置の構成の簡素化(配線数の削減)が実現される。   An electro-optical device according to a preferred aspect of the present invention includes a scanning line and a signal line that intersect each other, and a selection switch that connects the signal line and the pixel electrode when the scanning line is selected. The switch is controlled by a common signal (for example, scanning signal Y [m]). In the above aspect, since the selection switch and the second control switch are controlled by a common signal, the configuration of the electro-optical device can be simplified (the number of wires) compared to a configuration in which both are controlled by separate signals. Reduction) is realized.

本発明の具体的な態様に係る電気光学装置は、相交差する複数の走査線および複数の信号線と、高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、複数の走査線と複数の信号線との各交差に対応して配置された複数の画素回路と、各画素回路を駆動する駆動回路とを具備し、複数の画素回路の各々は、反転用電位が高位側電位となる単位期間にて低位側電位に設定されて反転用電位が低位側電位となる単位期間にて高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子と、走査線の選択時に信号線と画素電極とを接続する選択スイッチと、画素電極と反転用電位線との接続を制御する第1制御スイッチとを含み、駆動回路は、単位期間にて複数の走査線の各々を順次に選択するとともに当該走査線に対応する各画素回路の指定階調に応じた階調電位を複数の信号線の各々に供給する一方、複数の画素回路の各々について、電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオン状態に制御し、電気光学素子の両電極間の電圧が第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオフ状態に制御する。以上の態様でも、特許文献2の放電動作が不要であるという所期の効果が実現される。   An electro-optical device according to a specific aspect of the invention includes a plurality of scanning lines and a plurality of signal lines that intersect each other, and one for a reversal that sequentially changes from one of a high potential and a low potential to every other unit period. An inversion potential line to which a potential is supplied, a plurality of pixel circuits arranged corresponding to each intersection of the plurality of scanning lines and the plurality of signal lines, and a drive circuit for driving each pixel circuit, Each of the plurality of pixel circuits has a common potential that is set to a low potential in a unit period in which the inversion potential is a high potential and is set to a high potential in a unit period in which the inversion potential is a low potential. , An electro-optical element including a common electrode and a pixel electrode, a selection switch for connecting the signal line and the pixel electrode when the scanning line is selected, and a first for controlling the connection between the pixel electrode and the inversion potential line. Including a control switch and a drive circuit in a unit period. Each of the plurality of scanning lines is sequentially selected and a gradation potential corresponding to the designated gradation of each pixel circuit corresponding to the scanning line is supplied to each of the plurality of signal lines, while each of the plurality of pixel circuits In the case where a gradation potential in which the voltage between both electrodes of the electro-optic element is the first voltage is supplied, the first control switch is turned on in a period including the time when the common potential fluctuates after the supply of the gradation potential. And a period including a time point at which the common potential fluctuates after the supply of the gradation potential when the gradation potential is supplied such that the voltage between both electrodes of the electro-optic element is a second voltage different from the first voltage. The first control switch is controlled to be in the OFF state. Also in the above aspect, the expected effect that the discharge operation of Patent Document 2 is unnecessary is realized.

以上の各態様に係る電気光学装置は各種の電子機器に利用される。電子機器の典型例は、電気光学装置を表示装置として利用した機器である。具体的には携帯電話機や携帯情報端末が本発明の電子機器として例示される。また、光源からの出射光を変調する光変調体として以上の各態様の電気光学装置を利用した投写型表示装置も本発明の電子機器の概念に包含される。投写型表示装置は、光線を出射する光源と、光源からの出射光を変調する以上の各態様の電気光学装置と、電気光学装置による変調光を投射面に投射する光学系とを具備する。   The electro-optical device according to each aspect described above is used in various electronic apparatuses. A typical example of an electronic device is a device that uses an electro-optical device as a display device. Specifically, a mobile phone or a portable information terminal is exemplified as the electronic apparatus of the present invention. Further, a projection display device using the electro-optical device of each of the above aspects as a light modulator that modulates light emitted from a light source is also included in the concept of the electronic apparatus of the present invention. The projection display device includes a light source that emits a light beam, the electro-optical device according to each aspect described above that modulates light emitted from the light source, and an optical system that projects the modulated light from the electro-optical device onto a projection surface.

本発明は、以上の各態様に係る電気光学装置の駆動方法としても特定される。本発明に係る駆動方法は、指定階調に応じた階調電位を単位期間にて画素電極に供給する一方、電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオン状態に制御し、電気光学素子の両電極間の電圧が第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオフ状態に制御する。以上の駆動方法によれば本発明の電気光学装置と同様の効果が実現される。   The present invention is also specified as a driving method of the electro-optical device according to each of the above aspects. In the driving method according to the present invention, a grayscale potential corresponding to a designated grayscale is supplied to the pixel electrode in a unit period, while a grayscale potential at which the voltage between both electrodes of the electro-optic element becomes the first voltage is supplied. In this case, the first control switch is controlled to be in an ON state in a period including a time point when the common potential fluctuates after the supply of the gradation potential, and the voltage between both electrodes of the electro-optic element is different from the first voltage. In the case where a gradation potential as a voltage is supplied, the first control switch is controlled to be in an off state in a period including a time when the common potential fluctuates after the supply of the gradation potential. According to the above driving method, an effect similar to that of the electro-optical device of the present invention is realized.

他の態様に係る駆動方法は、高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、反転用電位が高位側電位となる単位期間にて低位側電位に設定されて反転用電位が低位側電位となる単位期間にて高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子とを具備する電気光学装置の駆動方法であって、電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて画素電極に反転用電位を供給し、電気光学素子の両電極間の電圧が第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて画素電極に対する反転用電位の供給を禁止する。   A driving method according to another aspect includes an inversion potential line that is supplied with an inversion potential that sequentially changes from one high-side potential and a low-side potential to the other for each unit period, and the inversion potential is a high-side potential. An electro-optic element including a common electrode and a pixel electrode that are supplied with a common potential set to a high potential in a unit period that is set to a low potential in a unit period and the inversion potential becomes a low potential When the grayscale potential at which the voltage between both electrodes of the electrooptic element is the first voltage is supplied, the common potential fluctuates after the grayscale potential is supplied. When a reversal potential is supplied to the pixel electrode in a period including the voltage and a grayscale potential is supplied such that the voltage between both electrodes of the electro-optic element is a second voltage different from the first voltage, the supply of the grayscale potential is performed. Pixels in a period including the time when the common potential fluctuates thereafter It prohibits the supply of the reversing potential for electrode.

また、本発明に係る電気光学装置の駆動回路は、指定階調に応じた階調電位を単位期間にて画素電極に供給する一方、電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオン状態に制御し、電気光学素子の両電極間の電圧が第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に共通電位が変動する時点を含む期間にて第1制御スイッチをオフ状態に制御する。以上の駆動回路によれば本発明の電気光学装置と同様の効果が実現される。   In addition, the drive circuit of the electro-optical device according to the present invention supplies the gradation potential corresponding to the designated gradation to the pixel electrode in a unit period, while the voltage between both electrodes of the electro-optical element becomes the first voltage. When the gradation potential is supplied, the first control switch is controlled to be in an ON state in a period including the time when the common potential fluctuates after the supply of the gradation potential, and the voltage between both electrodes of the electro-optic element is the first. When a gradation potential that is a second voltage different from the voltage is supplied, the first control switch is controlled to be in an off state in a period including a time point when the common potential fluctuates after the supply of the gradation potential. According to the above drive circuit, the same effect as the electro-optical device of the present invention is realized.

本発明の第1実施形態に係る電気光学装置のブロック図である。1 is a block diagram of an electro-optical device according to a first embodiment of the invention. FIG. 画素回路の回路図である。It is a circuit diagram of a pixel circuit. 共通電位および反転用電位と単位期間との関係を示すタイミングチャートである。6 is a timing chart showing a relationship between a common potential and an inversion potential and a unit period. 液晶素子の印加電圧と階調(透過率,反射率)との関係を示すグラフである。It is a graph which shows the relationship between the applied voltage of a liquid crystal element, and a gradation (transmittance, reflectance). 信号線駆動回路のブロック図である。It is a block diagram of a signal line drive circuit. 信号線駆動回路の動作の説明図である。It is explanatory drawing of operation | movement of a signal line drive circuit. 液晶素子の電圧を正極性から負極性に変化させる場合のタイミングチャートである。It is a timing chart in the case of changing the voltage of a liquid crystal element from positive polarity to negative polarity. 黒色を表示する場合の画素回路の動作の説明図である。It is explanatory drawing of operation | movement of the pixel circuit in the case of displaying black. 白色を表示する場合の画素回路の動作の説明図である。It is explanatory drawing of operation | movement of the pixel circuit in the case of displaying white. 液晶素子の電圧を負極性から正極性に変化させる場合のタイミングチャートである。It is a timing chart in the case of changing the voltage of a liquid crystal element from negative polarity to positive polarity. 黒色を表示する場合の画素回路の動作の説明図である。It is explanatory drawing of operation | movement of the pixel circuit in the case of displaying black. 白色を表示する場合の画素回路の動作の説明図である。It is explanatory drawing of operation | movement of the pixel circuit in the case of displaying white. 第2実施形態に係る電気光学装置の画素回路の回路図である。FIG. 10 is a circuit diagram of a pixel circuit of an electro-optical device according to a second embodiment. 電子機器の形態(パーソナルコンピュータ)を示す斜視図である。It is a perspective view which shows the form (personal computer) of an electronic device. 電子機器の形態(携帯電話機)を示す斜視図である。It is a perspective view which shows the form (cellular phone) of an electronic device. 電子機器の形態(携帯情報端末)を示す斜視図である。It is a perspective view which shows the form (mobile information terminal) of an electronic device.

<A:第1実施形態>
図1は、本発明の第1実施形態に係る電気光学装置100のブロック図である。電気光学装置100は、画像を表示する表示体として様々な電子機器に採用される液晶装置である。図1に示すように、電気光学装置100は、複数の画素回路PIXが平面状に配列された素子部(表示領域)10と、各画素回路PIXを駆動する駆動回路30と、各画素回路PIXの駆動用の電位を生成する電位生成回路42と、駆動回路30や電位生成回路42を制御する制御回路44とを具備する。
<A: First Embodiment>
FIG. 1 is a block diagram of an electro-optical device 100 according to the first embodiment of the present invention. The electro-optical device 100 is a liquid crystal device that is employed in various electronic devices as a display body that displays an image. As shown in FIG. 1, an electro-optical device 100 includes an element portion (display area) 10 in which a plurality of pixel circuits PIX are arranged in a plane, a drive circuit 30 that drives each pixel circuit PIX, and each pixel circuit PIX. And a control circuit 44 that controls the drive circuit 30 and the potential generation circuit 42.

素子部10には、X方向に延在するM本の走査線12と、X方向に交差するY方向に延在するN本の信号線14とが形成される(MおよびNは自然数)。複数の画素回路PIXは、各走査線12と各信号線14との交差に対応して配置されて縦M行×横N列の行列状に配列する。また、素子部10には、各信号線14に対応してY方向に延在するN本の制御線16が形成され、各走査線12に対応してX方向に延在するM本の共通電位線22とM本の反転用電位線24とM本の容量線26とが形成される。   In the element unit 10, M scanning lines 12 extending in the X direction and N signal lines 14 extending in the Y direction intersecting the X direction are formed (M and N are natural numbers). The plurality of pixel circuits PIX are arranged corresponding to the intersections of the scanning lines 12 and the signal lines 14 and are arranged in a matrix of vertical M rows × horizontal N columns. In the element unit 10, N control lines 16 extending in the Y direction corresponding to the signal lines 14 are formed, and M common lines extending in the X direction corresponding to the scanning lines 12 are formed. A potential line 22, M inversion potential lines 24, and M capacitance lines 26 are formed.

図2は、各画素回路PIXの回路図である。図2においては、第m行(m=1〜M)の第n列(n〜1〜N)に位置する1個の画素回路PIXが代表的に図示されている。図2に示すように、画素回路PIXは、液晶素子50と3個のスイッチ(選択スイッチTSL,第1制御スイッチTC1,第2制御スイッチTC2)と2個の容量素子(保持容量CS,制御用容量C1)とを含んで構成される。各スイッチ(TSL,TC1,TC2)は、例えば素子基板の面上に形成された任意の導電型(本形態ではNチャネル型)の薄膜トランジスタで構成される。ただし、相補型のトランジスタ(例えばトランスファーゲート)を各スイッチ(TSL,TC1,TC2)として採用すれば、各々の駆動に必要な電圧を低減することも可能である。   FIG. 2 is a circuit diagram of each pixel circuit PIX. In FIG. 2, one pixel circuit PIX located in the nth column (n-1 to N) of the mth row (m = 1 to M) is representatively shown. As shown in FIG. 2, the pixel circuit PIX includes a liquid crystal element 50, three switches (selection switch TSL, first control switch TC1, second control switch TC2) and two capacitance elements (holding capacity CS, control). Capacitance C1). Each switch (TSL, TC1, TC2) is composed of, for example, an arbitrary conductive type (N-channel type in this embodiment) thin film transistor formed on the surface of the element substrate. However, if a complementary transistor (for example, a transfer gate) is employed as each switch (TSL, TC1, TC2), the voltage required for each drive can be reduced.

液晶素子50は、画素電極52と共通電極(対向電極)54と両電極間の液晶56とで構成される電気光学素子である。画素電極52は、素子基板(図示略)の面上に画素回路PIX毎に独立に形成され、共通電極54は、素子基板に対向する対向基板(図示略)の面上に複数の画素回路PIXにわたって共通に形成される(図1参照)。画素電極52と共通電極54との間の液晶56は、両電極間の電圧に応じて階調(透過率や反射率)が変化する。第1実施形態の液晶56は、垂直配向型(VA(Vertical Alignment))に設定され、画素電極52と共通電極54との間の電圧がゼロである場合に階調が最低(黒色)となるノーマリーブラックモードで動作する。液晶素子50の両電極間の電圧の極性は順次に反転する(詳細は後述する)。   The liquid crystal element 50 is an electro-optical element including a pixel electrode 52, a common electrode (counter electrode) 54, and a liquid crystal 56 between both electrodes. The pixel electrode 52 is formed independently for each pixel circuit PIX on the surface of the element substrate (not shown), and the common electrode 54 is formed on the surface of the counter substrate (not shown) facing the element substrate. (See FIG. 1). The liquid crystal 56 between the pixel electrode 52 and the common electrode 54 changes in gradation (transmittance and reflectance) in accordance with the voltage between both electrodes. The liquid crystal 56 of the first embodiment is set to a vertical alignment type (VA (Vertical Alignment)), and the gradation becomes the lowest (black) when the voltage between the pixel electrode 52 and the common electrode 54 is zero. Operates in normally black mode. The polarity of the voltage between both electrodes of the liquid crystal element 50 is sequentially reversed (details will be described later).

第n列の各画素回路PIXの選択スイッチTSLは、画素電極52と第n列の信号線14との間に介在して両者の電気的な接続(導通/非導通)を制御する。第m行の各画素回路PIXの保持容量CSは、画素電極52と第m行の共通電位線22との間に介在する(すなわち、液晶素子50に対して並列に配置された)静電容量である。具体的には、保持容量CSは、画素電極52に接続された電極EA1と共通電位線22に接続された電極EA2と両電極間の誘電体とで構成される。保持容量CSは、画素電極52の電位(液晶素子50の印加電圧)を保持する要素として機能する。   The selection switch TSL of each pixel circuit PIX in the n-th column is interposed between the pixel electrode 52 and the signal line 14 in the n-th column and controls the electrical connection (conduction / non-conduction) between them. The holding capacitor CS of each pixel circuit PIX in the m-th row is interposed between the pixel electrode 52 and the common potential line 22 in the m-th row (that is, arranged in parallel with the liquid crystal element 50). It is. Specifically, the storage capacitor CS is composed of an electrode EA1 connected to the pixel electrode 52, an electrode EA2 connected to the common potential line 22, and a dielectric between both electrodes. The holding capacitor CS functions as an element that holds the potential of the pixel electrode 52 (voltage applied to the liquid crystal element 50).

第m行の各画素回路PIXの第1制御スイッチTC1は、画素電極52と第m行の反転用電位線24との間に介在して両者の電気的な接続を制御する。第m行の各画素回路PIXの制御用容量C1は、第1制御スイッチTC1のゲートと第m行の容量線26との間に介在する静電容量である。具体的には、制御用容量C1は、第1制御スイッチTC1のゲートに接続された電極EB1と容量線26に接続された電極EB2と両電極間の誘電体とで構成される。制御用容量C1は、第1制御スイッチTC1のゲートの電位を保持する要素として機能する。   The first control switch TC1 of each pixel circuit PIX in the m-th row is interposed between the pixel electrode 52 and the inversion potential line 24 in the m-th row and controls the electrical connection therebetween. The control capacitor C1 of each pixel circuit PIX in the m-th row is a capacitance that is interposed between the gate of the first control switch TC1 and the capacitor line 26 in the m-th row. Specifically, the control capacitor C1 includes an electrode EB1 connected to the gate of the first control switch TC1, an electrode EB2 connected to the capacitor line 26, and a dielectric between the electrodes. The control capacitor C1 functions as an element that holds the potential of the gate of the first control switch TC1.

第n列の各画素回路PIXの第2制御スイッチTC2は、第1制御スイッチTC1のゲートと第n列の制御線16との間に介在して両者の電気的な接続を制御する。第m行の各画素回路PIXにおける選択スイッチTSLおよび第2制御スイッチTC2の各々のゲートは第m行の走査線12に共通に接続される。選択スイッチTSLと第2制御スイッチTC2とは導電型が共通するから、選択スイッチTSLと第2制御スイッチTC2とは同じ状態(オン状態/オフ状態)に制御される。   The second control switch TC2 of each pixel circuit PIX in the n-th column is interposed between the gate of the first control switch TC1 and the control line 16 in the n-th column and controls the electrical connection between them. The gates of the selection switch TSL and the second control switch TC2 in each pixel circuit PIX in the m-th row are commonly connected to the scanning line 12 in the m-th row. Since the selection switch TSL and the second control switch TC2 have the same conductivity type, the selection switch TSL and the second control switch TC2 are controlled to be in the same state (on state / off state).

図1の制御回路44は、電気光学装置100の動作を規定する各種の信号を生成して駆動回路30および電位生成回路42に供給する。例えば、制御回路44は、液晶素子50の印加電圧の極性を反転させる単位となる期間(以下「単位期間」という)を規定する同期信号SVや、各単位期間における液晶素子50の印加電圧の極性(正極性/負極性)を指定する極性信号SPを、駆動回路30や電位生成回路42に出力する。また、制御回路44は、各画素回路PIX(各液晶素子50)の階調を指定する画像信号VIDを生成して駆動回路30(信号線駆動回路34)に供給する。   The control circuit 44 in FIG. 1 generates various signals that define the operation of the electro-optical device 100 and supplies the signals to the drive circuit 30 and the potential generation circuit 42. For example, the control circuit 44 includes a synchronization signal SV that defines a period (hereinafter referred to as “unit period”) that is a unit for reversing the polarity of the voltage applied to the liquid crystal element 50, and the polarity of the voltage applied to the liquid crystal element 50 in each unit period. A polarity signal SP designating (positive / negative) is output to the drive circuit 30 and the potential generation circuit 42. In addition, the control circuit 44 generates an image signal VID that specifies the gradation of each pixel circuit PIX (each liquid crystal element 50) and supplies the image signal VID to the drive circuit 30 (signal line drive circuit 34).

電位生成回路42は、共通電位LCCOMおよび反転用電位LCCOMXと、正側階調電位VDATA[+]および負側階調電位VDATA[-]と、オン電位VONおよびオフ電位VOFFと、保持電位VSLとを生成する。共通電位LCCOMは、M本の共通電位線22と対向基板上の共通電極54とに対して共通に供給される。反転用電位LCCOMXは、M本の反転用電位線24に共通に供給される。正側階調電位VDATA[+]および負側階調電位VDATA[-]とオン電位VONおよびオフ電位VOFFとは信号線駆動回路34に供給される。保持電位VSLは、M本の容量線26に共通に供給される所定の電位である。   The potential generation circuit 42 includes a common potential LCCOM and an inversion potential LCCOMX, a positive side gradation potential VDATA [+] and a negative side gradation potential VDATA [−], an on potential VON and an off potential VOFF, and a holding potential VSL. Is generated. The common potential LCCOM is supplied in common to the M common potential lines 22 and the common electrode 54 on the counter substrate. The inversion potential LCCOMX is supplied in common to the M inversion potential lines 24. The positive side gradation potential VDATA [+], the negative side gradation potential VDATA [−], the ON potential VON, and the OFF potential VOFF are supplied to the signal line driver circuit 34. The holding potential VSL is a predetermined potential that is commonly supplied to the M capacitor lines 26.

図3に示すように、共通電位LCCOMは、制御回路44が同期信号SVで規定する単位期間(例えばフィールド期間)F毎に、高位側電位VHおよび低位側電位VLの一方から他方に順次に変動する。高位側電位VHは低位側電位VLを上回る。電位生成回路42は、極性信号SPが正極性(図3の正号(+))を指示する単位期間Fでは共通電位LCCOMを低位側電位VLに設定し、極性信号SPが負極性(図3の負号(-))を指示する単位期間Fでは共通電位LCCOMを高位側電位VHに設定する。共通電位LCCOMが低位側電位VLに設定された場合の液晶素子50の印加電圧を正極性と定義し、共通電位LCCOMが高位側電位VHに設定された場合の液晶素子50の印加電圧を負極性と定義する。   As shown in FIG. 3, the common potential LCCOM sequentially changes from one to the other of the high potential VH and the low potential VL every unit period (for example, field period) F defined by the control signal 44 by the synchronization signal SV. To do. The higher potential VH exceeds the lower potential VL. In the unit period F in which the polarity signal SP indicates positive polarity (positive sign (+) in FIG. 3), the potential generation circuit 42 sets the common potential LCCOM to the lower potential VL and the polarity signal SP has negative polarity (FIG. 3). In the unit period F instructing the negative sign (-)), the common potential LCCOM is set to the high potential VH. The applied voltage of the liquid crystal element 50 when the common potential LCCOM is set to the lower potential VL is defined as positive polarity, and the applied voltage of the liquid crystal element 50 when the common potential LCCOM is set to the higher potential VH is negative. It is defined as

共通電位LCCOMと同様に、反転用電位LCCOMXは、高位側電位VHおよび低位側電位VLの一方から他方に単位期間F毎に順次に変動する。ただし、共通電位LCCOMと反転用電位LCCOMXとは電位の高低を反転させた関係にある。すなわち、共通電位LCCOMが高位側電位VHに設定される単位期間Fでは反転用電位LCCOMXが低位側電位VLに設定され、共通電位LCCOMが低位側電位VLに設定される単位期間Fでは反転用電位LCCOMXが高位側電位VHに設定される。図3には、共通電位LCCOMおよび反転用電位LCCOMXが高位側電位VHおよび低位側電位VLの一方から他方に変動している期間(以下「反転期間」という)Wが図示されている。   Similar to the common potential LCCOM, the inversion potential LCCOMX sequentially changes from one to the other of the high potential VH and the low potential VL every unit period F. However, the common potential LCCOM and the inversion potential LCCOMX have a relationship in which the potential level is inverted. That is, in the unit period F in which the common potential LCCOM is set to the high potential VH, the inversion potential LCCOMX is set to the low potential VL, and in the unit period F in which the common potential LCCOM is set to the low potential VL. LCCOMX is set to the higher potential VH. FIG. 3 illustrates a period W (hereinafter referred to as “inversion period”) in which the common potential LCCOM and the inversion potential LCCOMX vary from one of the high potential VH and the low potential VL to the other.

正側階調電位VDATA[+]および負側階調電位VDATA[-]は、液晶素子50の階調の制御のために画素電極52に供給される電位である。正側階調電位VDATA[+]は負側階調電位VDATA[-]を上回る。具体的には、正側階調電位VDATA[+]は高位側電位VHと同電位であり、負側階調電位VDATA[-]は低位側電位VLと同電位である。また、オン電位VONおよびオフ電位VOFFは、第1制御スイッチTC1の制御に利用される電位である。第1制御スイッチTC1は、ゲートに対するオン電位VONの供給でオン状態に遷移し、ゲートに対するオフ電位VOFFの供給でオフ状態に遷移する。   The positive side gradation potential VDATA [+] and the negative side gradation potential VDATA [−] are potentials supplied to the pixel electrode 52 for controlling the gradation of the liquid crystal element 50. The positive gradation potential VDATA [+] exceeds the negative gradation potential VDATA [-]. Specifically, the positive gradation potential VDATA [+] is the same potential as the high potential VH, and the negative gradation potential VDATA [−] is the same potential as the low potential VL. The on potential VON and the off potential VOFF are potentials used for controlling the first control switch TC1. The first control switch TC1 transitions to the on state when the on potential VON is supplied to the gate, and transitions to the off state when the off potential VOFF is supplied to the gate.

図1の駆動回路30は、複数の画素回路PIXの各々を駆動することで各液晶素子50の階調(透過率または反射率)を制御する。駆動回路30による各画素回路PIXの駆動にはサブフィールド駆動が採用される。すなわち、駆動回路30は、各単位期間Fを区分した複数のサブフィールドSF(SF1,SF2,SF3)の各々にて各画素回路PIXの液晶素子50に2種類の電圧(VA,VB)の何れかを印加する。図3に示すように、1個の単位期間Fは3個のサブフィールドSF(SF1,SF2,SF3)に区分される。単位期間F内の3個のサブフィールドSFの時間長は2進加重の関係(SF1:SF2:SF3=1:2:4)にある。もっとも、単位期間F内のサブフィールドSFの個数や時間長は任意に変更される。   The drive circuit 30 in FIG. 1 controls the gradation (transmittance or reflectivity) of each liquid crystal element 50 by driving each of the plurality of pixel circuits PIX. Subfield driving is employed for driving each pixel circuit PIX by the driving circuit 30. That is, the drive circuit 30 determines which of the two kinds of voltages (VA, VB) is applied to the liquid crystal element 50 of each pixel circuit PIX in each of the plurality of subfields SF (SF1, SF2, SF3) divided into the unit periods F. Apply. As shown in FIG. 3, one unit period F is divided into three subfields SF (SF1, SF2, SF3). The time lengths of the three subfields SF in the unit period F are in a binary weighted relationship (SF1: SF2: SF3 = 1: 2: 4). However, the number and time length of the subfield SF in the unit period F are arbitrarily changed.

図4は、液晶素子50の両電極間の電圧(絶対値)と液晶素子50の階調(透過率または反射率)との関係を示すグラフである。図4の電圧VAは、液晶素子50の階調を変化させる電圧であり、電圧VBは、電圧VAとは異なる電圧(本実施形態では電圧VAを下回る電圧)である。電圧VBは典型的には0Vに設定される。図3に示すように、高位側電位VH(正側階調電位VDATA[+])と低位側電位VL(負側階調電位VDATA[-])との電位差が電圧VAに相当する。図4に示すように、液晶素子50は、電圧VAの印加で階調GWに制御されるとともに電圧VBの印加で階調GBに制御される。液晶素子50がノーマリーブラックモードで動作する本形態では、階調GWは最高の階調(白色)に相当し、階調GBは最低の階調(黒色)に相当する。単位期間Fのうち液晶素子50に電圧VAを印加する時間と電圧VBを印加する時間との比率(サブフィールドSFの個数比)が、各画素回路PIXの指定階調に応じて可変に制御される。   FIG. 4 is a graph showing the relationship between the voltage (absolute value) between both electrodes of the liquid crystal element 50 and the gradation (transmittance or reflectance) of the liquid crystal element 50. The voltage VA in FIG. 4 is a voltage for changing the gradation of the liquid crystal element 50, and the voltage VB is a voltage different from the voltage VA (in this embodiment, a voltage lower than the voltage VA). The voltage VB is typically set to 0V. As shown in FIG. 3, the potential difference between the higher potential VH (positive gradation potential VDATA [+]) and the lower potential VL (negative gradation potential VDATA [-]) corresponds to the voltage VA. As shown in FIG. 4, the liquid crystal element 50 is controlled to the gradation GW by the application of the voltage VA and is controlled to the gradation GB by the application of the voltage VB. In this embodiment in which the liquid crystal element 50 operates in the normally black mode, the gradation GW corresponds to the highest gradation (white) and the gradation GB corresponds to the lowest gradation (black). In the unit period F, the ratio of the time during which the voltage VA is applied to the liquid crystal element 50 and the time during which the voltage VB is applied (number ratio of the subfield SF) is variably controlled according to the designated gradation of each pixel circuit PIX. The

図1に示すように、駆動回路30は、走査線駆動回路32と信号線駆動回路34とを含んで構成される。走査線駆動回路32は、M本の走査線12の各々を順次に選択する。具体的には、走査線駆動回路32は、各走査線12に走査信号Y[1]〜Y[M]を出力することで、各単位期間FのサブフィールドSF内にてM本の走査線12の各々を順次に選択する。第m行の走査線12に出力される走査信号Y[m]は、第m行の選択/非選択を指示する電圧信号である。すなわち、走査信号Y[m]は、図3に示すように、各サブフィールドSF内の第m番目の水平走査期間H[m]にて選択電位VSEL_ON(走査線12の選択を意味する電位)に設定され、他の期間にて非選択電位VSEL_OFF(走査線12の非選択を意味する電位)に設定される。   As shown in FIG. 1, the drive circuit 30 includes a scanning line drive circuit 32 and a signal line drive circuit 34. The scanning line driving circuit 32 sequentially selects each of the M scanning lines 12. Specifically, the scanning line driving circuit 32 outputs the scanning signals Y [1] to Y [M] to each scanning line 12, so that M scanning lines in the subfield SF of each unit period F are output. Each of 12 is selected sequentially. The scanning signal Y [m] output to the m-th row scanning line 12 is a voltage signal instructing selection / non-selection of the m-th row. That is, as shown in FIG. 3, the scanning signal Y [m] has a selection potential VSEL_ON (potential meaning selection of the scanning line 12) in the m-th horizontal scanning period H [m] in each subfield SF. And is set to the non-selection potential VSEL_OFF (potential meaning non-selection of the scanning line 12) in other periods.

図1の信号線駆動回路34は、走査線駆動回路32による各走査線12の選択に同期して、階調信号X[1]〜X[N]を各信号線14に出力するとともに制御信号Z[1]〜Z[N]を各制御線16に出力する。水平走査期間H[m]にて第n列の信号線14に供給される階調信号X[n]は、第m行の第n列の画素回路PIXにおける液晶素子50について階調GW(白表示)および階調GB(黒表示)の何れかを指定する電圧信号であり、正側階調電位VDATA[+]および負側階調電位VDATA[-]の何れかに設定される。水平走査期間H[m]にて第n列の制御線16に供給される制御信号Z[n]は、第m行の第n列の画素回路PIXにおける第1制御スイッチTC1の状態(オン状態/オフ状態)を指定する電圧信号であり、オン電圧VONおよびオフ電圧VOFFの何れかに設定される。   The signal line drive circuit 34 in FIG. 1 outputs gradation signals X [1] to X [N] to each signal line 14 in synchronization with the selection of each scan line 12 by the scan line drive circuit 32 and a control signal. Z [1] to Z [N] are output to each control line 16. The gradation signal X [n] supplied to the signal line 14 in the n-th column in the horizontal scanning period H [m] is the gradation GW (white) for the liquid crystal element 50 in the pixel circuit PIX in the m-th row and the n-th column. Display) and gradation GB (black display), and is set to either the positive gradation potential VDATA [+] or the negative gradation potential VDATA [-]. The control signal Z [n] supplied to the control line 16 in the n-th column in the horizontal scanning period H [m] is the state (ON state) of the first control switch TC1 in the pixel circuit PIX in the n-th column of the m-th row. / Off state) and is set to either the on voltage VON or the off voltage VOFF.

図5は、信号線駆動回路34のブロック図である。図5に示すように、信号線駆動回路34は、分配回路62と出力回路64とを含んで構成される。分配回路62は、第m行のN個の画素回路PIXに対応する階調データD[1]〜D[N]を画像信号VIDから生成して各水平走査期間H[m]にて並列に出力する回路である。水平走査期間H[m]にて分配回路62から出力される階調データD[n]は、第m行の第n列に位置する画素回路PIXの液晶素子50について階調GW(白表示の電圧VA)または階調GB(黒表示の電圧VB)の何れかを指定するデータである。   FIG. 5 is a block diagram of the signal line driving circuit 34. As shown in FIG. 5, the signal line drive circuit 34 includes a distribution circuit 62 and an output circuit 64. The distribution circuit 62 generates gradation data D [1] to D [N] corresponding to the N pixel circuits PIX in the m-th row from the image signal VID, and in parallel in each horizontal scanning period H [m]. It is a circuit to output. The gradation data D [n] output from the distribution circuit 62 in the horizontal scanning period H [m] is the gradation GW (white display) for the liquid crystal element 50 of the pixel circuit PIX located in the nth column of the mth row. This is data specifying either voltage VA) or gradation GB (black display voltage VB).

図5に示すように、分配回路62は、選択回路621と第1ラッチ回路623と第2ラッチ回路625とを含んで構成される。選択回路621は、各水平走査期間H[m]内にN系統の選択信号SEL[1]〜SEL[N]を順次にアクティブに設定する。例えば、開始パルスを順次に転送するN段のシフトレジスタが選択回路621として採用される。第1ラッチ回路623は、選択信号SEL[1]〜SEL[N]の各々(SEL[n])がアクティブに設定された時点で制御回路44から供給されている画像信号VIDを階調データD[n]として出力および保持する。すなわち、階調データD[1]〜D[N]が点順次で第1ラッチ回路623から並列に出力される。第2ラッチ回路625は、第1ラッチ回路623が出力する階調データD[1]〜D[N]を水平走査期間H[m]毎に一斉に出力(線順次出力)および保持する。   As shown in FIG. 5, the distribution circuit 62 includes a selection circuit 621, a first latch circuit 623, and a second latch circuit 625. The selection circuit 621 sequentially sets the N selection signals SEL [1] to SEL [N] to active in each horizontal scanning period H [m]. For example, an N-stage shift register that sequentially transfers start pulses is employed as the selection circuit 621. The first latch circuit 623 receives the image signal VID supplied from the control circuit 44 at the time when each of the selection signals SEL [1] to SEL [N] (SEL [n]) is set to active, and the gradation data D Output and hold as [n]. That is, the gradation data D [1] to D [N] are output in parallel from the first latch circuit 623 in dot order. The second latch circuit 625 simultaneously outputs (line-sequential output) and holds the gradation data D [1] to D [N] output from the first latch circuit 623 every horizontal scanning period H [m].

出力回路64は、階調信号X[1]〜X[N]と制御信号Z[1]〜Z[N]とを階調データD[1]〜D[N]に応じて生成して出力する。図5に示すように、出力回路64は、画素回路PIXの列数に相当するN個の単位回路U[1]〜U[N]を含んで構成される。第n段目の単位回路U[n]は、分配回路62が出力する階調データD[n]に応じて階調信号X[n]および制御信号Z[n]を生成して出力する。図5に示すように、単位回路U[n]は、階調信号X[n]を生成する電位選択回路641と制御信号Z[n]を生成する電位選択回路643とを含んで構成される。図6は、電位選択回路641および電位選択回路643の動作(階調信号X[n]および制御信号Z[n]の電位の設定)を説明するための図表である。   The output circuit 64 generates gradation signals X [1] to X [N] and control signals Z [1] to Z [N] according to the gradation data D [1] to D [N] and outputs them. To do. As shown in FIG. 5, the output circuit 64 includes N unit circuits U [1] to U [N] corresponding to the number of columns of the pixel circuit PIX. The n-th unit circuit U [n] generates and outputs a gradation signal X [n] and a control signal Z [n] according to the gradation data D [n] output from the distribution circuit 62. As shown in FIG. 5, the unit circuit U [n] includes a potential selection circuit 641 that generates a gradation signal X [n] and a potential selection circuit 643 that generates a control signal Z [n]. . FIG. 6 is a chart for explaining operations of the potential selection circuit 641 and the potential selection circuit 643 (setting of the potentials of the gradation signal X [n] and the control signal Z [n]).

図5の電位選択回路641は、電位生成回路42が生成した正側階調電位VDATA[+]および負側階調電位VDATA[-]の何れかを階調データD[n]および極性信号SPに応じて選択して階調信号X[n]として信号線14に出力する。具体的には、電位選択回路641は、階調データD[n]で指示される階調(GW,GB)に対応した電圧(VA,VB)が液晶素子50に印加されるように、階調信号X[n]の電位を正側階調電位VDATA[+]および負側階調電位VDATA[-]の何れかに設定する。   The potential selection circuit 641 in FIG. 5 uses either the positive gradation potential VDATA [+] or the negative gradation potential VDATA [−] generated by the potential generation circuit 42 as the gradation data D [n] and the polarity signal SP. Is selected according to the output signal and output to the signal line 14 as the gradation signal X [n]. Specifically, the potential selection circuit 641 adjusts the voltage (VA, VB) corresponding to the gradation (GW, GB) indicated by the gradation data D [n] so as to be applied to the liquid crystal element 50. The potential of the adjustment signal X [n] is set to either the positive side gradation potential VDATA [+] or the negative side gradation potential VDATA [-].

例えば、極性信号SPが正極性を指示する単位期間F(共通電位LCCOMが低位側電位VLに設定される期間)では、電位選択回路641は、図6に示すように、階調データD[n]が階調GWを指示する場合には正側階調電位VDATA[+]を選択し、階調データD[n]が階調GBを指示する場合には負側階調電位VDATA[-]を選択する。他方、極性信号SPが負極性を指示する単位期間F(共通電位LCCOMが高位側電位VHに設定される期間)では、電位選択回路641は、階調データD[n]が階調GWを指示する場合には負側階調電位VDATA[-]を選択し、階調データD[n]が階調GBを指示する場合には正側階調電位VDATA[+]を選択する。   For example, in the unit period F in which the polarity signal SP indicates positive polarity (the period in which the common potential LCCOM is set to the lower potential VL), the potential selection circuit 641 performs the gradation data D [n as shown in FIG. ] Indicates the gradation GW, the positive side gradation potential VDATA [+] is selected, and when the gradation data D [n] indicates the gradation GB, the negative side gradation potential VDATA [-] is selected. Select. On the other hand, in the unit period F in which the polarity signal SP indicates the negative polarity (period in which the common potential LCCOM is set to the higher potential VH), the potential selection circuit 641 indicates that the gradation data D [n] indicates the gradation GW. In this case, the negative gradation potential VDATA [-] is selected, and when the gradation data D [n] indicates the gradation GB, the positive gradation potential VDATA [+] is selected.

図5の電位選択回路643は、電位生成回路42が生成したオン電位VONおよびオフ電位VOFFの何れかを階調データD[n]に応じて選択して制御信号Z[n]として制御線16に出力する。具体的には、電位選択回路643は、図6に示すように、階調データD[n]が階調GW(電圧VA)を指示する場合にはオン電位VONを選択し、階調データD[n]が階調GB(電圧VB)を指示する場合にはオフ電位VOFFを選択する。   The potential selection circuit 643 in FIG. 5 selects either the ON potential VON or the OFF potential VOFF generated by the potential generation circuit 42 according to the gradation data D [n], and uses the control line 16 as the control signal Z [n]. Output to. Specifically, as shown in FIG. 6, the potential selection circuit 643 selects the ON potential VON when the gradation data D [n] indicates the gradation GW (voltage VA), and the gradation data D When [n] indicates the gradation GB (voltage VB), the off potential VOFF is selected.

次に、図7から図12を参照して電気光学装置100の動作を説明する。共通電位LCCOMが低位側電位VLに設定される単位期間F(図7〜図9)と高位側電位VHに設定される単位期間F(図10〜図12)との各々について、階調データD[n]が階調GBを指示する場合(図8,図11)と階調GWを指示する場合(図9,図12)との動作を以下では説明する。なお、以下では第m行の第n列の画素回路PIXに着目して動作を説明する。素子部10内の各画素回路PIXについて同様の動作が実行される。   Next, the operation of the electro-optical device 100 will be described with reference to FIGS. The gradation data D for each of the unit period F (FIGS. 7 to 9) in which the common potential LCCOM is set to the lower potential VL and the unit period F (FIGS. 10 to 12) set to the higher potential VH. The operation when [n] indicates the gradation GB (FIGS. 8 and 11) and when the gradation GW is specified (FIGS. 9 and 12) will be described below. In the following, the operation will be described focusing on the pixel circuit PIX in the m-th row and the n-th column. A similar operation is performed for each pixel circuit PIX in the element unit 10.

また、以下では、図7や図10に示すように、非選択電位VSEL_OFFと低位側電位VLと負側階調電位VDATA[-]とオフ電位VOFFとを基準(0V)として、高位側電位VHと正側階調電位VDATA[+]とを5Vに設定し、オン電位VONを7Vに設定し、選択電位VSEL_ONを9Vに設定した場合を例示する。画素回路PIXの各スイッチ(TSL,TC1,TC2)の閾値電圧は2V以下と仮定する。なお、階調GB(黒表示)に対応する電圧VBは0Vであるが、極性信号SPが正極性を指示する単位期間Fで液晶素子50に印加される電圧+VBと、極性信号SPが負極性を指示する単位期間Fで液晶素子50に印加される電圧−VBとを便宜的に区別する。   In the following, as shown in FIG. 7 and FIG. 10, the non-selection potential VSEL_OFF, the low potential VL, the negative gradation potential VDATA [-], and the off potential VOFF are set as a reference (0 V) as the reference (0 V). The positive gradation potential VDATA [+] is set to 5V, the ON potential VON is set to 7V, and the selection potential VSEL_ON is set to 9V. It is assumed that the threshold voltage of each switch (TSL, TC1, TC2) of the pixel circuit PIX is 2V or less. The voltage VB corresponding to the gradation GB (black display) is 0 V, but the voltage + VB applied to the liquid crystal element 50 in the unit period F in which the polarity signal SP indicates positive polarity and the polarity signal SP is negative. For the sake of convenience, the voltage -VB applied to the liquid crystal element 50 in the unit period F instructing the above is distinguished.

[A]極性信号SPが正極性を指示する単位期間F(図7〜図9)
[A1]階調データD[n]が階調GB(黒表示)を指示する場合(図8)
極性信号SPが正極性を指示する単位期間Fでは、図7に示すように、共通電位LCCOMが低位側電位VLに設定されるとともに反転用電位LCCOMXが高位側電位VHに設定される。また、階調データD[n]が階調GBを指示するから、水平走査期間H[m]では、図8の部分(A)に示すように、信号線14の階調信号X[n]が共通電位LCCOM(低位側電位VL)と同電位の負側階調電位VDATA[-]に設定され、制御線16の制御信号Z[n]がオフ電位VOFFに設定される。
[A] Unit period F in which polarity signal SP indicates positive polarity (FIGS. 7 to 9)
[A1] When gradation data D [n] indicates gradation GB (black display) (FIG. 8)
In the unit period F in which the polarity signal SP indicates positive polarity, as shown in FIG. 7, the common potential LCCOM is set to the low potential VL and the inversion potential LCCOMX is set to the high potential VH. Further, since the gradation data D [n] indicates the gradation GB, the gradation signal X [n] of the signal line 14 is shown in the horizontal scanning period H [m], as shown in part (A) of FIG. Is set to the negative gradation potential VDATA [−] which is the same potential as the common potential LCCOM (low potential VL), and the control signal Z [n] of the control line 16 is set to the OFF potential VOFF.

図7に示すように、水平走査期間H[m]では、走査信号Y[m]が選択電位VSEL_ONに設定されることで選択スイッチTSLおよび第2制御スイッチTC2がオン状態に遷移する。したがって、画素電極52の電位VPは、図7の部分(i)および図8の部分(A)に示すように、選択スイッチTSLを介して信号線14から供給される負側階調電位VDATA[-](低位側電位VL)に設定される。共通電極54の共通電位LCCOMは低位側電位VLに維持されるから、図8の部分(A)に示すように、液晶素子50の両電極間には電圧+VB(0V)が印加される。したがって、液晶素子50は階調GB(黒表示)に制御される。他方、第1制御スイッチTC1のゲートには第2制御スイッチTC2を介して制御線16からオフ電位VOFFが供給される。したがって、第1制御スイッチTC1はオフ状態に制御される。すなわち、画素電極52と反転用電位線24とは電気的に絶縁される。   As shown in FIG. 7, in the horizontal scanning period H [m], the scanning signal Y [m] is set to the selection potential VSEL_ON, so that the selection switch TSL and the second control switch TC2 are turned on. Therefore, the potential VP of the pixel electrode 52 is, as shown in the part (i) of FIG. 7 and the part (A) of FIG. 8, the negative gradation potential VDATA [supplied from the signal line 14 via the selection switch TSL. -] (Low potential VL). Since the common potential LCCOM of the common electrode 54 is maintained at the lower potential VL, a voltage + VB (0 V) is applied between both electrodes of the liquid crystal element 50 as shown in part (A) of FIG. Therefore, the liquid crystal element 50 is controlled to the gradation GB (black display). On the other hand, the OFF potential VOFF is supplied from the control line 16 to the gate of the first control switch TC1 via the second control switch TC2. Therefore, the first control switch TC1 is controlled to the off state. That is, the pixel electrode 52 and the inversion potential line 24 are electrically insulated.

画素電極52の電位VPは保持容量CSで保持され、制御線16から供給されたオフ電位VOFFは制御用容量C1で保持される。したがって、図8の部分(B)に示すように、水平走査期間H[m]が経過して走査信号Y[m]が非選択電位VSEL_OFFに変化した以後も、液晶素子50の印加電圧は電圧+VBに維持され、第1制御スイッチTC1はオフ状態に維持される。以上の動作が単位期間F内の各サブフィールドSFにて順次に実行される。   The potential VP of the pixel electrode 52 is held by the holding capacitor CS, and the off-potential VOFF supplied from the control line 16 is held by the control capacitor C1. Therefore, as shown in part (B) of FIG. 8, even after the horizontal scanning period H [m] has elapsed and the scanning signal Y [m] has changed to the non-selection potential VSEL_OFF, the applied voltage of the liquid crystal element 50 remains the voltage. The voltage is maintained at + VB, and the first control switch TC1 is maintained in the off state. The above operation is sequentially executed in each subfield SF in the unit period F.

図7に示すように、単位期間Fの経過後の反転期間Wでは、共通電位LCCOMが低位側電位VLから高位側電位VHに変化するとともに反転用電位LCCOMXが高位側電位VHから低位側電位VLに変化する。他方、水平走査期間H[m]の経過後には選択スイッチTSLおよび第1制御スイッチTC1がオフ状態に制御されることで画素電極52は電気的なフローティング状態に維持される。画素電極52は保持容量CSを介して共通電位線22に容量結合するから、画素電極52の電位VPは、反転期間W内の保持容量CSの電極EA2の電位(共通電位LCCOM)に連動して変化する。画素電極52の電位VPの変化量は、共通電位LCCOMの変化量と略同等である。すなわち、図7の部分(i)や図8の部分(C)に示すように、画素電極52の電位VPは、反転期間Wの開始前の低位側電位VLから高位側電位VHに変化して維持される。したがって、液晶素子50の印加電圧は、共通電極54の共通電位LCCOMの変化後の高位側電位VHと画素電極52の変化後の高位側電位VHとに対応する負極性の電圧−VB(0V)に設定される。以上のように、液晶素子50の階調は、反転期間W内での共通電位LCCOMの変化の前後にわたって階調GB(黒表示)に維持される。他方、第1制御スイッチTC1はオフ状態を維持するから、反転期間W内での反転用電位LCCOMXの変化は画素電極52の電位VPに影響しない。   As shown in FIG. 7, in the inversion period W after the lapse of the unit period F, the common potential LCCOM changes from the low potential VL to the high potential VH and the inversion potential LCCOMX changes from the high potential VH to the low potential VL. To change. On the other hand, after the elapse of the horizontal scanning period H [m], the selection switch TSL and the first control switch TC1 are controlled to be turned off, so that the pixel electrode 52 is maintained in an electrically floating state. Since the pixel electrode 52 is capacitively coupled to the common potential line 22 via the storage capacitor CS, the potential VP of the pixel electrode 52 is interlocked with the potential of the electrode EA2 of the storage capacitor CS within the inversion period W (common potential LCCOM). Change. The amount of change in the potential VP of the pixel electrode 52 is substantially the same as the amount of change in the common potential LCCOM. That is, as shown in part (i) of FIG. 7 and part (C) of FIG. 8, the potential VP of the pixel electrode 52 changes from the lower potential VL before the start of the inversion period W to the higher potential VH. Maintained. Therefore, the voltage applied to the liquid crystal element 50 is a negative voltage −VB (0 V) corresponding to the high potential VH after the change of the common potential LCCOM of the common electrode 54 and the high potential VH after the change of the pixel electrode 52. Set to As described above, the gradation of the liquid crystal element 50 is maintained at the gradation GB (black display) before and after the change of the common potential LCCOM within the inversion period W. On the other hand, since the first control switch TC1 maintains the OFF state, the change in the inversion potential LCCOMX within the inversion period W does not affect the potential VP of the pixel electrode 52.

[A2]階調データD[n]が階調GW(白表示)を指示する場合(図9)
極性信号SPが正極性を指示する単位期間F(LCCOM=VL)にて階調データD[n]が階調GWを指示する場合、水平走査期間H[m]では、図9の部分(A)に示すように、階調信号X[n]が正側階調電位VDATA[+](すなわち、共通電位LCCOMとは相違する電位)に設定され、制御信号Z[n]がオン電位VONに設定される。
[A2] When gradation data D [n] indicates gradation GW (white display) (FIG. 9)
In the case where the gradation data D [n] indicates the gradation GW in the unit period F (LCCOM = VL) in which the polarity signal SP indicates positive polarity, in the horizontal scanning period H [m], the portion (A ), The gradation signal X [n] is set to the positive gradation potential VDATA [+] (that is, a potential different from the common potential LCCOM), and the control signal Z [n] is set to the ON potential VON. Is set.

したがって、走査信号Y[m]が選択電位VSEL_ONに設定される水平走査期間H[m]では、図9の部分(A)に示すように、正側階調電位VDATA[+]が信号線14から選択スイッチTSLを介して画素電極52に供給される。また、第1制御スイッチTC1のゲートには第2制御スイッチTC2を介して制御線16からオン電位VONが供給される。反転用電位LCCOMX(第1制御スイッチTC1のソースの電位)は高位側電位VH(5V)に設定されるが、第1制御スイッチTC1のゲート−ソース間の電圧が閾値電圧(2V以下)を上回るようにオン電位VON(7V)が設定されるから、第1制御スイッチTC1はオン状態に遷移して画素電極52と反転用電位線24とが電気的に接続される。すなわち、正側階調電位VDATA[+]の信号線14と反転用電位LCCOMX(高位側電位VH)の反転用電位線24との双方が画素電極52に接続される。正側階調電位VDATA[+]と高位側電位VHとは同電位であるから、画素電極52の電位VPは、図7の部分(ii)や図9の部分(A)に示すように高位側電位VH(正側階調電位VDATA[+])に設定される。共通電極54の共通電位LCCOMは低位側電位VLに維持されるから、図9の部分(A)のように液晶素子50の両電極間には正極性の電圧+VA(5V)が印加される。したがって、液晶素子50は階調GW(白表示)に制御される。   Therefore, in the horizontal scanning period H [m] in which the scanning signal Y [m] is set to the selection potential VSEL_ON, as shown in part (A) of FIG. To the pixel electrode 52 via the selection switch TSL. The ON potential VON is supplied from the control line 16 to the gate of the first control switch TC1 via the second control switch TC2. The inversion potential LCCOMX (source potential of the first control switch TC1) is set to the higher potential VH (5 V), but the voltage between the gate and source of the first control switch TC1 exceeds the threshold voltage (2 V or less). Thus, the ON potential VON (7V) is set, so that the first control switch TC1 transitions to the ON state, and the pixel electrode 52 and the inversion potential line 24 are electrically connected. That is, both the signal line 14 of the positive gradation potential VDATA [+] and the inversion potential line 24 of the inversion potential LCCOMX (higher side potential VH) are connected to the pixel electrode 52. Since the positive side gradation potential VDATA [+] and the higher potential VH are the same potential, the potential VP of the pixel electrode 52 is higher as shown in part (ii) of FIG. 7 and part (A) of FIG. It is set to the side potential VH (positive side gradation potential VDATA [+]). Since the common potential LCCOM of the common electrode 54 is maintained at the lower potential VL, a positive voltage + VA (5 V) is applied between both electrodes of the liquid crystal element 50 as shown in part (A) of FIG. Accordingly, the liquid crystal element 50 is controlled to the gradation GW (white display).

画素電極52の電位VPは保持容量CSで保持され、制御信号Z[n]のオン電位VONは制御用容量C1で保持される。したがって、水平走査期間H[m]の経過後にも、図9の部分(B)に示すように、液晶素子50の両電極間には引続き電圧+VAが印加され、第1制御スイッチTC1がオン状態に維持されることで反転用電位線24から画素電極52に継続的に反転用電位LCCOMX(高位側電位VH)が供給される。以上の動作が単位期間F内のサブフィールドSFにて順次に実行される。   The potential VP of the pixel electrode 52 is held by the holding capacitor CS, and the ON potential VON of the control signal Z [n] is held by the control capacitor C1. Therefore, even after the horizontal scanning period H [m] has elapsed, as shown in part (B) of FIG. 9, the voltage + VA is continuously applied between both electrodes of the liquid crystal element 50, and the first control switch TC1 is turned on. Thus, the inversion potential LCCOMX (high potential VH) is continuously supplied from the inversion potential line 24 to the pixel electrode 52. The above operations are sequentially executed in the subfield SF in the unit period F.

図7に示すように、単位期間Fの経過後の反転期間Wでは、共通電位LCCOMが低位側電位VLから高位側電位VHに変化するとともに反転用電位LCCOMXが高位側電位VHから低位側電位VLに変化する。他方、画素電極52に対する反転用電位LCCOMXの供給(第1制御スイッチTC1のオン状態)は反転期間W内でも維持される。すなわち、階調GBが指示された場合の反転期間Wでは画素電極52が電気的なフローティング状態に設定されるのに対し、階調GWが指示された場合には画素電極52は反転用電位LCCOMが供給された状態に設定される。したがって、画素電極52と共通電位線22(保持容量CSの電極EA2)との容量結合に起因した電位VPの変動は発生せず、画素電極52の電位VPは、図7の部分(ii)や図9の部分(C)に示すように、反転期間W内にて反転用電位LCCOMXとともに高位側電位VHから低位側電位VLに変化する。したがって、液晶素子50の印加電圧は、共通電極54の共通電位LCCOMの変化後の高位側電位VHと画素電極52の電位VPの変化後の低位側電位VLとの電位差に相当する負極性の電圧−VAに設定される。つまり、液晶素子50が階調GW(白表示)に維持されたまま、反転期間W内での共通電位LCCOMの変化の前後で液晶素子50の印加電圧の極性が反転する。   As shown in FIG. 7, in the inversion period W after the lapse of the unit period F, the common potential LCCOM changes from the low potential VL to the high potential VH and the inversion potential LCCOMX changes from the high potential VH to the low potential VL. To change. On the other hand, the supply of the inversion potential LCCOMX to the pixel electrode 52 (the ON state of the first control switch TC1) is maintained even during the inversion period W. That is, in the inversion period W when the gradation GB is instructed, the pixel electrode 52 is set in an electrically floating state, whereas when the gradation GW is instructed, the pixel electrode 52 is in an inversion potential LCCOM. Is set to the supplied state. Therefore, the potential VP does not fluctuate due to the capacitive coupling between the pixel electrode 52 and the common potential line 22 (the electrode EA2 of the storage capacitor CS), and the potential VP of the pixel electrode 52 is equal to the portion (ii) in FIG. As shown in part (C) of FIG. 9, within the inversion period W, the inversion potential LCCOMX changes from the higher potential VH to the lower potential VL. Therefore, the voltage applied to the liquid crystal element 50 is a negative voltage corresponding to the potential difference between the high potential VH after the change of the common potential LCCOM of the common electrode 54 and the low potential VL after the change of the potential VP of the pixel electrode 52. Set to -VA. That is, the polarity of the voltage applied to the liquid crystal element 50 is reversed before and after the change of the common potential LCCOM within the inversion period W while the liquid crystal element 50 is maintained at the gradation GW (white display).

[B]極性信号SPが負極性を指示する単位期間F(図10〜図12)
[B1]階調データD[n]が階調GB(黒表示)を指定する場合(図11)
極性信号SPが負極性を指示する単位期間Fでは、図10に示すように、共通電位LCCOMが高位側電位VHに設定されるとともに反転用電位LCCOMXが低位側電位VLに設定される。また、階調データD[n]が階調GBを指示する場合、水平走査期間H[m]では、図11の部分(A)に示すように、階調信号X[n]が正側階調電位VDATA[+]に設定されるとともに制御信号Z[n]がオフ電位VOFFに設定される。
[B] Unit period F in which polarity signal SP indicates negative polarity (FIGS. 10 to 12)
[B1] When gradation data D [n] designates gradation GB (black display) (FIG. 11)
In the unit period F in which the polarity signal SP indicates negative polarity, as shown in FIG. 10, the common potential LCCOM is set to the high potential VH and the inversion potential LCCOMX is set to the low potential VL. Further, when the gradation data D [n] indicates the gradation GB, as shown in the part (A) of FIG. 11, in the horizontal scanning period H [m], the gradation signal X [n] The adjustment potential VDATA [+] is set and the control signal Z [n] is set to the OFF potential VOFF.

水平走査期間H[m]にて走査信号Y[m]が選択電位VSEL_ONに設定されると、図10の部分(i)に示すように、画素電極52の電位VPが信号線14の正側階調電位VDATA[+]に変化する。したがって、図11の部分(A)に示すように、液晶素子50の印加電圧は、共通電極54の共通電位LCCOM(高位側電位VH)と画素電極52の正側階調電位VDATA[+]とに対応する負極性の電圧−VB(0V)に設定される。すなわち、液晶素子50は階調GB(黒表示)に制御される。他方、第1制御スイッチTC1はオフ電位VOFFの供給でオフ状態に制御されるから、画素電極52と反転用電位線24とは電気的に絶縁される。図11の部分(B)に示すように、水平走査期間H[m]の経過後も以上の状態が保持される。   When the scanning signal Y [m] is set to the selection potential VSEL_ON in the horizontal scanning period H [m], the potential VP of the pixel electrode 52 is set to the positive side of the signal line 14 as shown in part (i) of FIG. The gradation potential changes to VDATA [+]. Therefore, as shown in part (A) of FIG. 11, the voltage applied to the liquid crystal element 50 includes the common potential LCCOM (high potential VH) of the common electrode 54 and the positive gradation potential VDATA [+] of the pixel electrode 52. Is set to a negative polarity voltage -VB (0 V). That is, the liquid crystal element 50 is controlled to the gradation GB (black display). On the other hand, since the first control switch TC1 is controlled to be turned off by supplying the off potential VOFF, the pixel electrode 52 and the inversion potential line 24 are electrically insulated. As shown in part (B) of FIG. 11, the above state is maintained even after the horizontal scanning period H [m] has elapsed.

図10に示すように、単位期間Fの経過後の反転期間Wでは、共通電位LCCOMが高位側電位VHから低位側電位VLに変化するとともに反転用電位LCCOMXが低位側電位VLから高位側電位VHに変化する。画素電極52は電気的なフローティング状態にあるから、画素電極52の電位VPは、図10の部分(i)に示すように、共通電位線22の共通電位LCCOMに連動して高位側電位VHから低位側電位VLに変化して維持される。したがって、液晶素子50の印加電圧は、図11の部分(C)に示すように、共通電極54の低位側電位VLと画素電極52の低位側電位VLとに対応する正極性の電圧+VB(0V)に設定される。すなわち、液晶素子50の階調は、反転期間W内の共通電位LCCOMの変化の前後にわたって階調GB(黒表示)に維持される。第1制御スイッチTC1はオフ状態を維持するから、反転期間W内での反転用電位LCCOMXの変化は画素電極52の電位VPに影響しない。   As shown in FIG. 10, in the inversion period W after the lapse of the unit period F, the common potential LCCOM changes from the high potential VH to the low potential VL and the inversion potential LCCOMX changes from the low potential VL to the high potential VH. To change. Since the pixel electrode 52 is in an electrically floating state, the potential VP of the pixel electrode 52 is changed from the higher potential VH in conjunction with the common potential LCCOM of the common potential line 22 as shown in part (i) of FIG. The low potential VL is changed and maintained. Therefore, the voltage applied to the liquid crystal element 50 is a positive voltage + VB (0 V) corresponding to the lower potential VL of the common electrode 54 and the lower potential VL of the pixel electrode 52, as shown in part (C) of FIG. ). That is, the gradation of the liquid crystal element 50 is maintained at the gradation GB (black display) before and after the change of the common potential LCCOM within the inversion period W. Since the first control switch TC1 is kept off, the change in the inversion potential LCCOMX within the inversion period W does not affect the potential VP of the pixel electrode 52.

[B2]階調データD[n]が階調GB(黒表示)を指示する場合(図12)
極性信号SPが負極性を指示する単位期間F(LCCOM=VH)にて階調データD[n]が階調GWを指示する場合、水平走査期間H[m]では、図12の部分(A)に示すように、階調信号X[n]が負側階調電位VDATA[-]に設定される。また、制御信号Z[n]がオン電位VONに設定されることで第1制御スイッチTC1がオン状態に制御される。すなわち、水平走査期間H[m]では、負側階調電位VDATA[-]が信号線14から画素電極52に供給されるとともに、反転用電位LCCOMXの低位側電位VLが反転用電位線24から第1制御スイッチTC1を介して画素電極52に供給される。したがって、共通電極54の高位側電位VHと画素電極52の低位側電位VL(負側階調電位VDATA[-])との電位差に相当する負極性の電圧−VAが液晶素子50の両電極間に印加され、液晶素子50は階調GW(白表示)に制御される。図12の部分(B)に示すように、水平走査期間H[m]の経過後も以上の状態が維持される。
[B2] When gradation data D [n] indicates gradation GB (black display) (FIG. 12)
When the gradation data D [n] indicates the gradation GW in the unit period F (LCCOM = VH) in which the polarity signal SP indicates negative polarity, in the horizontal scanning period H [m], the portion (A ), The gradation signal X [n] is set to the negative gradation potential VDATA [−]. Further, the control signal Z [n] is set to the ON potential VON, whereby the first control switch TC1 is controlled to be in the ON state. That is, in the horizontal scanning period H [m], the negative gradation potential VDATA [−] is supplied from the signal line 14 to the pixel electrode 52, and the lower potential VL of the inversion potential LCCOMX is supplied from the inversion potential line 24. The pixel electrode 52 is supplied via the first control switch TC1. Therefore, a negative voltage −VA corresponding to the potential difference between the higher potential VH of the common electrode 54 and the lower potential VL (negative gradation potential VDATA [−]) of the pixel electrode 52 is between the electrodes of the liquid crystal element 50. The liquid crystal element 50 is controlled to a gradation GW (white display). As shown in part (B) of FIG. 12, the above state is maintained even after the horizontal scanning period H [m] has elapsed.

図10に示すように、反転期間Wでは、共通電位LCCOMが高位側電位VHから低位側電位VLに変化するとともに反転用電位LCCOMXが低位側電位VLから高位側電位VHに変化する。画素電極52と反転用電位線24との接続は反転期間Wでも維持されるから、図10の部分(ii)および図12の部分(C)に示すように、画素電極52の電位VPは、反転用電位LCCOMXとともに低位側電位VLから高位側電位VHに変化する。すなわち、液晶素子50の印加電圧は、共通電位LCCOMの変化後の低位側電位VLと画素電極52の変化後の高位側電位VHとの電位差に相当する正極性の電圧+VAに設定される。つまり、液晶素子50が階調GW(白表示)に維持されたまま、反転期間W内での共通電位LCCOMの変化の前後で液晶素子50の印加電圧の極性が反転する。   As shown in FIG. 10, in the inversion period W, the common potential LCCOM changes from the high potential VH to the low potential VL and the inversion potential LCCOMX changes from the low potential VL to the high potential VH. Since the connection between the pixel electrode 52 and the inversion potential line 24 is maintained even during the inversion period W, as shown in the part (ii) of FIG. 10 and the part (C) of FIG. Along with the inversion potential LCCOMX, the low potential VL changes to the high potential VH. That is, the applied voltage of the liquid crystal element 50 is set to a positive voltage + VA corresponding to the potential difference between the lower potential VL after the change of the common potential LCCOM and the higher potential VH after the change of the pixel electrode 52. That is, the polarity of the voltage applied to the liquid crystal element 50 is reversed before and after the change of the common potential LCCOM within the inversion period W while the liquid crystal element 50 is maintained at the gradation GW (white display).

以上に説明したように、第1実施形態においては、共通電位LCCOMが高位側電位VHおよび低位側電位VLの一方から他方に順次に変動するから、共通電位LCCOMを固定した構成と比較して階調信号X[n]の振幅(正側階調電位VDATA[+]と負側階調電位VDATA[-]との電位差)を低減することが可能である。また、階調信号X[n]の振幅が低減されるから、選択スイッチTSLの制御に必要となる選択電位VSEL_ONも低減される。したがって、走査線駆動回路32や信号線駆動回路34に必要となる耐圧性能が低減されるとともに消費電力が削減されるという利点がある。   As described above, in the first embodiment, since the common potential LCCOM sequentially changes from one of the high potential VH and the low potential VL to the other, it is compared with the configuration in which the common potential LCCOM is fixed. It is possible to reduce the amplitude of the tone signal X [n] (potential difference between the positive gradation potential VDATA [+] and the negative gradation potential VDATA [−]). Further, since the amplitude of the gradation signal X [n] is reduced, the selection potential VSEL_ON necessary for controlling the selection switch TSL is also reduced. Therefore, there is an advantage that the withstand voltage performance required for the scanning line driving circuit 32 and the signal line driving circuit 34 is reduced and the power consumption is reduced.

また、第1実施形態においては、階調GWに対応する電圧VA(±VA)を液晶素子50に印加した場合に、共通電位LCCOMが変動する反転期間W内では反転用電位線24から画素電極52に反転用電位LCCOMXが供給される。すなわち、反転期間W内での共通電位LCCOMの変動は画素電極52の電位VPに影響しない。したがって、液晶素子50を階調GWに維持したまま、共通電位LCCOMの変化の前後で液晶素子50の電圧VAの極性を反転させることが可能である。以上の構成では、特許文献2の技術で必要となる放電動作が不要であるから、放電動作に起因したコントラストの低下が抑制されるという利点がある。また、電気光学素子の点灯/消灯を指示するデータを保持する記憶回路を画素回路PIXに内蔵する必要はないから、特許文献3の技術と比較して画素回路PIXの小型化(さらには表示画像の高精細化)が容易であるという利点もある。また、画素回路PIXの構成が簡素化されるから、特許文献3の技術と比較して歩留まりを向上することも可能である。   In the first embodiment, when the voltage VA (± VA) corresponding to the gradation GW is applied to the liquid crystal element 50, the pixel electrode is connected from the inversion potential line 24 within the inversion period W in which the common potential LCCOM varies. The inversion potential LCCOMX is supplied to 52. That is, the fluctuation of the common potential LCCOM within the inversion period W does not affect the potential VP of the pixel electrode 52. Therefore, the polarity of the voltage VA of the liquid crystal element 50 can be reversed before and after the change of the common potential LCCOM while the liquid crystal element 50 is maintained at the gradation GW. With the above configuration, since the discharge operation required by the technique of Patent Document 2 is unnecessary, there is an advantage that a reduction in contrast due to the discharge operation is suppressed. Further, since it is not necessary to incorporate in the pixel circuit PIX a storage circuit that holds data for instructing turning on / off of the electro-optic element, the pixel circuit PIX can be downsized (and further displayed images can be compared with the technique of Patent Document 3). (High definition) is also easy. Further, since the configuration of the pixel circuit PIX is simplified, it is possible to improve the yield as compared with the technique of Patent Document 3.

ところで、液晶素子50の階調(透過率または反射率)は、図4に実線で図示したように、理想的には、印加電圧が所定の閾値VTHを上回ると階調GWに飽和する。しかし、実際には図4に鎖線で図示したように、閾値VTHを上回る範囲内でも電圧に応じて液晶素子50の階調が変化する場合がある。したがって、階調GWに対応する階調信号X[n]の供給後に画素電極52が電気的なフローティング状態に設定される構成では、例えば保持容量CSの電流のリークに起因して画素電極52の電位VPが変動した場合に、液晶素子50の階調が変化する可能性がある。すなわち、液晶素子50の階調を高精度に設定することが困難である。他方、第1実施形態においては、階調GWに対応する電圧VAの印加後に画素電極52の電位VPが反転用電位LCCOMXに維持される。したがって、図4の鎖線で示した特性の液晶素子50を採用した場合でも、液晶素子50の階調(動作点)を高精度に設定できるという利点がある。   Incidentally, the gradation (transmittance or reflectance) of the liquid crystal element 50 ideally saturates to the gradation GW when the applied voltage exceeds a predetermined threshold VTH, as shown by the solid line in FIG. However, in practice, as shown by the chain line in FIG. 4, the gradation of the liquid crystal element 50 may change depending on the voltage even within the range exceeding the threshold value VTH. Therefore, in the configuration in which the pixel electrode 52 is set in an electrically floating state after the gradation signal X [n] corresponding to the gradation GW is supplied, for example, due to the leakage of the current of the storage capacitor CS, the pixel electrode 52 When the potential VP fluctuates, the gradation of the liquid crystal element 50 may change. That is, it is difficult to set the gradation of the liquid crystal element 50 with high accuracy. On the other hand, in the first embodiment, the potential VP of the pixel electrode 52 is maintained at the inversion potential LCCOMX after application of the voltage VA corresponding to the gradation GW. Therefore, even when the liquid crystal element 50 having the characteristics shown by the chain line in FIG. 4 is employed, there is an advantage that the gradation (operating point) of the liquid crystal element 50 can be set with high accuracy.

<B:第2実施形態>
図13は、本発明の第2実施形態に係る電気光学装置100の画素回路PIXの回路図である。第2実施形態の画素回路PIXは、第1実施形態の画素回路PIXから容量線26を省略するとともに制御用容量C2を追加した構成である。第2実施形態のうち作用や機能が第1実施形態と同等である要素については詳細な説明を省略する。
<B: Second Embodiment>
FIG. 13 is a circuit diagram of the pixel circuit PIX of the electro-optical device 100 according to the second embodiment of the present invention. The pixel circuit PIX of the second embodiment has a configuration in which the capacitor line 26 is omitted from the pixel circuit PIX of the first embodiment and a control capacitor C2 is added. Detailed descriptions of elements of the second embodiment that have the same functions and functions as those of the first embodiment will be omitted.

図13に示すように、制御用容量C1は、第1制御スイッチTC1のゲートと第m行の反転用電位線24との間に介在する。すなわち、電極EB1は第1制御スイッチTC1のゲートに接続され、電極EB2は反転用電位線24に接続される。他方、制御用容量C2は、第1制御スイッチTC1のゲートと第m行の共通電位線22との間に介在する。具体的には、制御用容量C2は、第1制御スイッチTC1のゲートに接続された電極EC1と共通電位線22に接続された電極EC2と両電極間の誘電体とで構成される。   As shown in FIG. 13, the control capacitor C1 is interposed between the gate of the first control switch TC1 and the inversion potential line 24 in the m-th row. That is, the electrode EB1 is connected to the gate of the first control switch TC1, and the electrode EB2 is connected to the inversion potential line 24. On the other hand, the control capacitor C2 is interposed between the gate of the first control switch TC1 and the common potential line 22 in the m-th row. Specifically, the control capacitor C2 is composed of an electrode EC1 connected to the gate of the first control switch TC1, an electrode EC2 connected to the common potential line 22, and a dielectric between the electrodes.

以上のように制御用容量C1の電極EB2には反転用電位LCCOMXが供給され、制御用容量C2の電極EC2には共通電位LCCOMが供給される。共通電位LCCOMと反転用電位LCCOMXとは電位を反転させた関係にある。具体的には、電極EB2の反転用電位LCCOMXが高位側電位VHおよび低位側電位VLの一方から他方に変化するときに電極EC2の共通電位LCCOMは逆方向に変化する。したがって、第1制御スイッチTC1のゲートの電位が電極EC2の共通電位LCCOMに連動して変化しようとする作用と電極EB2の反転用電位LCCOMXに連動して変化しようとする作用とが相殺される。すなわち、制御用容量C1と制御用容量C2との協働で、第1制御スイッチTC1のゲートの電位を保持する機能(第1実施形態の制御用容量C1と同様の機能)が実現される。   As described above, the inversion potential LCCOMX is supplied to the electrode EB2 of the control capacitor C1, and the common potential LCCOM is supplied to the electrode EC2 of the control capacitor C2. The common potential LCCOM and the inversion potential LCCOMX are in a relationship of inverting the potential. Specifically, when the inversion potential LCCOMX of the electrode EB2 changes from one of the higher potential VH and the lower potential VL to the other, the common potential LCCOM of the electrode EC2 changes in the reverse direction. Therefore, the action of the gate potential of the first control switch TC1 changing in conjunction with the common potential LCCOM of the electrode EC2 and the action of changing in conjunction with the inversion potential LCCOMX of the electrode EB2 are offset. That is, the function of holding the gate potential of the first control switch TC1 (the same function as the control capacitor C1 of the first embodiment) is realized in cooperation with the control capacitor C1 and the control capacitor C2.

以上の構成においても第1実施形態と同様の作用および効果が実現される。また、第2実施形態においては、第1実施形態のM本の容量線26が素子部10から省略されるから、素子部10の構成が簡素化されるという利点がある。   Even in the above configuration, the same operations and effects as those of the first embodiment are realized. In the second embodiment, since the M capacitor lines 26 of the first embodiment are omitted from the element unit 10, there is an advantage that the configuration of the element unit 10 is simplified.

<C:変形例>
以上の各形態には様々な変形が加えられる。具体的な変形の態様を以下に例示する。以下の例示から任意に選択された2以上の態様は併合され得る。
<C: Modification>
Various modifications are added to the above embodiments. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples may be merged.

(1)変形例1
画素回路PIXの構成は適宜に変更される。例えば、以上の各形態では、選択スイッチTSLと第2制御スイッチTC2とを共通の走査線12に接続したが、選択スイッチTSLと第2制御スイッチTC2とを別個の配線に接続したうえで相異なる信号で制御する構成も採用される。もっとも、選択スイッチTSLと第2制御スイッチTC2とを共通の走査線12に接続した構成によれば、両者を別個の配線に接続した構成と比較して素子部10の簡素化(配線数の削減)が実現されるという利点がある。
(1) Modification 1
The configuration of the pixel circuit PIX is changed as appropriate. For example, in the above embodiments, the selection switch TSL and the second control switch TC2 are connected to the common scanning line 12. However, the selection switch TSL and the second control switch TC2 are different from each other after being connected to separate wirings. A configuration controlled by signals is also employed. However, according to the configuration in which the selection switch TSL and the second control switch TC2 are connected to the common scanning line 12, the element unit 10 is simplified (reduction in the number of wirings) compared to the configuration in which both are connected to separate wirings. ) Is realized.

以上の各形態では共通電位線22や反転用電位線24や容量線26を行毎に独立に形成したが、複数行毎に1本の配線(共通電位線22,反転用電位線24,容量線26)を形成したうえで複数行の各画素回路PIXの駆動に共用する構成も採用される。また、液晶素子50の容量値が充分に確保されるならば保持容量CSは省略され得る。さらに、例えば第1制御スイッチTC1のゲートに付随する容量(例えば第1制御スイッチTC1のゲート容量や寄生容量)が充分に確保されるならば制御用容量C1(第2実施形態の制御用容量C2)は省略され得る。   In each of the above embodiments, the common potential line 22, the inversion potential line 24, and the capacitance line 26 are formed independently for each row. However, one wiring (the common potential line 22, the inversion potential line 24, and the capacitance is provided for each row. A configuration in which the line 26) is formed and shared for driving the pixel circuits PIX in a plurality of rows is also employed. Further, if the capacitance value of the liquid crystal element 50 is sufficiently secured, the storage capacitor CS can be omitted. Further, for example, if a capacitance associated with the gate of the first control switch TC1 (for example, a gate capacitance or a parasitic capacitance of the first control switch TC1) is sufficiently secured, the control capacitor C1 (the control capacitor C2 of the second embodiment). ) May be omitted.

(2)変形例2
画素電極52と共通電極54との間の電圧がゼロである場合に階調が最高(白色)となるノーマリーホワイトモードの液晶素子50を採用した電気光学装置100にも以上の各形態が同様に適用される。すなわち、白色に相当する階調GWを階調データD[n]が指示する場合(液晶素子50に電圧±VBを印加する場合)の反転期間Wでは画素電極52が電気的なフローティング状態に設定され、黒色に相当する階調GBを階調データD[n]が指示する場合(液晶素子50に電圧±VAを印加する場合)の反転期間Wでは画素電極52に反転用電位LCCOMXが供給される。すなわち、以上の各形態における駆動方法は、電圧±VAを液晶素子50に印加する場合に第1制御スイッチTC1をオン状態に制御し(すなわち、画素電極52と反転用電位線24とを接続し)、電圧±VAとは異なる電圧±VBを液晶素子50に印加する場合に第1制御スイッチTC1をオフ状態に制御する(すなわち、画素電極52と反転用電位線24とを絶縁する)方法として包括される。
(2) Modification 2
Each of the above forms is the same for the electro-optical device 100 employing the normally white mode liquid crystal element 50 in which the gradation is highest (white) when the voltage between the pixel electrode 52 and the common electrode 54 is zero. Applies to That is, the pixel electrode 52 is set in an electrically floating state during the inversion period W when the gradation data D [n] indicates the gradation GW corresponding to white (when the voltage ± VB is applied to the liquid crystal element 50). The inversion potential LCCOMX is supplied to the pixel electrode 52 in the inversion period W when the gradation data D [n] indicates the gradation GB corresponding to black (when the voltage ± VA is applied to the liquid crystal element 50). The That is, in the driving methods in the above embodiments, when the voltage ± VA is applied to the liquid crystal element 50, the first control switch TC1 is controlled to be in an ON state (that is, the pixel electrode 52 and the inversion potential line 24 are connected). ), When applying a voltage ± VB different from the voltage ± VA to the liquid crystal element 50, the first control switch TC1 is controlled to be turned off (that is, the pixel electrode 52 and the inversion potential line 24 are insulated). It is included.

(3)変形例3
以上の各形態では、液晶素子50に電圧±VAを印加した場合に、水平走査期間H[m]の経過後から次回の水平走査期間H[m]の開始まで第1制御スイッチTC1がオン状態に維持される。しかし、共通電位LCCOMに起因した画素電極52の電位VPの変動が顕著となるのは共通電位LCCOMの変動時であるから、共通電位LCCOMの変動時を含む所定の期間(例えば反転期間W)にて画素電極52に反転用電位LCCOMXが供給される構成であれば、他の期間における画素電極52と反転用電位線24との導通/非導通に関わらず、本発明の所期の効果は実現される。ただし、共通電位LCCOMの変動以外の要因(例えば保持容量CSや選択スイッチTSLでの電流のリーク)に起因した画素電極52の電位VPの変動を防止するという観点からすると、液晶素子50に電圧±VAを印加した場合には、以上の各形態で例示したように反転期間W以外の期間でも画素電極52に反転用電位LCCOMXを供給する構成が好適である。
(3) Modification 3
In each of the above embodiments, when the voltage ± VA is applied to the liquid crystal element 50, the first control switch TC1 is in the ON state from the elapse of the horizontal scanning period H [m] until the start of the next horizontal scanning period H [m]. Maintained. However, since the change in the potential VP of the pixel electrode 52 due to the common potential LCCOM becomes noticeable when the common potential LCCOM changes, during a predetermined period (for example, the inversion period W) including the change in the common potential LCCOM. If the inversion potential LCCOMX is supplied to the pixel electrode 52, the expected effect of the present invention is realized regardless of the conduction / non-conduction between the pixel electrode 52 and the inversion potential line 24 in other periods. Is done. However, from the viewpoint of preventing fluctuations in the potential VP of the pixel electrode 52 due to factors other than fluctuations in the common potential LCCOM (for example, current leakage in the storage capacitor CS and the selection switch TSL), the voltage ± When VA is applied, it is preferable to supply the inversion potential LCCOMX to the pixel electrode 52 even during a period other than the inversion period W as illustrated in the above embodiments.

(4)変形例4
共通電位LCCOMや反転用電位LCCOMXの変動の周期は任意に変更される。例えば、共通電位LCCOMや反転用電位LCCOMXをサブフィールドSF毎に高位側電位VHおよび低位側電位VLの一方から他方に変化させる構成(サブフィールドSFを極性反転の単位期間とした構成)も採用される。
(4) Modification 4
The cycle of fluctuation of the common potential LCCOM and the inversion potential LCCOMX is arbitrarily changed. For example, a configuration in which the common potential LCCOM and the inversion potential LCCOMX are changed from one of the higher potential VH and the lower potential VL to the other for each subfield SF (configuration in which the subfield SF is a unit period for polarity inversion) is also employed. The

(5)変形例5
液晶素子50は電気光学素子の例示である。例えば、電気泳動素子や発光素子(例えば有機EL素子)を以上の各形態の液晶素子50に置換した構成も採用される。すなわち、電気光学素子は、電圧(電界)の印加や電流の供給などの電気的な作用に応じて階調(透過率や輝度などの光学的な特性)が変化する被駆動素子として包括される。
(5) Modification 5
The liquid crystal element 50 is an example of an electro-optical element. For example, the structure which substituted the electrophoretic element and the light emitting element (for example, organic EL element) by the liquid crystal element 50 of each above form is also employ | adopted. In other words, the electro-optical element is included as a driven element whose gradation (optical characteristics such as transmittance and luminance) changes according to an electrical action such as application of voltage (electric field) or supply of current. .

<D:応用例>
次に、以上の各態様に係る電気光学装置100を利用した電子機器について説明する。図14ないし図16には、電気光学装置100を表示装置として採用した電子機器の形態が図示されている。
<D: Application example>
Next, electronic devices using the electro-optical device 100 according to each of the above aspects will be described. FIGS. 14 to 16 show forms of electronic devices that employ the electro-optical device 100 as a display device.

図14は、電気光学装置100を採用した可搬型のパーソナルコンピュータの構成を示す斜視図である。パーソナルコンピュータ2000は、各種の画像を表示する電気光学装置100と、電源スイッチ2001やキーボード2002が設置された本体部2010とを具備する。   FIG. 14 is a perspective view illustrating a configuration of a portable personal computer that employs the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

図15は、電気光学装置100を適用した携帯電話機の構成を示す斜視図である。携帯電話機3000は、複数の操作ボタン3001およびスクロールボタン3002と、各種の画像を表示する電気光学装置100とを備える。スクロールボタン3002を操作することによって、電気光学装置100に表示される画面がスクロールされる。   FIG. 15 is a perspective view illustrating a configuration of a mobile phone to which the electro-optical device 100 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled.

図16は、電気光学装置100を適用した携帯情報端末(PDA:Personal Digital Assistants)の構成を示す斜視図である。情報携帯端末4000は、複数の操作ボタン4001および電源スイッチ4002と、各種の画像を表示する電気光学装置100とを備える。電源スイッチ4002を操作すると、住所録やスケジュール帳といった様々な情報が電気光学装置100に表示される。   FIG. 16 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The portable information terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 that displays various images. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the electro-optical device 100.

なお、本発明に係る電気光学装置が適用される電子機器としては、図14から図16に例示した機器のほか、プロジェクタ、デジタルスチルカメラ、テレビ、ビデオカメラ、カーナビゲーション装置、ページャ、電子手帳、電子ペーパー、電卓、ワードプロセッサ、ワークステーション、テレビ電話、POS端末、プリンタ、スキャナ、複写機、ビデオプレーヤ、タッチパネルを備えた機器等などが挙げられる。   The electronic apparatus to which the electro-optical device according to the invention is applied includes, in addition to the apparatuses illustrated in FIGS. 14 to 16, a projector, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, Examples include electronic paper, calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

100……電気光学装置、10……素子部、PIX……画素回路、12……走査線、14……信号線、16……制御線、22……共通電位線、24……反転用電位線、26……容量線、30……駆動回路、32……走査線駆動回路、34……信号線駆動回路、42……電位生成回路、44……制御回路、52……画素電極、54……共通電極、56……液晶、TSL……選択スイッチ、TC1……第1制御スイッチ、TC2……第2制御スイッチ、CS……保持容量、C1,C2……制御用容量、62……分配回路、621……選択回路、623……第1ラッチ回路、625……第2ラッチ回路、64……出力回路、U[1]〜U[N]……単位回路、641……電位選択回路、643……電位選択回路。
DESCRIPTION OF SYMBOLS 100 ... Electro-optical device, 10 ... Element part, PIX ... Pixel circuit, 12 ... Scanning line, 14 ... Signal line, 16 ... Control line, 22 ... Common potential line, 24 ... Inversion potential , 26... Capacitance line, 30... Drive circuit, 32... Scan line drive circuit, 34... Signal line drive circuit, 42. ... Common electrode, 56 ... Liquid crystal, TSL ... Selection switch, TC1 ... First control switch, TC2 ... Second control switch, CS ... Holding capacity, C1, C2 ... Control capacity, 62 ... Distribution circuit, 621 ... selection circuit, 623 ... first latch circuit, 625 ... second latch circuit, 64 ... output circuit, U [1] to U [N] ... unit circuit, 641 ... potential selection Circuit, 643... Potential selection circuit.

Claims (9)

高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、
前記反転用電位が前記高位側電位となる単位期間にて前記低位側電位に設定されて前記反転用電位が前記低位側電位となる単位期間にて前記高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子と、
前記画素電極と前記反転用電位線との接続を制御する第1制御スイッチと
を具備する電気光学装置の駆動方法であって、
指定階調に応じた階調電位を前記単位期間にて前記画素電極に供給する一方、
前記電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオン状態に制御し、
前記電気光学素子の両電極間の電圧が前記第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオフ状態に制御する
電気光学装置の駆動方法。
An inversion potential line that is supplied with an inversion potential that sequentially changes every unit period from one of the high potential and the low potential to the other;
A common potential that is set to the low potential in the unit period in which the inversion potential becomes the high potential and supplied to the high potential in the unit period in which the inversion potential becomes the low potential is supplied. An electro-optic element including a common electrode and a pixel electrode,
A driving method of an electro-optical device comprising: a first control switch that controls connection between the pixel electrode and the inversion potential line;
While supplying a gradation potential corresponding to a specified gradation to the pixel electrode in the unit period,
In the case where a gradation potential is supplied at which the voltage between both electrodes of the electro-optic element is the first voltage, the first control switch is turned on during a period including the time when the common potential fluctuates after the supply of the gradation potential. Control to ON state,
When a gradation potential is supplied such that the voltage between both electrodes of the electro-optic element is a second voltage different from the first voltage, the period including the time when the common potential fluctuates after the gradation potential is supplied. A method for driving the electro-optical device, wherein the first control switch is controlled to be in an OFF state.
高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、
前記反転用電位が前記高位側電位となる単位期間にて前記低位側電位に設定されて前記反転用電位が前記低位側電位となる単位期間にて前記高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子と、
前記画素電極と前記反転用電位線との接続を制御する第1制御スイッチと
を具備する電気光学装置。
An inversion potential line that is supplied with an inversion potential that sequentially changes every unit period from one of the high potential and the low potential to the other;
A common potential that is set to the low potential in the unit period in which the inversion potential becomes the high potential and supplied to the high potential in the unit period in which the inversion potential becomes the low potential is supplied. An electro-optic element including a common electrode and a pixel electrode,
An electro-optical device comprising: a first control switch that controls connection between the pixel electrode and the inversion potential line.
駆動回路を具備し、
前記駆動回路は、
指定階調に応じた階調電位を前記単位期間にて前記画素電極に供給する一方、
前記電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオン状態に制御し、
前記電気光学素子の両電極間の電圧が前記第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオフ状態に制御する
請求項2の電気光学装置。
Comprising a drive circuit;
The drive circuit is
While supplying a gradation potential corresponding to a specified gradation to the pixel electrode in the unit period,
In the case where a gradation potential is supplied at which the voltage between both electrodes of the electro-optic element is the first voltage, the first control switch is turned on during a period including the time when the common potential fluctuates after the supply of the gradation potential. Control to ON state,
When a gradation potential is supplied such that the voltage between both electrodes of the electro-optic element is a second voltage different from the first voltage, the period including the time when the common potential fluctuates after the gradation potential is supplied. The electro-optical device according to claim 2, wherein the first control switch is controlled to be in an OFF state.
前記第1制御スイッチを制御する制御信号が供給される制御線と、
前記第1制御スイッチのゲートと前記制御線との接続を制御する第2制御スイッチと、
前記第1制御スイッチのゲートの電位を保持する第1制御用容量と
を具備する請求項2または請求項3の電気光学装置。
A control line to which a control signal for controlling the first control switch is supplied;
A second control switch for controlling connection between the gate of the first control switch and the control line;
The electro-optical device according to claim 2, further comprising: a first control capacitor that holds a potential of the gate of the first control switch.
前記共通電位が供給される共通電位線と、
前記共通電位線と前記画素電極との間に介在する保持容量と、
前記第1制御スイッチのゲートと前記共通電位線との間に介在する第2制御用容量と
を具備し、
前記第1制御用容量は、前記第1制御スイッチのゲートと前記反転用電位線との間に介在する
請求項4の電気光学装置。
A common potential line to which the common potential is supplied;
A storage capacitor interposed between the common potential line and the pixel electrode;
A second control capacitor interposed between the gate of the first control switch and the common potential line;
The electro-optical device according to claim 4, wherein the first control capacitor is interposed between a gate of the first control switch and the inversion potential line.
相交差する走査線および信号線と、
前記走査線の選択時に前記信号線と前記画素電極とを接続する選択スイッチと
を具備し、
前記選択スイッチと前記第2制御スイッチとは共通の信号で制御される
請求項4または請求項5の電気光学装置。
Crossing scan lines and signal lines;
A selection switch for connecting the signal line and the pixel electrode when the scanning line is selected;
The electro-optical device according to claim 4, wherein the selection switch and the second control switch are controlled by a common signal.
相交差する複数の走査線および複数の信号線と、
高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、
前記複数の走査線と前記複数の信号線との各交差に対応して配置された複数の画素回路と、
前記各画素回路を駆動する駆動回路とを具備し、
前記複数の画素回路の各々は、
前記反転用電位が前記高位側電位となる単位期間にて前記低位側電位に設定されて前記反転用電位が前記低位側電位となる単位期間にて前記高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子と、
前記走査線の選択時に前記信号線と前記画素電極とを接続する選択スイッチと、
前記画素電極と前記反転用電位線との接続を制御する第1制御スイッチとを含み、
前記駆動回路は、
前記単位期間にて前記複数の走査線の各々を順次に選択するとともに当該走査線に対応する前記各画素回路の指定階調に応じた階調電位を前記複数の信号線の各々に供給する一方、
前記複数の画素回路の各々について、
前記電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオン状態に制御し、
前記電気光学素子の両電極間の電圧が前記第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオフ状態に制御する
電気光学装置。
A plurality of scanning lines and a plurality of signal lines intersecting each other;
An inversion potential line that is supplied with an inversion potential that sequentially changes every unit period from one of the high potential and the low potential to the other;
A plurality of pixel circuits arranged corresponding to each intersection of the plurality of scanning lines and the plurality of signal lines;
A drive circuit for driving each of the pixel circuits,
Each of the plurality of pixel circuits is
A common potential that is set to the low potential in the unit period in which the inversion potential becomes the high potential and supplied to the high potential in the unit period in which the inversion potential becomes the low potential is supplied. An electro-optic element including a common electrode and a pixel electrode,
A selection switch for connecting the signal line and the pixel electrode when the scanning line is selected;
A first control switch for controlling connection between the pixel electrode and the inversion potential line;
The drive circuit is
While each of the plurality of scanning lines is sequentially selected in the unit period, a gradation potential corresponding to a designated gradation of each pixel circuit corresponding to the scanning line is supplied to each of the plurality of signal lines. ,
For each of the plurality of pixel circuits,
In the case where a gradation potential is supplied at which the voltage between both electrodes of the electro-optic element is the first voltage, the first control switch is turned on during a period including the time when the common potential fluctuates after the supply of the gradation potential. Control to ON state,
When a gradation potential is supplied such that the voltage between both electrodes of the electro-optic element is a second voltage different from the first voltage, the period including the time when the common potential fluctuates after the gradation potential is supplied. An electro-optical device that controls the first control switch to an OFF state.
請求項2から請求項7の何れかの電気光学装置を具備する電子機器。   An electronic apparatus comprising the electro-optical device according to claim 2. 高位側電位および低位側電位の一方から他方に単位期間毎に順次に変動する反転用電位が供給される反転用電位線と、
前記反転用電位が前記高位側電位となる単位期間にて前記低位側電位に設定されて前記反転用電位が前記低位側電位となる単位期間にて前記高位側電位に設定される共通電位が供給される共通電極と画素電極とを含む電気光学素子と、
前記画素電極と前記反転用電位線との接続を制御する第1制御スイッチと
を具備する電気光学装置の駆動回路であって、
指定階調に応じた階調電位を前記単位期間にて前記画素電極に供給する一方、
前記電気光学素子の両電極間の電圧が第1電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオン状態に制御し、
前記電気光学素子の両電極間の電圧が前記第1電圧とは異なる第2電圧となる階調電位を供給した場合、当該階調電位の供給以後に前記共通電位が変動する時点を含む期間にて前記第1制御スイッチをオフ状態に制御する
電気光学装置の駆動回路。
An inversion potential line that is supplied with an inversion potential that sequentially changes every unit period from one of the high potential and the low potential to the other;
A common potential that is set to the low potential in the unit period in which the inversion potential becomes the high potential and supplied to the high potential in the unit period in which the inversion potential becomes the low potential is supplied. An electro-optic element including a common electrode and a pixel electrode,
A drive circuit for an electro-optical device comprising: a first control switch that controls connection between the pixel electrode and the inversion potential line;
While supplying a gradation potential corresponding to a specified gradation to the pixel electrode in the unit period,
In the case where a gradation potential is supplied at which the voltage between both electrodes of the electro-optic element is the first voltage, the first control switch is turned on during a period including the time when the common potential fluctuates after the supply of the gradation potential. Control to ON state,
When a gradation potential is supplied such that the voltage between both electrodes of the electro-optic element is a second voltage different from the first voltage, the period including the time when the common potential fluctuates after the gradation potential is supplied. A drive circuit for the electro-optical device that controls the first control switch to an OFF state.
JP2009171937A 2009-07-23 2009-07-23 Electrooptical device, electronic device, and method and circuit for driving electrooptical device Pending JP2011027892A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013105393A1 (en) * 2012-01-12 2013-07-18 シャープ株式会社 Pixel circuit and display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013105393A1 (en) * 2012-01-12 2013-07-18 シャープ株式会社 Pixel circuit and display device

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