JP5663150B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5663150B2
JP5663150B2 JP2009166030A JP2009166030A JP5663150B2 JP 5663150 B2 JP5663150 B2 JP 5663150B2 JP 2009166030 A JP2009166030 A JP 2009166030A JP 2009166030 A JP2009166030 A JP 2009166030A JP 5663150 B2 JP5663150 B2 JP 5663150B2
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Japan
Prior art keywords
substrate
oxide film
base substrate
semiconductor
nitrogen
Prior art date
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Expired - Fee Related
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JP2009166030A
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English (en)
Japanese (ja)
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JP2010050444A5 (enExample
JP2010050444A (ja
Inventor
章広 石塚
章広 石塚
慎也 笹川
慎也 笹川
求 倉田
求 倉田
厚史 彦坂
厚史 彦坂
大河 村岡
大河 村岡
整 中山
整 中山
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2009166030A priority Critical patent/JP5663150B2/ja
Publication of JP2010050444A publication Critical patent/JP2010050444A/ja
Publication of JP2010050444A5 publication Critical patent/JP2010050444A5/ja
Application granted granted Critical
Publication of JP5663150B2 publication Critical patent/JP5663150B2/ja
Expired - Fee Related legal-status Critical Current
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Classifications

    • H10P90/1916—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H10W10/181—

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2009166030A 2008-07-22 2009-07-14 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5663150B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009166030A JP5663150B2 (ja) 2008-07-22 2009-07-14 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008189015 2008-07-22
JP2008189015 2008-07-22
JP2009166030A JP5663150B2 (ja) 2008-07-22 2009-07-14 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2010050444A JP2010050444A (ja) 2010-03-04
JP2010050444A5 JP2010050444A5 (enExample) 2012-08-02
JP5663150B2 true JP5663150B2 (ja) 2015-02-04

Family

ID=41696765

Family Applications (1)

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JP2009166030A Expired - Fee Related JP5663150B2 (ja) 2008-07-22 2009-07-14 Ｓｏｉ基板の作製方法

Country Status (2)

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US (1) US8247308B2 (enExample)
JP (1) JP5663150B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US20060228492A1 (en) * 2005-04-07 2006-10-12 Sumco Corporation Method for manufacturing SIMOX wafer
JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US20120021588A1 (en) * 2010-07-23 2012-01-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate and semiconductor device
US9773678B2 (en) * 2014-07-10 2017-09-26 Kabushiki Kaisha Toyota Jidoshokki Semiconductor substrate and method for manufacturing semiconductor substrate
JP6313189B2 (ja) * 2014-11-04 2018-04-18 東芝メモリ株式会社 半導体装置の製造方法
CN105702742A (zh) * 2016-02-25 2016-06-22 深圳市华星光电技术有限公司 氧化物薄膜晶体管及其制备方法
DE102016114949B4 (de) 2016-08-11 2023-08-24 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauelements
EP3652780B1 (en) * 2017-07-14 2022-01-05 Sunedison Semiconductor Limited Method of manufacture of a semiconductor on insulator structure
CN116583400A (zh) * 2020-12-18 2023-08-11 Ａｇｃ株式会社 接合体、接合体的制造方法以及发光装置
JPWO2022131066A1 (enExample) * 2020-12-18 2022-06-23
US20240339324A1 (en) * 2023-04-05 2024-10-10 Applied Materials, Inc. Atmospheric Pressure Plasma for Substrate Annealing

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
TW308707B (en) 1995-12-15 1997-06-21 Komatsu Denshi Kinzoku Kk Manufacturing method of bonding SOI wafer
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
US6583440B2 (en) 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
JP4507395B2 (ja) 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
JP2004134675A (ja) 2002-10-11 2004-04-30 Sharp Corp Ｓｏｉ基板、表示装置およびｓｏｉ基板の製造方法
US7508034B2 (en) 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
US20070110917A1 (en) 2003-12-02 2007-05-17 Bondtech, Inc Bonding method, device formed by such method, surface activating unit and bonding apparatus comprising such unit
JP3751972B2 (ja) 2003-12-02 2006-03-08 有限会社ボンドテック 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US7261793B2 (en) * 2004-08-13 2007-08-28 Hewlett-Packard Development Company, L.P. System and method for low temperature plasma-enhanced bonding
US7148124B1 (en) * 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
KR20080086899A (ko) 2005-12-27 2008-09-26 신에쓰 가가꾸 고교 가부시끼가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
US7745309B2 (en) * 2006-08-09 2010-06-29 Applied Materials, Inc. Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure
CN101281912B (zh) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
EP1993128A3 (en) * 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US7696058B2 (en) 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8093136B2 (en) 2007-12-28 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8119490B2 (en) 2008-02-04 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5548395B2 (ja) 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法

Also Published As

Publication number Publication date
US20100047997A1 (en) 2010-02-25
US8247308B2 (en) 2012-08-21
JP2010050444A (ja) 2010-03-04

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