JP5649777B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5649777B2 JP5649777B2 JP2008261805A JP2008261805A JP5649777B2 JP 5649777 B2 JP5649777 B2 JP 5649777B2 JP 2008261805 A JP2008261805 A JP 2008261805A JP 2008261805 A JP2008261805 A JP 2008261805A JP 5649777 B2 JP5649777 B2 JP 5649777B2
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- JP
- Japan
- Prior art keywords
- signal
- delay element
- delay
- element array
- circuit
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
11 メモリセルアレイ
12 ワードドライバ
13 センスアンプ群
14 カラムスイッチ
21 アドレス端子群
22 アドレスバッファ
23 ロウアドレスデコーダ
24 カラムアドレスデコーダ
30 データ入出力回路
31 データ入出力端子
41〜44 コマンド端子
45 コマンドデコーダ
50 モードレジスタ
60 内部電圧生成回路
61,62 電源端子
70 内部クロック生成回路
70a DLL回路
71 クロック端子
100 タイミング制御回路
110 パルス発生回路
120 タイミングモニタ
121 第1の遅延素子列
122 第2の遅延素子列
123 検出回路
1230〜123n 比較回路
124 設定回路
130 遅延制御回路
BL ビット線
MC メモリセル
WL ワード線
Claims (10)
- 設定された遅延量だけ基準信号を遅延させることによって動作タイミング信号を生成する遅延制御回路と、
互いに動作条件が異なる第1及び第2の遅延素子列と、
前記第1及び第2の遅延素子列に同時に入力されたパルス信号の伝搬速度差を検出する検出回路と、
前記検出回路による検出結果に基づいて、前記遅延制御回路の前記遅延量を設定する設定回路と、を備え、
前記パルス信号が間欠的に生成されることを特徴とする半導体装置。 - 前記第1及び第2の遅延素子列は、PVT変動による遅延量の変化が互いに異なることを特徴とする請求項1に記載の半導体装置。
- 前記第1の遅延素子列と前記第2の遅延素子列は、動作電圧が互いに異なることを特徴とする請求項2に記載の半導体装置。
- 前記第1の遅延素子列と前記第2の遅延素子列は、ファンアウトが互いに異なることを特徴とする請求項2又は3に記載の半導体装置。
- 前記第1の遅延素子列の動作電圧は前記第2の遅延素子列の動作電圧よりも高く、前記第1の遅延素子列のファンアウトは前記第2の遅延素子列のファンアウトよりも小さいことを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- 前記遅延制御回路は第3の遅延素子列を有しており、前記第1の遅延素子列と前記第3の遅延素子列は動作電圧及びファンアウトが同じであることを特徴とする請求項5に記載の半導体装置。
- 前記設定回路は、
前記第1の遅延素子列を伝搬する前記パルス信号の伝搬速度に対して、前記第2の遅延素子列を伝搬する前記パルス信号の伝搬速度が速いほど、前記遅延制御回路の前記遅延量が大きくなるよう設定し、
前記第1の遅延素子列を伝搬する前記パルス信号の伝搬速度に対して、前記第2の遅延素子列を伝搬する前記パルス信号の伝搬速度が遅いほど、前記遅延制御回路の前記遅延量が小さくなるよう設定することを特徴とする請求項6に記載の半導体装置。 - 複数のワード線、複数のビット線及びこれらの交点に配置された複数のメモリセルを有するメモリセルアレイと、
前記複数のワード線のいずれかを選択するワードドライバと、
対応する前記ビット線にそれぞれ接続された複数のセンスアンプと、をさらに備え、
前記基準信号は前記ワードドライバの活性化タイミングに同期した信号であり、前記動作タイミング信号は前記センスアンプを活性化させるための信号であることを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。 - 複数のワード線、複数のビット線及びこれらの交点に配置された複数のメモリセルを有するメモリセルアレイと、
前記複数のワード線のいずれかを選択するワードドライバと、
対応する前記ビット線にそれぞれ接続された複数のセンスアンプと、
前記複数のセンスアンプのいずれかを選択するカラムスイッチと、をさらに備え、
前記基準信号は前記ワードドライバの活性化タイミングに同期した信号であり、前記動作タイミング信号は前記カラムスイッチを活性化させるための信号であることを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。 - 前記メモリセルはDRAMセルであり、前記パルス信号は少なくともリフレッシュコマンドの発行に応答して生成されることを特徴とする請求項8又は9に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008261805A JP5649777B2 (ja) | 2008-10-08 | 2008-10-08 | 半導体装置 |
US12/588,200 US8134877B2 (en) | 2008-10-08 | 2009-10-07 | Semiconductor device having delay control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008261805A JP5649777B2 (ja) | 2008-10-08 | 2008-10-08 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010092542A JP2010092542A (ja) | 2010-04-22 |
JP5649777B2 true JP5649777B2 (ja) | 2015-01-07 |
Family
ID=42075710
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008261805A Expired - Fee Related JP5649777B2 (ja) | 2008-10-08 | 2008-10-08 | 半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US8134877B2 (ja) |
JP (1) | JP5649777B2 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8379459B2 (en) * | 2010-07-21 | 2013-02-19 | International Business Machines Corporation | Memory system with delay locked loop (DLL) bypass control |
US9159383B2 (en) * | 2012-04-11 | 2015-10-13 | Micron Technology, Inc. | Signal management in a memory device |
KR102008412B1 (ko) * | 2013-03-04 | 2019-08-08 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이 반도체 장치를 포함하는 마이크로프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
US9627061B2 (en) | 2013-03-04 | 2017-04-18 | SK Hynix Inc. | Electronic device having resistance element |
KR102043727B1 (ko) * | 2013-03-04 | 2019-12-02 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법, 이 반도체 장치를 포함하는 마이크로 프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
KR102092772B1 (ko) * | 2013-03-27 | 2020-03-24 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법, 이 반도체 장치를 포함하는 마이크로 프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
US9865806B2 (en) | 2013-06-05 | 2018-01-09 | SK Hynix Inc. | Electronic device and method for fabricating the same |
US10490741B2 (en) | 2013-06-05 | 2019-11-26 | SK Hynix Inc. | Electronic device and method for fabricating the same |
KR102025256B1 (ko) * | 2013-07-25 | 2019-09-26 | 에스케이하이닉스 주식회사 | 전자 장치 및 그 제조 방법 |
US9064559B2 (en) | 2013-08-15 | 2015-06-23 | Arm Limited | Memory device and method of performing access operations within such a memory device |
US11658668B2 (en) * | 2018-06-14 | 2023-05-23 | SK Hynix Inc. | Semiconductor device |
CN111398775B (zh) * | 2019-01-03 | 2024-02-06 | 瑞昱半导体股份有限公司 | 电路运行速度检测电路 |
US10910024B1 (en) * | 2019-10-08 | 2021-02-02 | Winbond Electronics Corp. | Memory device and data reading method thereof |
US11164620B1 (en) | 2020-06-03 | 2021-11-02 | Micron Technology, Inc. | Timing signal calibration for access operation of a memory device |
CN112685982B (zh) * | 2020-12-31 | 2023-03-24 | 海光信息技术股份有限公司 | 电路检测方法、装置、存储介质及电子设备 |
CN115083471A (zh) * | 2021-03-10 | 2022-09-20 | 华邦电子股份有限公司 | 半导体存储装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3359618B2 (ja) * | 1992-06-10 | 2002-12-24 | 松下電器産業株式会社 | 遅延時間補正機能を備えた半導体集積回路及び電源回路 |
JP2800690B2 (ja) * | 1994-07-28 | 1998-09-21 | 日本電気株式会社 | 位相同期回路 |
JP2000201058A (ja) * | 1999-01-05 | 2000-07-18 | Mitsubishi Electric Corp | 半導体装置 |
JP4002378B2 (ja) * | 1999-12-27 | 2007-10-31 | エルピーダメモリ株式会社 | 電子回路 |
JP2003023343A (ja) * | 2001-07-10 | 2003-01-24 | Mitsubishi Electric Corp | 遅延信号生成回路 |
JP2003258610A (ja) * | 2002-02-26 | 2003-09-12 | Fujitsu Ltd | 半導体集積回路及び半導体装置 |
JP4598420B2 (ja) | 2004-03-18 | 2010-12-15 | 富士通セミコンダクター株式会社 | 半導体記憶装置、及びタイミング制御方法 |
KR100889311B1 (ko) * | 2007-02-23 | 2009-03-18 | 주식회사 하이닉스반도체 | 비트라인 감지증폭기를 포함하는 반도체메모리소자 |
US7548471B2 (en) * | 2007-09-21 | 2009-06-16 | Qimonda North America Corp. | Method and apparatus for adjusting the timing of an electronic circuit |
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2008
- 2008-10-08 JP JP2008261805A patent/JP5649777B2/ja not_active Expired - Fee Related
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2009
- 2009-10-07 US US12/588,200 patent/US8134877B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2010092542A (ja) | 2010-04-22 |
US20100085824A1 (en) | 2010-04-08 |
US8134877B2 (en) | 2012-03-13 |
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