JP5645377B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention includes a first electrode, a second electrode, and a gate electrode. Under the condition that a potential higher than that of the second electrode is applied to the first electrode, the potential between the first electrode and the second electrode depends on the potential of the gate electrode. The present invention relates to a semiconductor device in which a current flows from the second electrode to the first electrode under the condition that the conduction and non-conduction are switched and a potential higher than that of the first electrode is applied to the second electrode.
For example, a vertical n-channel MOS is usually used under the condition that a higher potential is applied to the back electrode (drain electrode) than the front electrode (source electrode). In this case, when an on potential is applied to the gate electrode, the back electrode and the front electrode are conducted and current flows, and when no on potential is applied to the gate electrode, the back electrode and the front electrode are not conducted and current does not flow. When a higher potential is applied to the front electrode than to the rear electrode, a forward voltage is applied to the diode built in the n-channel MOS, and current flows from the front electrode to the rear electrode. In the above, the surface means the side where the gate electrode is formed.
For example, a vertical p-channel MOS is normally used under the condition that a higher potential is applied to the front electrode (source electrode) than to the rear electrode (drain electrode). In this case, when an on potential is applied to the gate electrode, the surface electrode and the back electrode are conducted and current flows, and when no on potential is applied to the gate electrode, the surface electrode and the back electrode are not conducted and current does not flow. When a higher potential is applied to the back electrode than the front electrode, a forward voltage is applied to the diode built in the p-channel MOS, and current flows from the back electrode to the front electrode. Also in the above, the surface means the side on which the gate electrode is formed.
In the case of n-channel MOS, the back electrode (drain electrode) is referred to as the first electrode, the front electrode (source electrode) is referred to as the second electrode, and in the case of p-channel MOS, the back electrode (drain electrode) is referred to as the first electrode. Assuming that the surface electrode (source electrode) is the first electrode, both the n-channel MOS and the p-channel MOS have the gate electrode under the condition that a higher potential is applied to the first electrode than the second electrode. The conduction and non-conduction between the first electrode and the second electrode are switched by the potential, and a current flows from the second electrode to the first electrode under a condition in which a higher potential is applied to the second electrode than the first electrode.
The present invention has a semiconductor device of this type, that is, has both a switching function and a diode function, and conducts when a forward voltage is applied to the diode structure, and applies a reverse voltage to the diode structure. Relates to a semiconductor device in which a switching function acts.

In the case of a switching semiconductor device in which conduction and non-conduction between the first electrode and the second electrode are switched by the potential of the gate electrode, a high voltage is applied between the first electrode and the second electrode unless an on-voltage is applied to the gate electrode. Even if it is applied, a withstand voltage that does not break the insulation state between the first electrode and the second electrode is required.
Various techniques for improving the breakdown voltage have been proposed. Patent Document 1 discloses a structure in which a plurality of trench gates extend in parallel to each other. In this case, when no on-voltage is applied to the gate electrode, electric field concentration occurs near the bottom surface of the outermost trench gate. That is, if the voltage applied between the drain electrode and the source electrode is increased without applying the on-voltage to the trench gate electrode, the insulation is broken in the vicinity of the bottom surface of the outermost trench gate. Therefore, the technique of Patent Document 1 proposes a structure in which the vicinity of the bottom surface of the outermost trench gate is covered with a p-type region. This semiconductor device is an n-channel MOS, and covers the vicinity of the bottom surface of the outermost trench gate in a region having the same conductivity type as the channel region.

JP 2009-16618 A

For example, under the condition that a higher potential is applied to the drain electrode than the source electrode, such as an n-channel MOS, conduction and non-conduction between the drain electrode and the source electrode are switched by the potential of the gate electrode (that is, a switching function is provided) In addition, when a semiconductor device in which a current flows from the source electrode to the drain electrode (that is, has a diode structure) under a condition in which a higher potential than the drain electrode is applied to the source electrode, the component used for the inverter circuit is used. The number can be reduced. This is because the diode structure incorporated in the semiconductor device for switching can be used for the freewheeling diode. There is no need to mount a diode separately from the semiconductor device for switching.
Similarly, the p-channel MOS switches the conduction and non-conduction between the source electrode and the drain electrode according to the potential of the gate electrode under the condition that the potential higher than the drain electrode is applied to the source electrode (that is, the switching function). In addition, even if a semiconductor device in which a current flows from the drain electrode to the source electrode (that is, has a diode structure) under a condition in which a higher potential than the source electrode is applied to the drain electrode, an inverter is used. The number of parts used in the circuit can be reduced. The diode structure incorporated in the semiconductor device for switching can be used as a freewheeling diode, and it is not necessary to mount a diode separately from the semiconductor device for switching.

  3 to 6 show an inverter circuit 11 configured by combining four switching semiconductor devices SW1 to SW4 and four diodes Dp1 to Dp4. The inverter circuit 11 is a circuit that generates single-phase AC power from a DC power supply, and is used by connecting to the DC power supply 12 and the inductive load L.

In the case of FIG. 3, n-channel switching semiconductor devices SW <b> 1 to SW <b> 4 are used, and the drains of the switching semiconductor devices SW <b> 1 and SW <b> 3 are connected to the high voltage side terminal of the DC power supply 12. The sources of the switching semiconductor devices SW2 and SW4 are connected to the low voltage side terminal of the DC power supply 12. The source of the switching semiconductor device SW1 and the drain of the switching semiconductor device SW2 are connected to one terminal of the inductive load L via the connection point J1. The source of the switching semiconductor device SW3 and the drain of the switching semiconductor device SW4 are connected to the other terminal of the inductive load L via the connection point J2.
The diode Dp1 is connected in parallel to the switching semiconductor device SW1. The diode Dp1 is connected in a direction in which a current flows through the diode Dp1 when a voltage higher than that of the drain is applied to the source of the switching semiconductor device SW1. The relationship between the other diodes Dp2 to Dp4 and the switching semiconductor devices SW2 to SW4 is the same.

  FIG. 3 is an explanatory diagram showing the operation of the inverter circuit 11 in the first state. FIG. 5 is an explanatory diagram showing a state of operation of the inverter circuit 11 in the second state. The inverter circuit 11 can convert DC power into AC power by alternately switching between the first state and the second state. The first state is a state in which the switching semiconductor device SW1 and the switching semiconductor device SW4 are on, and the switching semiconductor device SW2 and the switching semiconductor device SW3 are off. In the inverter circuit 11 in the first state, the current flowing out from the positive electrode of the DC power source 12 includes the switching semiconductor device SW1 in the on state, the connection point J1, the inductive load L, the connection point J2, and the on state. It returns to the negative electrode of the DC power supply 12 via the switching semiconductor device SW4.

  FIG. 4 shows how the inverter circuit 11 operates in the first transition state. In the first transition state, the switching semiconductor device SW2 and the switching semiconductor device SW3 are maintained in the off state, and the switching semiconductor device SW1 and the switching semiconductor device SW4 are turned off. The reason why the transition state in which all of the four switching semiconductor devices SW1 to SW4 are turned off is sandwiched between the first state and the second state is to prevent the inverter circuit 11 from being short-circuited. is there.

  In the first transition state, an electromotive force that maintains the current flowing through the inductive load L is generated by the inductance of the inductive load L. Due to the electromotive force, a reflux current is returned from the inductive load L to the inductive load L via the connection point J2, the forward diode Dp3, the DC power supply 12, the forward diode Dp2, and the connection point J1. Flowing. The DC power supply 12 is charged by the reflux current. Moreover, since the diode Dp3 and the diode Dp2 are inserted in the direction in which the circulating current flows, an excessive voltage is not applied to the switching semiconductor devices SW1 to SW4.

  Without the free-wheeling diodes Dp1 to Dp4, an excessive voltage is applied to the switching semiconductor devices SW1 to SW4 when the switching semiconductor devices SW1 to SW4 are turned off. When the semiconductor device 10 having both a diode and a switching function is used, it is not necessary to mount a diode in addition to the switching semiconductor device. When the semiconductor device 10 having both a diode and a switching function is used, the inverter circuit 11 can be realized with a small number of components.

  FIG. 5 is an explanatory diagram showing a state of operation of the inverter circuit 11 in the second state. In the second state, the switching semiconductor device SW1 and the switching semiconductor device SW4 are maintained in the off state, and the switching semiconductor device SW2 and the switching semiconductor device SW3 are turned on. In the inverter circuit 11 in the second state, the current flowing out from the positive electrode of the DC power source 12 includes the switching semiconductor device SW3 in the on state, the connection point J2, the inductive load L, the connection point J1, and the on state. It returns to the negative electrode of the DC power supply 12 via the switching semiconductor device SW2.

  FIG. 6 shows a state immediately after switching from the state of FIG. 4 to the state of FIG. In this state, the reverse voltage is applied to the diodes Dp2 and Dp3 to which the forward voltage was applied before (see FIG. 4). As a result, the carriers accumulated in the semiconductor region are extracted while the forward current is flowing, and a current (recovery current) in the opposite direction flows. The recovery current flows when holes are extracted to the source electrode.

  FIG. 7 is a diagram illustrating the magnitude of the current flowing through the diode Dp of the semiconductor device 10. The on state in FIG. 7 shows a state in which a forward current flows through the diode Dp, for example, as shown in FIG. Timing t0 indicates the timing when the state shown in FIG. 4 is switched to the state shown in FIG. After that, the current value flowing in the forward direction through the diode Dp decreases, and the current flowing through the diode Dp becomes zero at the timing t1. After timing t1, current starts to flow in the reverse direction, and the current value increases. The reverse current flowing after timing t1 is referred to as a recovery current. If the semiconductor device 10 operates normally, the recovery current will eventually decrease and eventually settle to zero. However, the recovery current continues to increase, and the semiconductor device 10 may be destroyed.

  As described above, Patent Document 1 discloses a technique for improving the breakdown voltage of a switching semiconductor device. However, the conventional withstand voltage improvement technique is a technique for increasing the maximum voltage that can maintain an insulating state between the drain electrode and the source electrode without applying an on-voltage to the gate electrode, and an excessive recovery current flows in the semiconductor device. This does not prevent the semiconductor device from being destroyed by an excessive recovery current.

  The present invention was created to solve the above-described problems, and prevents an excessive recovery current from flowing when a diode structure built in a semiconductor device is used as a free-wheeling diode. In addition, a technique for preventing the semiconductor device from being destroyed by an excessive recovery current is provided.

In order to create the present invention, the inventors have studied the cause of excessive recovery current flowing when an existing semiconductor device is used. As a result, it has been found that the greatest problem is outside the longitudinal end of the trench gate electrode.
2 and FIG. 8 are perspective views of the vicinity of the end portion in the longitudinal direction of the trench gate electrode of an existing switching semiconductor device having a diode structure. In FIG. 8, the channel region 23 is transparent for clarity. In both FIG. 2 and FIG. 8, the source electrode and the gate electrode are not shown. In FIG. 8, the trench gate region 21 and the conductive film FP ₀ are separated for clarity of illustration, but as shown in FIG. 2, both are integrally formed of polysilicon or the like. . The conductive film FPo is a wiring that connects the trench gate region 21 and the gate electrode pad (see G in FIG. 1), and also functions as a field plate.

In FIG. 8, reference numeral 802 denotes a drain electrode, which is formed on the back surface of the n-type semiconductor substrate 810. Reference numeral 32 denotes an n ⁺ -type drain region which is formed in a range facing the back surface of the n-type semiconductor substrate 810 and is electrically connected to the drain electrode 802. The transparent region 23 is a p ^- type channel region, and is formed in the central portion of the region facing the surface of the semiconductor substrate 810. Reference number RSo is a p ⁻⁻ type RESURF region, and is formed in a peripheral portion (range that goes around the outside of the channel region 23) in the range facing the surface of the semiconductor substrate 810. A region of the n-type semiconductor substrate 810 that is not the drain region 32, the channel region 23, or the RESURF region RSo is an n ⁻ -type drift region. N-type semiconductor regions 31 and 32 exist on the back side of the n-type semiconductor substrate 810, that is, on the back side of the channel region 23 and the RESURF region RSo.

820 is a plurality of trenches extending from the surface of the semiconductor substrate 810 and reaching the drift region 31 through the channel region 23. Reference numeral 22 denotes a gate insulating film covering the wall surface of the trench 820, and reference numeral 21 denotes a conductive gate region accommodated in the trench 820 while being covered with the gate insulating film 22. Reference numeral 25 is an n ⁺ type source region formed in a range in contact with the trench 820 and facing the surface of the channel region 23, and is electrically connected to a source electrode (not shown). The source electrode is insulated from the gate region 21 by an insulating film (not shown) and is electrically connected to the p-type channel region 23 and the n-type source region 25. In order to ensure conduction between the source electrode and the p ⁻ type channel region 23, a p ⁺ type channel contact region 24 is formed. Gate region 21 is electrically connected to the gate electrode pad (not shown) by conductive FP ₀ (G in Figure 1). The conductive film FP ₀ is insulated from the RESURF region RSo and the channel region 23 by an insulating film (not shown).

The impurity concentration of the p ⁻ type channel region 23 is higher than the impurity concentration of the p ⁻ type resurf region RSo. The plurality of trenches 820 are arranged in parallel to each other, and the end portions in the longitudinal direction of the plurality of trenches are aligned on the same straight line 822. A straight line 822 in which ends in the longitudinal direction of the plurality of trenches 820 are aligned is located on the peripheral side of the boundary line 824 between the p-type channel region 23 and the p-type RESURF region RSo. That is, the end of the trench 820 in the longitudinal direction penetrates into the p-type RESURF region RSo.

  FIG. 9 shows a circuit configuration obtained by analyzing the recovery current. Lw shown shows the parasitic inductance component of circuit wiring. Illustration L shows an inductive load. The illustrated SW corresponds to a switch portion of the semiconductor device for switching. Here, in order to realize a circuit equivalent to a circuit in which a semiconductor device for switching and a diode are connected in parallel, a switch that flows bidirectionally when conducting is used. If the switch flows in both directions, even if it is connected in series with a diode, it operates in the same way as a circuit in which a switching semiconductor device and a diode device are connected in parallel. Dpc in the figure shows a diode composed of an n-type semiconductor substrate 810 and a p-type channel region 23, and Dpp in the figure shows a diode composed of an n-type semiconductor substrate 810 and a p-type RESURF region RSo. In the two diode structures, Dpc and Dpp are connected in parallel.

The circuit of FIG. 9 simulates the following operation. When the switch portion of the switching semiconductor device SW is turned on, a current flows through the inductive load L. Next, when the switching unit of the switching semiconductor device SW is turned off, a voltage is generated by the inductance of the inductive load L, and a forward current flows through the parasitic diodes Dpc and Dpp existing in the switching semiconductor device. As a result, carriers are accumulated in the two parasitic diodes Dpc and Dpp. After that, when the switching unit of the switching semiconductor device SW is turned on again, the carriers accumulated in the parasitic diodes Dpc and Dpp are discharged in the opposite direction, and the recovery current is supplied to the two parasitic diodes Dpc and Dpp. I _R flows.

(A) of FIG. 10, n-type semiconductor substrate 810 and the p-type RESURF region indicates recovery current _{I RP} through the formed diode Dpp in RSo, (b) in FIG. 10, n-type semiconductor substrate 810 and the p-type It shows the recovery current _{I RC} through the formed diode Dpc in the channel region 23. The illustrated arrow indicates the timing at which the switching semiconductor device SW starts to be destroyed by the recovery current. The results of the study, in an existing semiconductor device, be n-type semiconductor substrate 810 and the p-type RESURF region recovery current flowing through the formed diode Dpc in RSo I _RP switching semiconductor device SW to become excessive is destroyed found.

FIG. 11 is an explanatory diagram showing a range U to be analyzed of an existing switching semiconductor device. The range U is a range including a place where occurrence of recovery destruction is assumed. Recovery current _{I R} (hole current), in the range U, the impurity concentration of approximately ¹⁰ 16 ^{cm -3 p -} RESURF region impurity concentration from RS ₀ is about ¹⁰ 17 ^{cm -3 P} _- a _ch channel region 23 It flows through the P ⁺ channel contact region 24 having an impurity concentration of about 10 ¹⁹ cm ⁻³ . Thus, in the path of the recovery current I _R, p ^- since the impurity concentration of the RESURF region RS ₀ is the smallest, wherein the resulting potential distribution, a large electric field is found to be likely to occur.

12 to 14 show the results of analyzing the phenomenon that occurs in the switching semiconductor device SW when the circuit of FIG. 9 is configured using the existing switching semiconductor device SW shown in FIGS. 2, 8, and 11. Show. 12 to 14, (a) shows the electric field distribution Fd _0S1 generated in the switching semiconductor device SW, (b) shows the hole current distribution Hd _0S1 , and (c) shows the impact ionization distribution Id _0S1. Yes.
12 shows the analysis result at the depth S1 in FIG. 8, FIG. 13 shows the analysis result at the depth S2, and FIG. 14 shows the analysis result at the depth S3.

As can be seen from the electric field distribution Fd _{0S1 in} FIG. 12A, in the vicinity of the surface of the semiconductor substrate 810, the electric field concentration portion A is formed in the p ⁻⁻ resurf region Rso near the outside of the corner GC at the longitudinal end portion of the trench gate 21. There ^{occurs, p -} RESURF region RS ₀ and ^P _{- ch} is the boundary of the channel region 23 ^P _- ^{/ P} - electric field concentration B occurs _ch boundary.

As can be seen from the hole current distribution Hd _{0S1 in} FIG. _12B , the hole current concentrates on the electric field concentration portion A near the outside corner GC at the end portion in the longitudinal direction of the trench gate 21, and P ⁻ / It is dispersed toward the P ^- _ch boundary. The hole current is concentrated in the electric field concentration portion A because the holes accumulated in the p ⁻⁻ resurf region RS ₀ located in the range outside the longitudinal end portion of the trench gate 21 are in the field. This is because the flow tends to flow along the trench gate 21 after flowing along the plate FPo. The recovery current ^P - ^{/ P} _- to disperse toward the _ch ^boundary, P - because _ch to the channel region 23 is the recovery current is sucked _- ^{/ P} _- from _ch boundary ^P.

Impact ionization is a phenomenon in which, when a high electric field is applied to a semiconductor, carriers collide with atoms constituting the semiconductor and ionize them, and at the same time create a plurality of carriers. In this chain reaction, if positive feedback is applied, avalanche breakdown occurs, leading to destruction. The impact ionization distribution Id _0S1 becomes more severe as the product of the electric field strength and the hole current density is larger. As can be seen from the impact ionization distribution Id _{0S1 in} FIG. _12C , severe impact ionization occurs in the electric field concentration portion A near the outside corner GC at the longitudinal end of the trench gate 21. This is because the electric field concentration portion A is a region where the electric field concentrates and the hole current concentrates.

FIG. 13 is an explanatory diagram showing an analysis result at the depth S2 of FIG. The electric field has substantially the same distribution as the electric field distribution _Fd0S1 at the depth S1. On the other hand, as can be seen from the hole current distribution _Hd0S2 in FIG. 13B, the concentration of the recovery current is small in the hole current. Thus, the degree of concentration of the recovery current is reduced is because apart from the field plate FP ₀ than the depth S1 towards the depth S2. Since the field plate FP ₀ is at the ground potential, the hole current is attracted to the vicinity of the field plate, and the concentration of the hole current at the depth S1 is increased.

As can be seen from the impact ionization distribution Id _{0S2 in} FIG. 13C, impact ionization occurs in the electric field concentration portion A near the outside of the corner GC at the end of the trench gate 21. However, since the concentration of the hole current is small, the degree of avalanche breakdown (avalanche breakdown) is reduced.

FIG. 14 is an explanatory diagram showing an analysis result at the depth S3 in FIG. At the depth S3, since it approaches the n ⁻ type drift region 31, a strong electric field region is generated at the boundary between the P ⁻ _ch channel region 23 and the N ⁺ source region 25 or in the vicinity of the P ⁻ / P ⁻ _ch boundary. On the other hand, the hole current flows along the trench gate 21 as can be seen from the hole current distribution _Hd0S3, but the degree of concentration is further reduced. Thus, at the depth S3, the path of the hole current and the position of the strong electric field region are different from each other. Therefore, although a collision ionization occurs in the vicinity of the corner GC at the end of the trench gate 21, an avalanche breakdown occurs. Not.

As described above, in the existing semiconductor device 10, in the p ⁻⁻ resurf region RS ₀ where current is relatively difficult to flow and a strong electric field is likely to be generated, the hole current concentration and the electric field concentration overlap with each other ( Since the electric field concentration portion A) exists, it has been found that an avalanche breakdown that causes the semiconductor device to break down is likely to occur at the concentration portion.

  The present invention was created based on the above analysis, and provides a semiconductor structure that prevents the occurrence of avalanche breakdown by preventing the location where the hole current is concentrated from the location where the electric field strength is increased. To do.

  In the above description, the term “existing semiconductor device 10” is used. This means a known technique recognized by the inventor and does not mean a conventional technique defined by the Patent Law. The technology known at the research site may not be the conventional technology defined by the Patent Law. Even if it is existing, it does not admit that it is a prior art defined by the law.

The semiconductor device disclosed in the present specification is formed at the central portion of the first conductivity type drain region formed in a range facing the back surface of the semiconductor substrate and the range facing the surface of the semiconductor substrate. The second conductivity type channel region, the second conductivity type RESURF region formed in the peripheral portion of the range facing the surface of the semiconductor substrate, and the first region formed within the range facing the surface of the channel region. A plurality of conductive type source regions and a plurality of first conductive type semiconductor regions extending from the surface of the semiconductor substrate at positions adjacent to the source region, penetrating through the channel region and existing on the back side of the semiconductor substrate; A trench, a gate insulating film covering the wall of the trench, a conductive gate region covered with the gate insulating film, and a drain conducting to the drain region An electrode, a source electrode electrically connected to the channel region and the source region and insulated from the gate region, an insulating film covering the surface of the RESURF region, and an electrically conductive material to the gate region and on the surface of the insulating film And a formed conductive film.
The plurality of trenches are arranged in parallel to each other, the longitudinal ends of the plurality of trenches are aligned on the same straight line, and the impurity concentration of the channel region is higher than the impurity concentration of the RESURF region. In addition, at least a part of the channel region protrudes to the peripheral side of the semiconductor substrate from the straight line (a straight line in which ends in the longitudinal direction of the trench are aligned) between the pitches of a pair of adjacent trenches.

In the case of an n-channel semiconductor device, the first conductivity type is n and the second conductivity type is p. In the case of an n-channel semiconductor device, when a higher potential is applied to the n-type drain region than the n-type source region, the gate region is insulated from the state in which the drain region and the source region are conducted by the potential of the gate region. Is switched. When a higher potential is applied to the p-type channel region than to the n-type drain region, a current flows from the channel region to the drain region. This semiconductor device includes a switch portion and a diode portion. When an inverter circuit is configured using this semiconductor device, it is not necessary to prepare a free-wheeling diode in addition to the switching semiconductor device.
In the case of a p-channel semiconductor device, the first conductivity type is p and the second conductivity type is n. In the case of a p-channel type semiconductor device, when a higher potential is applied to the p-type source region than the p-type drain region, the source region and the drain region are insulated from the conductive state by the potential of the gate region. Is switched. When a higher potential is applied to the p-type drain region than the n-type channel region, a current flows from the drain region to the channel region. This semiconductor device includes a switch portion and a diode portion. When an inverter circuit is configured using this semiconductor device, it is not necessary to prepare a free-wheeling diode in addition to the switching semiconductor device.

  When a recovery current flows through a diode composed of a deep region and a resurf region of the semiconductor substrate, carriers move from the resurf region to the channel region. In the existing semiconductor device, carriers moving in the RESURF region toward the channel region are concentrated in the vicinity of the outside of the corner at the end in the longitudinal direction of the trench gate. Since this carrier concentration portion is also an electric field concentration portion, an avalanche breakdown is likely to occur when a recovery current flows in an existing semiconductor device.

In the semiconductor device of the present invention, at least a part of the channel region protrudes to the peripheral side between the pitches of a pair of adjacent trenches rather than the straight line in which the ends in the longitudinal direction of the plurality of trenches are aligned. In this case, before the carriers are concentrated near the outside of the corner at the end portion in the longitudinal direction of the trench gate, the carriers flow into the channel region protruding to the peripheral side. As a result, carriers are not concentrated near the outside of the corner at the longitudinal end of the trench gate. As a result, according to the semiconductor device of the present invention, the carrier concentration portion and the electric field concentration portion do not overlap, and the occurrence of avalanche breakdown is suppressed.
The conductive film connected to the gate region may also serve as a field plate. Alternatively, a field plate may be formed in addition to the conductive film conducting to the gate region.

  In the semiconductor device described above, at least a part of the channel region only has to protrude beyond the straight line where the end portions in the longitudinal direction of the plurality of trenches are aligned between the pitches of a pair of adjacent trenches. One example is a pattern in which the boundary line between the channel region and the RESURF region is a straight line, and the straight line is located on the peripheral side of the straight line where the longitudinal ends of the plurality of trenches are aligned. can do.

On the other hand, between the pitches of a pair of adjacent trenches, a part of the channel region may be drawn to the center side from the straight line where the end portions in the longitudinal direction of the plurality of trenches are aligned.
For example, a comb in which the boundary line between the channel region and the RESURF region is displaced more to the peripheral side than the straight line at a portion away from the trench between adjacent trenches, and to the center side from the straight line at a portion in contact with the trench. It may be tooth-shaped.

  In this case, it is preferable that the pattern of the boundary line between the channel region and the RESURF region matches the pattern of the conductive film that is conducted to the gate region.

  When the pattern of the boundary line between the channel region and the RESURF region matches the pattern of the conductive film conducting to the gate region, the channel region formation range is regulated by regulating the implantation range of the second conductivity type impurity. A common mask can be used as a mask and a mask that restricts the formation range of a conductive film (which may or may not be used as a field plate) that is conductive to the gate region. .

The semiconductor device of the present invention has both a switching structure and a diode structure, and can form an inverter circuit with a small number of components. In the semiconductor device of the present invention, when the recovery current flows through the diode structure, the carrier concentration portion and the electric field concentration portion do not overlap with each other, and the occurrence of avalanche breakdown that causes destruction of the semiconductor device can be suppressed. it can.
In addition, the boundary between the channel region and the RESURF region is displaced more to the peripheral side than the straight line where the end portions in the longitudinal direction of the trench are aligned in the portion away from the trench, and the end portion in the longitudinal direction of the trench in the portion in contact with the trench If the shape of the comb teeth is displaced to the center side of the straight line, the pattern of the boundary line between the channel region and the RESURF region and the pattern of the conductive film conducting to the gate region can be matched, A mask for forming a channel region and a mask for forming a gate wiring can be used together. The manufacturing process of the semiconductor device is simplified.

The outline of the top view of the existing semiconductor device 10 is shown. FIG. 3 is an enlarged cross-sectional view showing a part (region Z) of the structure of an existing semiconductor device 10. Explanatory drawing which shows the mode of the action | operation of the inverter circuit 11 in a 1st state. Explanatory drawing which shows the mode of operation | movement of the inverter circuit 11 in a 1st transition state. Explanatory drawing which shows the mode of operation | movement of the inverter circuit 11 in a 2nd state. Explanatory drawing which shows the mode of operation | movement of the inverter circuit 11 in a 2nd transition state. The figure which shows the recovery current which flows into the parasitic diode of the existing semiconductor device 10 by contrast at the time of normal time and destruction. FIG. 3 is an internal perspective view showing a state where a channel region is transmitted in the vicinity of a peripheral region of an existing semiconductor device 10. The wiring diagram which shows the equivalent circuit containing the semiconductor device for switching used for the analysis, and an external circuit. The figure which shows the recovery current which flows into the parasitic diode of the existing semiconductor device 10 divided into a center part and a peripheral part. (A) is a recovery current flowing through the central portion, and (b) is a recovery current flowing through the peripheral portion. 4 is an explanatory diagram showing an analysis target range U of an existing semiconductor device 10. FIG. Explanatory drawing which shows the analysis result in depth S1 (FIG. 8) of the existing semiconductor device 10. FIG. Explanatory drawing which shows the analysis result in depth S2 (FIG. 8) of the existing semiconductor device 10. FIG. Explanatory drawing which shows the analysis result in depth S3 (FIG. 8) of the existing semiconductor device 10. FIG. The internal perspective view which shows the state which permeate | transmitted the channel group in the vicinity of peripheral region Ap of the semiconductor device 10a which concerns on 1st Example. Explanatory drawing which shows the analysis object range Ua of the semiconductor device 10a which concerns on 1st Example. Explanatory drawing which shows the analysis result in cross section S1 (FIG. 15) of the semiconductor device 10a which concerns on 1st Example. Explanatory drawing which shows the analysis result in cross section S2 (FIG. 15) of the semiconductor device 10a which concerns on 1st Example. Explanatory drawing which shows the analysis result in cross section S3 (FIG. 15) of the semiconductor device 10a which concerns on 1st Example. The flowchart which shows the content of the manufacturing method of the semiconductor device 10a which concerns on 1st Example. Explanatory view showing a region forming step ^{- p} of the semiconductor device 10a of the first embodiment. Explanatory drawing which shows the LOCOS oxidation process of the semiconductor device 10a of 1st Example. Explanatory drawing which shows the P ^- ch area | region formation process of the semiconductor device 10a of 1st Example. Explanatory drawing which shows the trench etching process of the semiconductor device 10a of 1st Example. Explanatory drawing which shows the gate insulating-film formation process of the semiconductor device 10a of 1st Example. The flowchart which shows the content of the trench gate formation process (S700) of the semiconductor device 10a of 1st Example. Sectional drawing in a trench formation site. Sectional drawing in the site | part in which the trench is not formed. Explanatory drawing which shows the P ⁺ area | region formation process of the semiconductor device 10a of 1st Example. Explanatory drawing which shows the source electrode formation process of the semiconductor device 10a of 1st Example. The internal perspective view which shows the state which permeate | transmitted the channel group in the vicinity of peripheral region Ap of the semiconductor device 10b which concerns on 2nd Example. Explanatory drawing which shows the analysis object range Ub of the semiconductor device 10b of 2nd Example. Explanatory drawing which shows the analysis result in cross section S1 (FIG. 31) of the semiconductor device 10b of 2nd Example. Explanatory drawing which shows the analysis result in cross section S2 (FIG. 31) of the semiconductor device 10b of 2nd Example. Explanatory drawing which shows the analysis result in cross section S3 (FIG. 31) of the semiconductor device 10b of 2nd Example. The flowchart which shows the content of the manufacturing method of the semiconductor device 10b of 2nd Example. The flowchart which shows the content of the trench gate formation process of the semiconductor device 10b of 2nd Example. Sectional drawing in a trench formation site. Sectional drawing in the site | part in which the trench is not formed. Explanatory drawing which shows the P < ^- > ch area | region formation process of the semiconductor device 10b of 2nd Example.

This invention can also implement | achieve a preferable form, for example by providing the following characteristics individually or in combination.
(Characteristic 1) It has a planar shape in which the channel region and the field plate fit each other.
(Feature 2) A channel region is formed by performing an ion implantation process using a mask that controls the field plate formation range by etching.
(Characteristic 3) The planar shape which fits mutually is a comb-tooth shape.
(Characteristic 3) The semiconductor device is both a semiconductor device for switching and a diode.
(Characteristic 4) A semiconductor device is used as a component of an inverter circuit. The inverter circuit is completed with a small number of parts in order to use both the switching semiconductor device and the diode.

In the following, embodiments of the present invention will be described in the following order in order to clearly describe the operation and effects of the present invention based on the above-described features.
A. Configuration and manufacturing method of semiconductor device according to first embodiment:
A-1. Configuration of the semiconductor device according to the first embodiment:
A-2. Method for manufacturing a semiconductor device according to the first embodiment:
B. Configuration and manufacturing method of semiconductor device according to second embodiment:
B-1. Configuration of a semiconductor device according to the second embodiment:
B-2. Manufacturing method of semiconductor device according to second embodiment:
C. Variations:

A. Configuration and manufacturing method of semiconductor device according to first embodiment:
The inventors of the present application have found that if a semiconductor device in which a hole current concentration portion when a recovery current flows and a portion having a high electric field strength do not overlap each other is configured, resistance to recovery breakdown can be increased. The inventor of the present application has created the semiconductor device according to the first embodiment based on such a discovery.

A-1. Configuration of a semiconductor device according to the first embodiment of the present invention:
FIG. 15 is an internal perspective view illustrating a state in which the channel group is transmitted in the vicinity of the peripheral region Ap of the semiconductor device 10a according to the first example. As can be seen from this figure, the P ^- _ch channel region 23 a is formed to the further peripheral side of the end portion 21 e in the longitudinal direction of the trench gate 21. That is, when the straight line 150 in which the end portions in the longitudinal direction of the plurality of trenches 21 are aligned and the boundary line 151 of the P ⁻ _ch channel region 23 a and the p ⁻⁻ resurf region RS ₁ are compared, the boundary line 151 is straighter. It is displaced toward the peripheral side of the semiconductor substrate from 150. Thus, in the semiconductor device 10a of the first embodiment, the longitudinal ends 21e of the high electric field strength is likely to occur trench gate ^{21, p -} consists RESURF region RS ₁ to leave a distance _{P 1.} The distance P ₁ is, that a marked effect in 1μm was confirmed in the experiments with the simulation by the present inventors.

FIG. 16 is an explanatory diagram showing the analysis target range Ua of the switching vertical semiconductor device 10a of the first embodiment. In the range Ua, the recovery current I R (hole current) reaches the P − ch channel region 23 a before reaching the vicinity of the trench gate 21 from the p − −resurf region RS 1 . In the first embodiment, the ends 21e of the trench gate 21 is p - RESURF is away from the region RS 1 by a distance P 1, P - ch channel region 23a is in the peripheral region Ap from the end portion 21e of the trench gate 21 This is because it extends to the side.

FIG. 17 is an explanatory diagram illustrating an analysis result in the cross section S1 (FIG. 15) of the vertical semiconductor device for switching 10a according to the first embodiment. As it can be seen from the field distribution _{Fd 1S1} of (a), the electric field ^intensity, P - higher in _ch boundary _- ^{/ P.} As can be seen from the hole current distribution Hd _1S1 of (b), the hole current without concentrating in the vicinity of the trench gate 21, P ^- ch flowing distributed a wide range of channel region 23a. P ^- ch channel region 23a ^{is, p -} since many amount of impurities than RESURF region RS _1, without being sucked to the trench gate 21, because flows on average a wide range.

As can be seen from impact ionization distribution _{Id 1S1} of (c), impact ionization, ^P strong electric field intensity is generated - is occurring at _ch boundary _- ^{/ P.} However, since the concentration of the hole current is reduced, the degree of impact ionization is reduced.

FIG. 18 is an explanatory diagram illustrating an analysis result in the cross section S2 (FIG. 15) of the vertical semiconductor device for switching 10a according to the first embodiment. In the cross section S2, the strong electric field region is expanded more than the electric field distribution Fd _1S1 in the cross section S1. On the other hand, the hole current does not concentrate in the vicinity of the trench gate 21 and flows through the P ^- ch channel region 23a on the average, similarly to the hole current distribution _Hd1S1 in the cross section S1. As can be seen from the impact ionization distribution _Id1S2 , the impact ionization is reduced in the same manner as the impact ionization in the cross section S1 because the concentration of the hole current is small.

FIG. 19 is an explanatory diagram showing an analysis result in the cross section S3 (FIG. 15) of the switching vertical semiconductor device 10a of the first embodiment. In the cross section S3, the strong electric field region is further expanded from the electric field distribution _Fd1S1 in the cross section S1. This is due to the influence of the electric field generated at the boundary between the P ⁻ ch channel region 23 a and the N ⁻ semiconductor lower layer 31. On the other hand, since the hole current is away from the field plate FP _{1 in the} vertical direction (Z-axis direction), it hardly flows. As can be seen from the impact ionization distribution Id _{1S3 in} (c), since the hole current hardly flows, the impact ionization hardly occurs.

  As described above, the semiconductor device 10a according to the first embodiment can suppress the avalanche breakdown generated by the synergistic effect of the electric field concentration and the carrier concentration in the vicinity of the end portion in the longitudinal direction of the trench gate 21. As a result, an excessive recovery current does not flow through the diode formed parasitically inside the semiconductor device 10a, and it is possible to suppress the destruction by the excessive recovery current.

A-2. Method of manufacturing a semiconductor device according to the first embodiment of the present invention:
FIG. 20 is a flowchart showing the contents of the manufacturing method of the semiconductor device 10a according to the first embodiment of the present invention. In step S100, a semiconductor substrate is prepared. An N ⁻ layer and an N ⁺ drain layer 32 are formed on the prepared semiconductor substrate.

FIG. 21 is an explanatory diagram illustrating a p ⁻⁻ region forming process in the manufacturing process of the semiconductor device 10a according to the first embodiment. In step S200, a p ⁻⁻ region forming process is performed. The p ⁻⁻ region forming step is a step of forming a p ⁻⁻ resurf region RS ₁ that functions as a RESURF region in the peripheral region Ap of the semiconductor device 10. The p ⁻⁻ region forming process includes a mask process, an ion implantation process, and a thermal diffusion process. The ion implantation step is a step of implanting acceptors, which are impurities for producing a P-type semiconductor, as ions. The thermal diffusion process is a process of thermally diffusing the implanted ions.

FIG. 22 is an explanatory view showing the state of the LOCOS oxidation process. In step S300, a LOCOS (Local Oxidation of Silicon) oxidation process is performed. In the present embodiment, the LOCOS insulating film 41 is formed by partially oxidizing the surfaces of the p ⁻⁻ resurf region RS ₁ and the N ⁻ semiconductor lower layer 31.

FIG. 23 is an explanatory diagram showing a state of the P ^- _ch region forming step. In step S400, a P-ch region forming process is performed. In the P-ch region forming step, a mask M2 is formed, and a region to be the P ⁻ ch channel region 23a is formed by the same step as the p ⁻⁻ region forming step.

  FIG. 24 is an explanatory view showing the state of the trench etching process. In step S500, a trench etching process is performed. In the trench etching process, a trench for forming the trench gate 21 is formed by etching. This process can be realized by deep RIE (Deep RIE), which is reactive ion etching having a high aspect ratio (narrow and deep), for example.

  FIG. 25 is an explanatory diagram showing the state of the gate oxidation process. In step S600, a gate oxidation process is performed. In the gate oxidation process, an oxide film is formed on the entire surface of the semiconductor including the wall surface and bottom surface of the trench formed in the trench etching process.

  FIG. 26 is a flowchart showing the contents of the trench gate formation step (S700). The trench gate formation process (S700) includes a polysilicon CVD process (S710), a polysilicon CVD process (S710), a mask formation process (S720), and a polysilicon etching process (S730).

27 and 28 are cross-sectional views showing the state of the trench gate forming step (see FIG. 16 for the cross-sectional position). FIG. 27 is a cross-sectional view at a position where the trench gate 21 exists. FIG. 28 is a cross-sectional view at a position where a P ^- ch channel region 23a exists between adjacent trench gates.

In the polysilicon CVD process (S710), by chemical vapor deposition, to form a conductive material layer of polysilicon, a step of integrally forming the field plate FP ₀ and the trench gate 21. The field plate FP ₀ also serves as a wiring for conducting the trench gate 21 and the gate electrode pad (G in FIG. 1). Mask forming step (S720) is a step of forming a mask covering a range to leave the trench gate 21 and field plate FP _0. Polysilicon etching step (S730), the polysilicon is not covered with the mask is etched, a step of forming the outer shape of the trench gate 21 and field plate FP _0. Note that the outer shape of the field plate FP ₀ is simplified in the perspective view of FIG. 15 and the like for easy understanding of the description.

FIG. 29 is an explanatory diagram showing the P ⁺ region forming step (S800). In step S800, a P ⁺ region forming process is performed. P ⁺ region formation step, a mask ^{M3, p -} region forming step and ^P - by ch channel region 23a similar step is a step of forming a ^{P +} channel contact region 24.

FIG. 30 is an explanatory diagram showing the contents of the source electrode formation step (S900). In step S900, a source electrode is formed. This process includes an interlayer insulating film CVD process, a contact hole etching process, an aluminum deposition process, and an aluminum electrode etching process. By the source electrode forming step, the P ⁺ channel contact region 24 and the N ⁺ source region 25 are electrically connected to the source terminal electrode.

The contents of each process are as follows. Interlayer insulating film CVD step is a step of forming an interlayer insulating film B with an interlayer insulating film CVD in order to secure insulation between the trench gate 21 and field plate FP _0. In the contact hole etching step, the oxide film formed in the gate oxidation step and the interlayer insulating film B are partially removed to form holes in order to expose the P ⁺ channel contact region 24 and the N ⁺ source region 25. It is. The aluminum deposition step is a step of depositing aluminum by a method such as vapor deposition. The aluminum electrode etching step is a step of forming the outer shape of the aluminum electrode by etching.

  By completing such steps, the semiconductor device 10a of the first embodiment of the present invention can be manufactured. Note that the source electrode S and the interlayer insulating film B are omitted in FIG. 16 and the like for the sake of simplicity.

B. Configuration and manufacturing method of semiconductor device according to second embodiment of the present invention:
The inventor of the present application examines the contents of the above-described configuration and the manufacturing method, and thus can achieve efficient manufacturing without excessively reducing the characteristics of the semiconductor device 10a of the first embodiment. We succeeded in creating a method.

B-1. Configuration of a semiconductor device according to the second embodiment of the present invention:
FIG. 31 is an internal perspective view showing a state where the channel region 23b is transmitted in the vicinity of the peripheral region Ap of the semiconductor device 10b according to the second embodiment of the present invention. The semiconductor device 10b of the second embodiment, in a plan view of the semiconductor device, i.e., when viewed in the Z-axis direction, P ^- _ch channel region 23b and the field plate FP ₂ and the (in the trench conductor, the gate The conductive film for conducting the electrode pad) has a planar shape that fits to each other. Such fitting shape, as described later, using the mask for forming the outer shape of the field plate FP ₂ P ^- can be realized by forming a _ch channel region 23b, simplification of the manufacturing process Can be realized.

FIG. 32 is an explanatory diagram showing an analysis target range Ub of the vertical semiconductor device for switching 10b according to the second embodiment. Figure ^{320, P} _- a RESURF region RS ₂ of the boundary line, the center side than the boundary line 320 (left side) ^P _- ^- _ch channel region 23b and ^p are _ch channel region 23b, the peripheral side (right side ) is ^{p -} a RESURF region RS _2. The pattern on the center side of the field plate FP ₂ that is also a conductive film that conducts the conductor (trench gate region) 21 inside the trench and the gate electrode pad G coincides with the boundary line 320. That is, the pattern on the center side of the p ⁻⁻ RESURF region RS ₂ and the field plate FP ₂ overlaps, and the center side is the P ⁻ _ch channel region 23b.

The field plate FP _{2, which} is also a conductive film that conducts the trench gate region 21 and the gate electrode pad G, in a range in contact with the trench gate region 21 at a pitch p between a pair of adjacent trench gate regions 21, It protrudes toward the center side (left side) from the straight line 322 in which the ends in the longitudinal direction are aligned. In a plan view, both are conductive to the extent that overlap trench gate region 21 and the field plate FP _2. In the range p1 away from the trench gate region 21 at the pitch p, the P ^- _ch channel region 23b projects toward the peripheral side (right side) with respect to the straight line 322 where the longitudinal ends of the trench gate region 21 are aligned. ing. The P ^- _ch channel region 23b protrudes toward the peripheral side (right side) with respect to the straight line 322 where the end portions in the longitudinal direction of the trench gate region 21 are aligned at the pitch p between the pair of adjacent trench gate regions 21. It has a part.

The relationship of the planar shape, the recovery current _{I R} (hole ^{current), p -} the RESURF region RS ₂ before reaching the vicinity of the trench gate region ^{21, P} _- is found to be reached _ch channel region 23b . P ^- _ch channel region 23b is because has a longitudinal of the straight line 322 whose ends are aligned, the distance P ₂ only region protrudes toward the periphery side 23bp of the trench gate region 21. The distance P ₂ is that a marked effect in 3μm was confirmed in the experiments with the simulation by the present inventors.

FIG. 33 is an explanatory diagram showing an analysis result in a cross section S1 (see FIG. 31) of the vertical semiconductor device for switching according to the second embodiment. As can be seen from the field distribution Fd 2S1, P - ch portion 23bp overhanging the left of the straight line 322 and p of the channel region 23b - the boundary of the RESURF region RS 2, be strong electric field intensity is generated Recognize. As can be seen from the hole current distribution Hd 2 S 1 , the hole current does not concentrate in the vicinity of the trench gate 21 but flows into the P + channel contact region 24 via the P − ch channel region 23 b. As can be seen from impact ionization distribution Id 2S1, impact ionization phenomenon, p strong electric field intensity is generated - is occurring at ch boundary of the channel region 23b - RESURF region RS 2 and P. However, although the semiconductor device 10b of the second embodiment has a higher concentration of hole current than the semiconductor device 10a of the first embodiment, the concentration of hole current is higher than that of the existing semiconductor device 10. Since the degree is small, the degree of impact ionization is significantly smaller than that of the existing semiconductor device 10 although it is greater than that of the semiconductor device 10a of the first embodiment.

The degree of impact ionization in the semiconductor device 10b of the second embodiment is significantly smaller than that of the existing semiconductor device 10 because the degree of concentration of electric field strength and the degree of concentration of hole current are different. Specifically, when the semiconductor layer is viewed in plan, in the existing semiconductor device 10, the electric field intensity concentration portion and the hole current concentration portion are points (the electric field concentration portion in the vicinity of the corner GC at the end of the trench gate 21. while it is a), in the semiconductor device 10b of the second embodiment, concentration portions is a line ^(p field strength concentration portions and hole current ^- RESURF region RS ₂ and ^P _{- ch} channel region 23b of the borders) It is because it is distributed along.

The degree of impact ionization in the semiconductor device 10b of the second embodiment is larger than that of the semiconductor device 10a of the first embodiment because the degree of concentration of electric field strength and the degree of concentration of hole current are different. Specifically, when the semiconductor layer is viewed in plan, in the semiconductor device 10b of the second embodiment, a line (p ⁻⁻ RESURF region RS ₂ and This is because the length of the boundary line of the P ^- _ch channel region 23b is shorter than that of the semiconductor device 10a of the first embodiment.

  FIG. 34 is an explanatory view showing an analysis result in the cross section S2 (FIG. 31) of the switching semiconductor device of the second embodiment. Each distribution of the electric field, hole current, and impact ionization in the cross section S2 is almost the same as that in the cross section S1.

FIG. 35 is an explanatory view showing an analysis result in the cross section S3 (FIG. 31) of the switching semiconductor device of the second embodiment. The electric field in the cross section S3 has a stronger electric field region expanded than the electric field distribution Fd _2S1 in the cross section S1 and the electric field distribution Fd _{2S2 in the} cross section S2. This is the influence of the electric field generated at the boundary between the P ⁻ _ch channel region 23 b and the N ⁻ semiconductor lower layer 31, as in the first embodiment. On the other hand, since the hole current is separated from the field plate FP _{0 in the} vertical direction (Z-axis direction), almost no current flows. As for the impact ionization, as can be seen from the impact ionization distribution _Id2S3, almost no hole current flows, and therefore, impact ionization hardly occurs.

B-2. A method of manufacturing a semiconductor device according to the second embodiment of the present invention:
FIG. 36 is a flowchart showing the contents of the manufacturing method of the semiconductor device 10b according to the second embodiment of the present invention. Manufacturing method of the second embodiment are that P-ch region formation step (step S400) is omitted, the content is changed P trench gate forming step (S700) ^- comprising the step of forming a ch region It differs from the manufacturing method of the first embodiment in that it is a trench gate formation step (S700a).

FIG. 37 is a flowchart showing the contents of the trench gate formation step (S700a) according to the second embodiment of the present invention. In the trench gate formation process of the second embodiment, the mask formation region in the mask formation step (S720a) is changed, and an ion implantation step (S740) for forming a P ⁻ ch region is added. This is different from the trench gate formation step (S700) of the first embodiment.

38 and 39 are cross-sectional views showing the state of the trench gate formation process in the manufacture of the semiconductor device 10b of the second embodiment. FIG. 38 is a cross-sectional view at the position of the trench gate region 21. FIG. 39 is a cross-sectional view at a position between the pair of trench gate regions 21 where the P ^- _ch channel region 23b exists. As can be seen from these figures, the trench gate forming step (S700a), the outer shape of the field plate FP ₂ is the outer shape of the field plate FP ₂ is formed to have a comb-like shape.

In the mask forming step (S720a) in the second embodiment, in a plan view of the semiconductor layer, the outer shape of the field plate FP ₂ is applied with the photomask M4 so that the mask shape such that comb teeth shape . The planar shape of the mask formation range is on the peripheral side (right side) of the boundary line 320 in FIG. Comb-like shape, P ^- _ch channel region 23b and the field plate FP ₂ is in the form of an example for realizing a planar shape to be fitted to each other. In the polysilicon etch process follows step (S730), using a mask M4, the outer shape of the field plate FP ₂ is formed by etching.

FIG. 40 is an explanatory view showing the state of an ion implantation step for forming a P ⁻ ch region in the manufacture of the semiconductor device 10b of the second embodiment. P ^- In ch ion implantation process area formed (S740), using a mask M4 used in polysilicon etching step (S730), ion implantation implanting acceptor is an impurity for forming a P-type semiconductor as an ion In this step, the region 23br to be the P ⁻ _ch channel region 23b is formed by the step and the thermal diffusion step of thermally diffusing the implanted ions.

Thus, in the semiconductor device 10b of the second embodiment, the formation process of the P ⁻ _ch channel region 23b can be performed simultaneously with the trench gate formation process (S700a), and the common mask M4 can be used. The manufacturing process can be simplified and manufactured at low cost.

C. Variations:
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects. Specifically, for example, the following modifications can be implemented.

C-1: In each of the above-described embodiments, as an example of a channel that can be used in the present invention, when a semiconductor device is viewed in plan, a P ^- ch channel extending in the longitudinal direction to the peripheral region side from the trench gate The region 23a and the P ^- ch channel region 23b having a portion extending in the longitudinal direction to the peripheral region side than the trench gate are illustrated. For example, the channel reaching the end of the trench gate in the longitudinal direction It has been confirmed by simulations and experiments by the inventors of the present application that a channel having a part reaching the end of the trench gate in the longitudinal direction may be used. In general, the channel usable in the present invention may be a channel in which at least a part reaches the end of the trench gate (excluding the insulating film) in the longitudinal direction.

C-2: In each of the above-described embodiments, a configuration in which the present invention is applied to an N-channel MOSFET is illustrated, but the present invention can also be applied to, for example, a P-channel MOSFET. However, the N-channel MOSFET has the advantage that the main carrier is an electron, and the on-resistance is reduced because the mobility is higher than that of the hole, and the switching semiconductor device characteristics are better than that of the P-channel MOSFET. Have.

  When the present invention is applied to a P-channel MOSFET, the impurity (donor) for forming the N-type semiconductor is an example of the first conductivity type impurity, and the impurity (acceptor) for forming the P-type semiconductor is the second. This is an example of a conductive impurity. In the N-channel MOSFET, the first electrode and the second electrode correspond to the source electrode and the drain electrode, and in the P-channel MOSFET, the first electrode and the second electrode are the drain electrode, the source electrode, and Corresponding to

C-3: In each of the above-described embodiments and modifications, advantages of the case where the present invention is used in an inverter circuit and a parasitic diode is actively used are exemplified, but the semiconductor device of the present invention is You may use it for the use for which a parasitic diode is not necessarily utilized actively. This is because even in such an application, there is a case where an advantage as an improvement in resistance to a case where an abnormal current flows may be exhibited. However, if the parasitic diode is actively used, it directly affects the performance, so that it has a remarkable effect in applications where the parasitic diode can be actively used to simplify the circuit design like an inverter circuit. be able to.

DESCRIPTION OF SYMBOLS 10, 10a, 10b ... Semiconductor device 11 ... Inverter circuit 12 ... DC power supply 21 ... Trench gate 22 ... Gate insulating film 24 ... Channel contact region 25 ... Source region 32 ... Drain layer 41 ... LOCOS insulating film Ap ... Peripheral region Ac ... Cell Region Dp, Dc, Dp ... Parasitic diode FP ₀ , FP ₁ , FP ₂ ... Field plate

Claims (3)

A drain region of a first conductivity type formed in a range facing the back surface of the semiconductor substrate;
A channel region of a second conductivity type formed in the central portion of the range facing the surface of the semiconductor substrate;
A second conductivity type RESURF region formed in a peripheral portion of a range facing the surface of the semiconductor substrate;
A source region of a first conductivity type formed within a range facing the surface of the channel region;
A plurality of trenches extending from the surface of the semiconductor substrate at a position in contact with the source region, penetrating the channel region and reaching the first conductivity type semiconductor region existing on the back surface side of the semiconductor substrate;
A gate insulating film covering the wall of the trench;
A conductive gate region housed in the trench in a state covered with a gate insulating film;
A drain electrode conducting to the drain region;
A source electrode conducting to the channel region and the source region and insulated from the gate region;
An insulating film covering the surface of the RESURF region;
A conductive film that is electrically connected to the gate region and formed on the surface of the insulating film;
The plurality of trenches are arranged in parallel to each other,
The longitudinal ends of the plurality of trenches are aligned on the same straight line,
The impurity concentration in the channel region is higher than the impurity concentration in the RESURF region,
Between the pitches of a pair of adjacent trenches, at least a part of the channel region protrudes to the peripheral side of the semiconductor substrate from the straight line ,
The boundary line between the channel region and the RESURF region is displaced more to the peripheral side than the straight line in the portion away from the trench between the adjacent trenches, and is comb-shaped displaced to the center side from the straight line in the portion in contact with the trench A semiconductor device characterized by the above . 2. The semiconductor device according to claim 1 , wherein a pattern of a boundary line between the channel region and the RESURF region and a pattern of the conductive film conducted to the gate region coincide with each other. It is a manufacturing method of the semiconductor device according to claim 2 ,
A common mask is used as a mask for regulating the formation range of the channel region by regulating the implantation range of the second conductivity type impurity and a mask for regulating the formation range of the conductive film conducted to the gate region. A method for manufacturing a semiconductor device.

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