JP2007095874A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can control a latchup phenomenon, and also to prevent an element damage caused by local generation of heat. <P>SOLUTION: A semiconductor device 100 comprises a first n-type base layer 10; a second p-type base layer 20 formed in a first surface of the first base layer; a p-type deep layer 30 deeper than the second base layer, formed in the circumference of the second base layer in the first surface; an n-type emitter layer 40 formed in the second base layer of the first surface; a gate electrode 50 provided so that it might be insulated from the second base layer via a gate insulating film; a p-type collector layer 60 formed in the second surface of the first base layer at the opposite side of the first surface; a gate lead-out line 80 formed via an insulating film 101 on the deep layer; and an emitter electrode 110 for connecting the emitter layer and the deep layer through a via 90 which threads the gate lead-out line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  A power semiconductor device such as a MOSFET, an IGBT (Insulated Gate Bipolar Transistor), or an IEGT (Injection Enhanced Gate Transistor) has a large number of basic cell structures connected in parallel, and can switch a large current.

  However, when the power semiconductor device shifts from the on state to the off state, a large current and a high voltage are simultaneously applied, and an excessive current due to an avalanche phenomenon may flow. Since the avalanche current passes through a part of the basic cells, there is a problem that a latch-up phenomenon in which a parasitic thyristor such as an IGBT is turned on or a breakdown phenomenon due to local heat generation is likely to occur.

In order to prevent the latch-up phenomenon, measures such as not providing a source layer in the basic cell at the end have been proposed. However, if the source layer is reduced, the number of basic cells is reduced, which causes a problem that the on-voltage increases. Also, such a measure cannot prevent destruction due to local heat generation.
Japanese Patent Laid-Open No. 9-270512

  Provided is a semiconductor element capable of suppressing the latch-up phenomenon and preventing element destruction due to local heat generation.

  A semiconductor device according to an embodiment of the present invention includes a first conductivity type first base layer and a second conductivity type second base layer formed on a first surface of the first base layer. A deep layer of a second conductivity type that is formed around the second base layer of the first surface and is deeper than the second base layer, and the second base of the first surface. A first conductivity type emitter layer formed in the layer, a gate electrode provided so as to be insulated from the second base layer via a gate insulating film, and a side opposite to the first surface A collector layer of a second conductivity type formed on the second surface of the first base layer, a gate lead line formed on the deep layer via an insulating film and connected to the gate electrode; An emitter for connecting the emitter layer and the deep layer via vias penetrating a gate lead line And a pole.

  The semiconductor device according to the present invention can suppress the latch-up phenomenon and prevent device destruction due to local heat generation.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention. Note that the drawings are schematic and do not show the actual objects to scale.

(First embodiment)
FIG. 1 is a plan view of an insulated gate power semiconductor device (hereinafter simply referred to as a semiconductor device) 100 according to a first embodiment of the present invention. The semiconductor device 100 may be, for example, a MOSFET, IGBT, or IEGT. In the first embodiment, the semiconductor device 100 is an n-channel IGBT.

  A deep layer 30 is formed around the p-type base layer 20 which is an element formation region. The gate lead line 80 connected to the gate electrode 50 is provided above the deep layer 30. A guard ring 35 is formed on the outer side of the deep layer 30.

  The base layer 20 is provided with a large number of basic cells described with reference to FIGS. The gate lead line 80 is provided around the base layer 20 so as to surround it. As a result, the gate lead-out line 80 can apply voltages to all the gate electrodes 50 almost simultaneously and operate a large number of basic cells almost simultaneously.

  FIG. 2 is an enlarged plan view showing the gate electrode 50 and the gate lead line 80 in the broken line frame B shown in FIG. As shown in FIG. 2, the gate lead line 80 is provided with a via 90. A plurality of vias 90 are provided along the gate lead line 80.

  FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. The semiconductor device 100 includes an n-type first base layer 10, a p-type second base layer 20, a p + -type deep layer 30, an n + -type emitter layer 40, a gate electrode 50, and a p + -type. The collector layer, the gate lead line 80, and the emitter electrode 110 are provided.

  The second base layer 20 is provided on the first surface 11 of the first base layer 10. The deep layer 30 is formed on the first surface 11 so as to be adjacent to the second base layer 20, and is provided around the second base layer 20 as shown in FIG. 1. The deep layer 30 is formed deeper than the second base layer 20. The emitter layer 40 is provided in the second base layer 20 in the first surface 11.

  As shown in FIG. 4, the gate electrode 50 is provided in a trench formed so as to penetrate the second base layer 20 from the first surface 11 and reach the first base layer 10. The gate electrode 50 is provided so as to be insulated from the first base layer 10 and the second base layer 20 via a gate insulating film (not shown) formed on the inner wall of the trench. That is, the gate electrode 50 is a trench type insulated gate electrode. By applying a potential to the gate electrode 50, a channel is formed in the second base layer 20 between the emitter layer 40 and the first base layer 10 shown in FIG. The second base layer 20 provided between the gate electrode 50 and the gate electrode 50 constitutes a basic cell. Each basic cell is connected in parallel to the emitter electrode 110 and the collector electrode 70. Therefore, the semiconductor device 100 can flow a large current according to the number of basic cells.

  An interlayer insulating film 101 is provided on the first surface 11. The gate lead line 80 is formed in the interlayer insulating film 101 and is insulated from the deep layer 30 by the interlayer insulating film 101. Further, the gate lead line 80 is connected to the gate electrode 50 as shown in FIG. 3 and 4, the gate lead line 80 appears to be cut by the via 90. However, the gate lead-out line 80 is connected at a portion other than the via 90 as shown in FIG.

  The gate wiring 81 is provided on the interlayer insulating film 101 and is connected to the gate lead line 80 through a contact provided on the interlayer insulating film 101. Thereby, the gate wiring 81 is electrically connected to the gate electrode 50.

  The gate electrode 50, the gate lead-out line 80, and the gate wiring 81 are electrically insulated from the first and second base layers 10 and 20, the deep layer 30, the emitter layer 40, and the emitter electrode 110.

  The emitter electrode 110 is connected to the emitter layer 40 and the second base layer 20. The via 90 is formed so as to penetrate the interlayer insulating film 101 and the gate lead line 80 and reach the deep layer 30. The emitter electrode 110 is also connected to the deep layer 30 through the via 90. The inner wall of the via 90 is formed of an insulating film, and the emitter electrode 110 and the gate lead line 80 are insulated. The emitter electrode 110 is commonly connected to the emitter layers 40 of many basic cells.

  The collector layer 60 is provided on the second surface 12 of the first base layer 10 opposite to the first surface 11. In the present embodiment, an n + type buffer layer 15 is provided on the second surface 12 as a part of the first base layer 10 in order to increase the breakdown voltage of the semiconductor device 100. The buffer layer 15 is not an essential component, and the effect of the present embodiment is not lost even without the buffer layer 15.

  A collector electrode 70 is provided on the back side of the collector layer 60. The collector electrode 70 is commonly connected to each basic cell.

  Further, a guard ring 35 is provided outside the deep layer 30 so as to be separated from the deep layer 30. Usually, the guard ring 35 is provided along the outer periphery of the chip. In general, a plurality of guard rings 35 are provided according to a required withstand voltage. In place of the guard ring 35, a relatively shallow p-type RESURF layer may be provided so as to be in contact with the deep layer 30.

  The gate electrode 50 and the gate lead line 80 are made of, for example, doped polysilicon. The emitter electrode 110, the collector electrode 70, and the gate wiring 81 are made of a metal such as Al or Cu, for example.

  In the present embodiment, the emitter electrode 110 is connected not only to the emitter layer 40 and the second base layer 20 but also to the deep layer 30 through the via 90.

  Conventionally, when an avalanche breakdown occurs at the interface between the deep layer 30 and the first base layer, the avalanche current flows through the deep layer 30 and the second base layer 20 to the emitter electrode 110. The avalanche current turns on the thyristor including the n-type emitter layer 40, the p-type base layer 20, the n-type base layer 30 and the p-type collector layer 60, thereby causing a latch-up phenomenon. However, the latch-up phenomenon can be avoided by not providing the n-type emitter layer in the portion where the avalanche current can flow. However, an excessive avalanche current may generate heat locally by passing through a part of the basic cells, thereby destroying the basic cells. In particular, the basic cell in the vicinity of the deep layer 30, that is, the basic cell at the end of the second base layer 20 is easily destroyed.

  On the other hand, in this embodiment, since the emitter electrode 110 is directly connected to the deep layer 30, the avalanche current is discharged to the emitter electrode 110 via the via 90 without passing through the basic cell. As a result, destruction of the basic cell is suppressed. This means that the basic cell can be formed up to the vicinity of the end of the second base layer 20. Therefore, the number of basic cells can be increased and the on-voltage can be reduced.

  The gate pitch of the basic cell is, for example, 3 to 4 μm, whereas the width of the deep layer 30 is usually considerably wider than the gate pitch, for example, 100 μm. Therefore, it is easy to form the via 90 so as to connect the emitter electrode 110 to the deep layer 30 and to increase the width of the emitter electrode through the via and connect to the deep layer 30 to several tens of μm. Thereby, the possibility of destruction due to local heat generation is also reduced. Furthermore, since the emitter electrode 110 is connected to the deep layer 30 via the via 90, the basic cell can be formed up to the vicinity of the end of the second base layer 20.

  Of the interface between the deep layer 30 and the second base layer 20, the portion where the electric field strength is highest when off is generally the interface on the side opposite to the basic cell. The emitter electrode 110 is connected to the deep layer 30 at a position relatively close to the basic cell. Accordingly, the distance from the breakdown position to the emitter electrode 110 is relatively long. Therefore, the avalanche current is discharged to the emitter electrode 110 across the second base layer 20 while being dispersed. Furthermore, a plurality of via holes 90 are provided along the gate lead lines 80. As a result, the avalanche current is dispersed and discharged to the emitter electrode 110 without being concentrated in part.

(Second Embodiment)
5 and 6 are cross-sectional views of a semiconductor device according to the second embodiment of the present invention. The cross section in FIG. 5 corresponds to the cross section along the line 3-3 in FIG. The cross section in FIG. 6 corresponds to the cross section along line 4-4 in FIG. The second embodiment is different from the first embodiment in that a separation unit 120 is provided between the second base layer 20 and the deep layer 30. The separation unit 120 is provided around the second base layer 20 along the gate lead line 80.

  The separation unit 120 preferably has a configuration similar to that of the gate electrode 50. This is because the separation part 120 can be manufactured in the same process as the gate electrode 50. The separation portion 120 is provided in a trench formed so as to penetrate the second base layer 20 from the surface 11 of 1 and reach the first base layer 10. The isolation portion 120 has an insulating film (not shown) formed on the inner wall of the trench, and an internal portion provided so as to be insulated from the first base layer 10 and the second base layer 20 through the insulating film. And an electrode.

  The internal electrode of the separation unit 120 is connected to the gate lead line 80 and is maintained at the same potential as the gate electrode 50.

  The separation unit 120 prevents the avalanche current generated in the deep layer 30 from flowing to the second base layer 20. As a result, the avalanche current is less likely to flow through the basic cell and more easily flows to the emitter electrode 110 via the via 90. As a result, destruction of the basic cell is more reliably suppressed.

  The second embodiment employs an IEGT structure. As shown in FIG. 6, the IEGT has a p-type dummy layer 21 that is not connected to the emitter electrode 110. Of course, the second embodiment can be applied to the IGBT structure in the same manner as the first embodiment. Furthermore, the second embodiment has the same effect as the first embodiment.

(Third embodiment)
7 and 8 are cross-sectional views of the semiconductor device according to the third embodiment of the present invention. The cross section in FIG. 7 corresponds to the cross section along line 3-3 in FIG. The cross section in FIG. 8 corresponds to the cross section along line 4-4 in FIG. The third embodiment differs from the second embodiment in that the separation unit 120 is connected to the emitter electrode 110.

  As shown in FIG. 7, the gate lead line 80 is provided with a via 92 in addition to the via 90. The via 92 passes through the interlayer insulating film 101 and the gate lead line 80 and reaches the isolation portion 120. The emitter electrode 110 is connected to the internal electrode of the separation unit 120 through the via 92.

  As shown in FIG. 8, a separation part lead line 85 electrically separated from the gate lead line 80 is provided between the separation part 120 and the emitter electrode 110.

  FIG. 9 is an enlarged plan view showing the gate electrode 50, the gate lead line 80, and the separation part lead line 85 at a portion corresponding to the broken line frame B shown in FIG. As shown in FIG. 9, the gate lead-out line 80 is provided with a plurality of vias 90 and vias 92 in parallel. Further, the separation portion lead line 85 is provided separately from the gate lead line 80.

  According to the third embodiment, since the separation unit 120 is connected to the emitter electrode 110, the potential of the separation unit 120 is stabilized. As a result, the operation of the semiconductor device is stabilized. Furthermore, the third embodiment has the same effect as the second embodiment.

  In the above embodiment, the gate electrode 50 is a trench type, but a planar type gate electrode may be adopted.

1 is a plan view of an insulated gate power semiconductor device 100 according to a first embodiment of the present invention. The top view which expanded and showed the gate electrode 50 and the gate leader line 80 in the broken-line frame B shown in FIG. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 1. Sectional drawing along line 4-4 in FIG. Sectional drawing of the semiconductor device according to 2nd Embodiment which concerns on this invention. Sectional drawing of the semiconductor device according to 2nd Embodiment which concerns on this invention. Sectional drawing of the semiconductor device according to 3rd Embodiment concerning this invention. Sectional drawing of the semiconductor device according to 3rd Embodiment concerning this invention. The top view which expanded and showed the gate electrode 50 of the location corresponded to the broken-line frame B shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Semiconductor device 10 ... 1st base layer 20 ... 2nd base layer 30 ... Deep layer 40 ... Emitter layer 50 ... Gate electrode 60 ... Collector layer 70 ... Collector electrode 80 ... Gate leader line 90 ... Via 101 ... Interlayer insulation Membrane 110 ... Emitter electrode

Claims (5)

A first base layer of a first conductivity type;
A second conductivity type second base layer formed on the first surface of the first base layer;
A deep layer of a second conductivity type formed around the second base layer of the first surface and deeper than the second base layer;
An emitter layer of a first conductivity type formed in the second base layer of the first surface;
A gate electrode provided to be insulated from the second base layer through a gate insulating film;
A collector layer of a second conductivity type formed on the second surface of the first base layer opposite to the first surface;
A gate lead line formed on the deep layer via an insulating film and connected to the gate electrode;
A semiconductor device comprising: an emitter electrode that connects the emitter layer and the deep layer through a via penetrating the gate lead line.   The gate electrode is a trench-type gate electrode provided in a trench formed so as to penetrate the second base layer from the first surface and reach the first base layer. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, further comprising a separation portion provided between the second base layer and the deep layer.   The semiconductor device according to claim 3, wherein the separation portion is connected to the gate lead line.   The semiconductor device according to claim 3, wherein the separation portion is connected to the emitter electrode.

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