JP5632479B2 - 光印刷回路基板及びその製造方法 - Google Patents
光印刷回路基板及びその製造方法 Download PDFInfo
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- JP5632479B2 JP5632479B2 JP2012533060A JP2012533060A JP5632479B2 JP 5632479 B2 JP5632479 B2 JP 5632479B2 JP 2012533060 A JP2012533060 A JP 2012533060A JP 2012533060 A JP2012533060 A JP 2012533060A JP 5632479 B2 JP5632479 B2 JP 5632479B2
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0274—Optical details, e.g. printed circuits comprising integral optical means
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Optical Couplings Of Light Guides (AREA)
- Optical Integrated Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
Claims (11)
- 少なくとも一つ以上の内層と前記内層を電気的に接続する回路パターンを備える印刷回路基板と、
前記印刷回路基板の内部に埋め込まれる一体型光接続モジュールを含み、
前記一体型光接続モジュールは、
光信号を送出する光送信部と、
前記光送信部から送出された光信号を受信する光受信部と、
前記光送信部と前記光受信部を接続する光導波路と、
前記光導波路の外部を保護する支持ユニットを含む、
ことを特徴とする光印刷回路基板。 - 前記支持ユニットは、前記光導波路を支持ユニットの上部面に配置し、または内部に収容する構造で形成される、請求項1に記載の光印刷回路基板。
- 前記印刷回路基板の表面には、前記一体型光接続モジュールの前記光送信部及び前記光受信部が露出する段差構造のアライメントパターン領域が形成される、請求項1に記載の光印刷回路基板。
- 前記一体型光接続モジュールは、前記印刷回路基板の内層に全体が埋め込まれる構造で配置される、請求項1に記載の光印刷回路基板。
- 前記アライメントパターン領域は、前記印刷回路基板の最外部表面の水平面より低い、少なくとも一つ以上の段差構造で形成される、請求項3に記載の光印刷回路基板。
- 前記アライメントパターン領域は、前記印刷回路基板の最外部の表面層を基準として、印刷回路基板の最外部内層の厚さを限度とする深さを有する、請求項3に記載の光印刷回路基板。
- 前記アライメントパターン領域に挿入され、前記一体型光接続モジュールと自動アライメントされて装着される送受信モジュールをさらに含む、請求項3に記載の光印刷回路基板。
- 前記送受信モジュールと前記一体型光接続モジュールは、ガイドピンを用いて2次アライメントされる構造で形成される、請求項7に記載の光印刷回路基板。
- 前記送受信モジュールは、E/Oコンバーター(Electro Optical Convertor)またはO/Eコンバーター(Optical Electro Convertor)を含む、請求項8に記載の光印刷回路基板。
- 前記送受信モジュールは、前記印刷回路基板の表面より低く装着される、請求項9に記載の光印刷回路基板。
- 前記一体型光接続モジュールは、前記光送信部及び前記光受信部にアライメントされて装着される送受信モジュールをさらに含む、請求項4に記載の光印刷回路基板。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090095841A KR101164952B1 (ko) | 2009-10-08 | 2009-10-08 | 광인쇄회로기판 및 그 제조방법 |
KR10-2009-0095841 | 2009-10-08 | ||
KR1020090096271A KR20110039017A (ko) | 2009-10-09 | 2009-10-09 | 광인쇄회로기판 및 그 제조방법 |
KR10-2009-0096271 | 2009-10-09 | ||
PCT/KR2010/001799 WO2011043521A1 (en) | 2009-10-08 | 2010-03-24 | Optical printed circuit board and method of fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013507656A JP2013507656A (ja) | 2013-03-04 |
JP5632479B2 true JP5632479B2 (ja) | 2014-11-26 |
Family
ID=43856960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012533060A Expired - Fee Related JP5632479B2 (ja) | 2009-10-08 | 2010-03-24 | 光印刷回路基板及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8867871B2 (ja) |
JP (1) | JP5632479B2 (ja) |
CN (1) | CN102648428B (ja) |
TW (1) | TWI434642B (ja) |
WO (1) | WO2011043521A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI549577B (zh) * | 2012-11-22 | 2016-09-11 | 鴻海精密工業股份有限公司 | 光纖連接器電路基板及光纖連接器 |
FI20135200L (fi) * | 2013-03-01 | 2014-09-02 | Tellabs Oy | Sähkölaite |
CN103308081B (zh) * | 2013-06-04 | 2016-01-27 | 北京经纬恒润科技有限公司 | 一种校准光路装置和光电传感器 |
US9837484B2 (en) * | 2015-05-27 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming substrate including embedded component with symmetrical structure |
US11071199B2 (en) | 2018-10-09 | 2021-07-20 | City University Of Hong Kong | Optical printed circuit board and its fabrication method |
US11899255B2 (en) | 2022-06-17 | 2024-02-13 | City University Of Hong Kong | Optical printed circuit board and its fabricating method |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU7885900A (en) * | 1999-08-27 | 2001-03-26 | Board Of Regents, The University Of Texas System | Packaging enhanced board level opto-electronic interconnects |
US7263248B2 (en) * | 2003-02-11 | 2007-08-28 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Optical via to pass signals through a printed circuit board |
KR100679253B1 (ko) * | 2004-09-10 | 2007-02-06 | 한국정보통신대학교 산학협력단 | 광 피씨비, 광 피씨비용 송수신 모듈 및 광연결블록연결구조 |
JP2008015336A (ja) * | 2006-07-07 | 2008-01-24 | Fujitsu Ltd | 回路基板及び半導体デバイスの光結合方法 |
KR100796982B1 (ko) * | 2006-11-21 | 2008-01-22 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
CN101206287A (zh) * | 2006-12-22 | 2008-06-25 | 财团法人工业技术研究院 | 光电基板及其制造方法 |
KR100905140B1 (ko) | 2007-09-28 | 2009-06-29 | 한국정보통신대학교 산학협력단 | 광 도파로가 적층된 광 인쇄회로기판을 이용한 광연결시스템 |
KR100952478B1 (ko) | 2008-02-19 | 2010-04-13 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR100976654B1 (ko) * | 2008-02-26 | 2010-08-18 | 한국과학기술원 | 광 인쇄회로기판 및 그 제조 방법 |
WO2009107908A1 (en) * | 2008-02-26 | 2009-09-03 | Icu Research And Industrial Cooperation Group | A optical printed circuit board and a optical module connected to the optical printed circuit board |
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2010
- 2010-03-24 JP JP2012533060A patent/JP5632479B2/ja not_active Expired - Fee Related
- 2010-03-24 US US13/500,779 patent/US8867871B2/en not_active Expired - Fee Related
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US8867871B2 (en) | 2014-10-21 |
US20120263412A1 (en) | 2012-10-18 |
TWI434642B (zh) | 2014-04-11 |
JP2013507656A (ja) | 2013-03-04 |
WO2011043521A1 (en) | 2011-04-14 |
TW201114349A (en) | 2011-04-16 |
CN102648428B (zh) | 2015-09-09 |
CN102648428A (zh) | 2012-08-22 |
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