JP5623607B2 - Imaging apparatus and imaging system - Google Patents

Description

The present invention relates to an imaging apparatus and an imaging system.

  The following three points are disclosed by the following Patent Document 1 as a driving method for expanding the dynamic range of the solid-state imaging device. First, the electric charge overflowing from the light receiving unit is accumulated in the floating diffusion and the additional capacitor to obtain a dynamic range expansion signal. Secondly, overflowing charges are accumulated only during a part of the accumulation period of the light receiving unit, and a dynamic range expansion signal is obtained. Thirdly, the signal accumulated in the light receiving unit and the dynamic range expansion signal are added and output within the pixel.

JP 2005-328493 A

  Patent Document 1 discloses that the floating diffusion includes a PN junction including a deep impurity region and a p-type well, and that the photodiode is a buried photodiode. However, the floating diffusion has a problem that the dark output due to the current generated in the depletion layer is large for the photodiode.

  This problem does not pose a problem when the accumulation period is short, but when the accumulation period is long, there arises a problem that a signal due to the dark current of the floating diffusion section or the additional capacitor that accumulates the dynamic range expansion signal increases. This is because the FD and CS portions are not buried PN junction capacitors, which increases dark current, and is not suitable as a holding portion that holds charges for a long time. The signal amplitude at the FD (or vertical signal line) is limited by the dark current component, and the signal amplitude for the dynamic range expansion signal cannot be secured.

  With respect to this problem, a certain degree of improvement can be achieved by shortening the accumulation period of the dynamic range expansion signal by the method shown in the second disclosed point. However, this time, the accumulation period of the photodiode and the accumulation period of the dynamic range expansion signal are shifted, and a big problem occurs that the simultaneity of the two signals is impaired. Both are not problematic because the accumulation period is short for moving images, but it is a major problem in still image shooting such as a digital single-lens reflex camera.

An object of the present invention is to provide an image pickup apparatus and an imaging system that can expand the dynamic range while maintaining the simultaneity of the photoelectric conversion part and the charge accumulation period of the charge storage portion.

The imaging device of the present invention is an imaging device having a plurality of pixels and a control unit, and each of the plurality of pixels includes a photoelectric conversion unit that accumulates charges generated by photoelectric conversion, and the photoelectric conversion unit. amplification and charge accumulation unit for accumulating electric charges of the floating diffusion portion, a transfer unit and the charge storage unit charges accumulated in including a transistor to be transferred to the floating diffusion section, a signal based on the charge of the floating diffusion portion And a reset unit that resets the floating diffusion unit , and the control unit reads the dynamic range expansion signal a plurality of times, and then resets the transistor from on to off after a reset operation by the reset unit. And turning on the transistor The transfer of charge from the charge storage unit to the floating diffusion portion, as intends multiple rows for a single charge accumulation period in the photoelectric conversion unit, and controls the transfer unit.

  The dynamic range can be expanded while ensuring the simultaneity of the charge accumulation period of the photoelectric conversion unit and the charge accumulation unit.

It is a circuit diagram which shows the structural example of the pixel part in the light reception area | region by the 1st Embodiment of this invention. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment of the present invention. It is a timing chart which shows the drive timing in the pixel part of the nth to (n + 2) line of a light reception area | region. It is a figure which shows the photoelectric conversion characteristic of 1st Embodiment. It is a timing chart which shows the drive timing of the solid imaging device by a 2nd embodiment of the present invention. It is a circuit diagram which shows the structural example of the pixel part in the light reception area | region by 2nd Embodiment. It is a figure which shows the photoelectric conversion characteristic of 2nd Embodiment. It is a figure which shows the structural example of the camera system at the time of using the solid-state imaging device by the 4th Embodiment of this invention for a camera. It is a timing chart which shows the drive timing of the solid-state imaging device by the 5th Embodiment of this invention. It is a timing chart which shows the drive timing of a solid-state imaging device.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS.
FIG. 2 is a block diagram showing a configuration example of the MOS type solid-state imaging device according to the first embodiment of the present invention, and FIG. 1 is a circuit diagram showing a configuration example of the pixel portion in the light receiving region 101 of FIG. A plurality of pixel portions are two-dimensionally arranged in the light receiving region 101.

  In FIG. 1, PD is a photodiode. The photodiode PD converts received light into electric charge and accumulates it. TX is a transfer switch. RES is a reset switch for resetting the floating diffusion portion FD. SF is a source follower input MOS field effect transistor having the floating diffusion portion FD as an input terminal. SEL is a switch for row selection. FD is a source follower input terminal, which is a floating diffusion section that holds transferred charges and converts the voltage. SW is a switch for controlling connection between the storage capacitor Ccs and the floating diffusion portion FD. Ccs is a storage capacitor for accumulating charges overflowing from the photodiode PD. By providing the storage capacitor Ccs in addition to the photodiode PD, the charge storage capacitor can be increased and the dynamic range can be expanded. A method for driving the pixel portion will be described later with reference to FIG.

  In FIG. 2, 100 is a sensor chip. Reference numeral 101 denotes a light receiving area. Reference numerals 102a and 102b denote column signal processing circuits. 103a and 103b are horizontal scanning circuits. Reference numeral 104 denotes a vertical scanning circuit. Reference numerals 105a and 105b denote read amplifier units. Reference numerals 106a and 106b denote common signal line portions. Reference numerals 107a and 107b denote output line portions.

  The light receiving region 101 has a plurality of pixel portions in FIG. 1 and generates a two-dimensional image signal. The vertical scanning circuit 104 sequentially selects the rows of the pixel portions of the light receiving region 101, and reads out the signals of the pixel portions of the selected rows to the column signal processing circuits 102a and 102b. The horizontal scanning circuits 103a and 103b sequentially select signal columns of the column signal processing circuits 102a and 102b, and output the selected signals to the read amplifier units 105a and 105b via the common signal line units 106a and 106b. The read amplifier units 105a and 105b amplify the signal and output it to the outside via the output line units 107a and 107b.

  FIG. 3 is a timing chart showing drive timings in the pixel portion from the n-th row to the (n + 2) -th row of the light receiving region 101. Hereinafter, a processing method of the solid-state imaging device will be described. Each pulse is a signal generated by the vertical scanning circuit 104 and is as follows. ΦRES is a gate drive pulse of the reset transistor RES in FIG. ΦTX is a gate drive pulse of the transfer transistor TX in FIG. ΦSW is a gate drive pulse of the switch transistor SW in FIG. ΦSEL is a gate drive pulse of SEL in FIG. N to n + 2 at the end of each pulse indicates a row. Further, the vertical scanning circuit 104 can turn on the switch SEL by outputting a high level to the gate of the switch SEL, and can turn off the switch SEL by outputting a low level to the gate of the switch SEL.

  When the signal ΦTX becomes high level, the transfer switch TX transfers the signal accumulated in the photodiode PD to the floating diffusion portion FD that is the input terminal of the source follower transistor SF. The reset switch RES resets the floating diffusion portion FD when the signal ΦRES becomes a high level. The holding capacitor Ccs is a capacitor for holding charges overflowing from the photodiode PD. The switch SW is a switch for controlling the connection between the floating diffusion portion FD and the storage capacitor Ccs. The switch SEL is a switch for selecting a row of the pixel portion of the light receiving region 101, and reads the output signal of the source follower transistor SF to the column signal processing circuit 103a or 103b when the gate becomes a high level.

  As shown in FIG. 3, the dynamic range expansion signal of the photodiode PD is read out in four steps. The operation in the periods T1 to T15 will be described below.

  The period T1 is a period during which the n-th row photodiode PD is reset. The period T1 is a period in which the high level state of the pulse is maintained. Specifically, the signals ΦTX_n, ΦRES_n, and ΦSW_n are high levels, and the other signals in the drawing maintain the low level. The transistors TX, RES, and SW in the nth row are turned on, and the photodiode PD and the holding capacitor Ccs in the nth row are reset.

  A period T2 is a reset period of the photodiode PD in the (n + 1) th row. Specifically, this is a period in which the signals ΦTX_n + 1, ΦRES_n + 1, and ΦSW_n + 1 are at a high level and the other signals in the drawing are maintained at a low level. The transistors TX, RES, and SW in the (n + 1) th row are turned on, and the photodiode PD and the storage capacitor Ccs in the (n + 1) th row are reset.

  A period T3 is a reset period of the photodiode PD in the (n + 2) th row. Specifically, this is a period in which the signals ΦTX_n + 2, ΦRES_n + 2, and ΦSW_n + 2 are at a high level, and other signals in the drawing are maintained at a low level. The transistors TX, RES, and SW in the (n + 2) th row are turned on, and the photodiode PD and the storage capacitor Ccs in the (n + 2) th row are reset.

  The period T4 is a first reading period of the dynamic range expansion signal of the nth row. The signal ΦSW_n changes from the high level to the low level. The transistor SW in the nth row is turned off from on. The storage capacitor Ccs accumulates charges overflowing from the photodiode PD, and outputs the charges to the floating diffusion portion FD via the transistor SW while the transistor SW is on. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a dynamic range expansion signal. The column signal processing circuit 102a or 102b reads and holds the dynamic range expansion signal.

  Next, the signal ΦRES_n becomes a high level, and the transistor RES in the n-th row is turned on. Thereby, the floating diffusion part FD of the nth row is reset.

  A period T5 is a first reading period of the reset signal in the n-th row. The signal ΦRES_n becomes a low level, and the transistor RES in the n-th row is turned off. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a reset signal (noise signal). The column signal processing circuit 102a or 102b reads and holds the reset signal. The read amplifier unit 105a or 105b outputs a pixel signal with reduced noise by subtracting the reset signal from the dynamic range expansion signal.

  The period T6 is a first reset period of the dynamic range expansion signal of the nth row. The signals ΦRES_n and ΦSW_n become high level, and the transistors RES and SW in the nth row are turned on. As a result, the storage capacitor Ccs in the nth row is reset.

  The period T7 is a first reading period of the dynamic range expansion signal of the (n + 1) th row. The signal ΦSW_n + 1 changes from the high level to the low level. The transistor SW in the (n + 1) th row is turned off from on. The storage capacitor Ccs accumulates charges overflowing from the photodiode PD, and outputs the charges to the floating diffusion portion FD via the transistor SW while the transistor SW is on. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a dynamic range expansion signal. The column signal processing circuit 102a or 102b reads and holds the dynamic range expansion signal.

  Next, the signal ΦRES_n + 1 becomes high level, and the transistors RES in the (n + 1) th row are turned on. As a result, the floating diffusion portion FD in the (n + 1) th row is reset.

  The period T8 is a first reading period of the reset signal of the (n + 1) th row. The signal ΦRES_n + 1 becomes a low level, and the transistors RES in the (n + 1) th row are turned off. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a reset signal (noise signal). The column signal processing circuit 102a or 102b reads and holds the reset signal. The read amplifier unit 105a or 105b outputs a pixel signal with reduced noise by subtracting the reset signal from the dynamic range expansion signal.

  The period T9 is a first reset period of the dynamic range expansion signal on the (n + 1) th row. The signals ΦRES_n + 1 and ΦSW_n + 1 become high level, and the transistors RES and SW in the (n + 1) th row are turned on. As a result, the storage capacitor Ccs in the (n + 1) th row is reset.

  Also in the (n + 2) th row, the first reading period of the dynamic range expansion signal of the (n + 2) th row, the first reading period of the reset signal of the (n + 2) th row, and the first reset period of the dynamic range expansion signal of the (n + 2) th row. Is done. These processes are the same as the processes in the above-mentioned n-th periods T4, T5, and T6.

  Next, similarly to the periods T4, T5, and T6, the second readout period of the dynamic range expansion signal of the nth row, the second readout period of the reset signal of the nth row, and the dynamic range extension signal of the nth row. Processing for the second reset period is performed. Further, thereafter, similarly, the third readout period of the nth row dynamic range expansion signal, the third readout period of the nth row reset signal, and the third reset period of the nth row dynamic range extension signal. Processing is performed.

  Similarly to the periods T7, T8, and T9, the second readout period of the dynamic range expansion signal of the (n + 1) th row, the second readout period of the reset signal of the (n + 1) th row, and the second readout period of the dynamic range extension signal of the (n + 1) th row. Processing for the second reset period is performed. Further, thereafter, similarly, the third readout period of the dynamic range expansion signal of the (n + 1) th row, the third readout period of the reset signal of the (n + 1) th row, and the third reset period of the dynamic range extension signal of the (n + 1) th row. Processing is performed.

  Similarly to the periods T4, T5, and T6, the second readout period of the dynamic range expansion signal in the (n + 2) th row, the second readout period of the reset signal in the (n + 2) th row, and the second readout period of the dynamic range expansion signal in the (n + 2) th row. Processing for the second reset period is performed. Further, thereafter, similarly, the third readout period of the dynamic range expansion signal of the (n + 2) th row, the third readout period of the reset signal of the (n + 2) th row, and the third reset period of the dynamic range extension signal of the (n + 2) th row. Processing is performed.

  Similarly to the period T4, the period T10 is a fourth reading period of the dynamic range expansion signal of the nth row.

  Similarly to the period T5, the period T11 is the fourth reading of the reset signal in the n-th row and the reset period of the floating diffusion portion FD. The signal ΦRES_n becomes a high level, and the n-th row transistor RES is turned on. Thereby, the floating diffusion part FD is reset. Next, the signal ΦRES_n becomes a low level, and the transistor RES in the n-th row is turned off. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a reset signal (noise signal). The column signal processing circuit 102a or 102b reads and holds the reset signal. The read amplifier unit 105a or 105b outputs a pixel signal with reduced noise by subtracting the reset signal from the dynamic range expansion signal.

  A period T12 is a first reading period of the photodiode signal in the n-th row. The signal ΦTX_n becomes a high level, and the transfer transistor TX in the n-th row is turned on. The charge accumulated in the photodiode PD is output to the floating diffusion portion FD. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a photodiode signal. The column signal processing circuit 102a or 102b reads out and holds the photodiode signal.

  Similarly to the period T7, the period T13 is a fourth reading period of the dynamic range expansion signal of the (n + 1) th row.

  The period T14 is a fourth period for reading the reset signal in the (n + 1) th row and resetting the floating diffusion FD. The signal ΦRES_n + 1 becomes high level, and the transistors RES in the (n + 1) th row are turned on. Thereby, the floating diffusion part FD is reset. Next, the signal ΦRES_n + 1 becomes low level, and the transistors RES in the (n + 1) th row are turned off. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a reset signal (noise signal). The column signal processing circuit 102a or 102b reads and holds the reset signal. The read amplifier unit 105a or 105b outputs a pixel signal with reduced noise by subtracting the reset signal from the dynamic range expansion signal.

  A period T15 is a first reading period of the photodiode signal in the (n + 1) th row. The signal ΦTX_n + 1 becomes high level, and the transfer transistor TX in the (n + 1) th row is turned on. The charge accumulated in the photodiode PD is output to the floating diffusion portion FD. By changing the signal ΦSEL_n from the low level to the high level, the source follower transistor SF reads a signal based on the potential of the floating diffusion portion FD as a photodiode signal. The column signal processing circuit 102a or 102b reads out and holds the photodiode signal.

  Next, the fourth readout period of the dynamic range expansion signal in the n + 2 row, the fourth readout period of the reset signal in the n + 2 row, the reset period of the floating diffusion FD, and the first readout period of the photodiode signal in the n + 2 row. Is performed. These processes are the same as the processes in the periods T10, T11, and T12.

  As a driving condition of the solid-state imaging device of the present embodiment, a driving condition that takes about 30 milliseconds to read out all pixels was used. For the storage period of the photodiode PD of 1 second, the dynamic range expansion signal is read out four times every 250 milliseconds. That is, in an accumulation period longer than one frame readout time, an overflow signal in the same accumulation period is read out in a plurality of times, and the overflow signal is reset after each readout operation.

  The read operation in the present embodiment is an operation of reading a signal based on the electric charge generated in the photodiode by turning on the SEL switch to the column signal processing circuit. Further, the reset signal subtraction process includes a clamp circuit or the like in the column signal processing circuits 102a and 102b, and this circuit can also perform the subtraction process.

  By doing so, it was possible to suppress the dynamic range expansion signal from being pressed by the dark current generated on the floating diffusion portion FD and the storage capacitor Ccs. Specifically, the maximum voltage amplitude at the floating diffusion portion FD and the storage capacitor Ccs was 0.5 V, whereas a signal due to dark current was generated at about 100 mV. It could be suppressed to 25 mV per reading. The signals read out in four times are added for each pixel by a processing circuit 803 (FIG. 8) separate from the solid-state imaging device, so that the dynamic range is expanded accordingly. Of course, the processing circuit may be included in the solid-state imaging device and the addition may be performed in the solid-state imaging device.

  That is, in the method disclosed in Patent Document 1, the amount of expansion of the dynamic range is +400 mV as the voltage on the floating diffusion portion FD with respect to the saturation voltage of the photodiode PD. On the other hand, in the present embodiment, (500-25) × 4 = 1900 mV, which is an enlargement amount close to five times, can be obtained.

  The dark current value described above is an average pixel value. Like the white spots (white scratches) in the photodiode PD, the floating diffusion portion FD and the storage capacitor Ccs are defective, and some pixels have a dark current 10 to 100 times that of an average pixel. . In such a pixel, a dynamic range expansion signal of +400 mV cannot be obtained, and in some cases, it may be hardly retained. This embodiment has an effect of not only expanding the dynamic range of an average pixel, but also reducing or eliminating the number of pixels that cannot hold the dynamic range expansion signal as described above.

  The important point is that the dark current is also reset because the reset operation is performed after reading out the dynamic range expansion signal. Further, by reading out and processing a dynamic range expansion signal during a period substantially the same as the accumulation period of the photodiode PD, the simultaneity of both can be ensured.

  The reason why it is described as “substantially the same period” is because information during the reading period cannot be obtained strictly. That is, while the entire accumulation period is several hundred milliseconds to several tens of seconds, the reading time is around 10 μsec and the lack of information is 10 μsec × number of readings, which is about 1/10000. is there. Each dynamic range expansion signal may be simply added, may be added with a gain, may be added with a weight, or may be added after a partial correction process is added. In any method, it is important that signal information within the same accumulation period is included. Synchronization is an extremely important item especially when handling long-second still images such as fireworks.

  Note that the driving shown in FIG. 10 may be performed instead of FIG. FIG. 10 differs from FIG. 3 in that the pulses of the signals ΦSEL_n, ΦSEL_n + 1, and ΦSEL_n + 2 are not changed when selected.

  FIG. 4 is a diagram showing the photoelectric conversion characteristics of this embodiment, and shows an output signal from the sensor chip 100. A characteristic Aa is a signal of the photodiode PD. Characteristics Ab, Ac, Ad, and Ae are read signals from the first to fourth times of the dynamic range expansion signal, respectively. At this time, the slope of the characteristic Aa and the slope of the characteristic Ab are different because the dynamic range expansion signal is voltage-converted by the sum of the capacity of the floating diffusion portion FD and the storage capacity Ccs. The characteristic Af is an output voltage on the floating diffusion portion FD and the holding capacitor Ccs due to the dark current on the floating diffusion portion FD and the holding capacitor Ccs in Patent Document 1. The characteristic Ag is an output voltage on the floating diffusion portion FD and the storage capacitor Ccs due to the dark current on the floating diffusion portion FD and the storage capacitor Ccs in the present embodiment.

In the above-mentioned Patent Document 1, the dynamic range expansion amount is VD. In the present embodiment, if VDR is used, the dynamic range expansion amount is expressed by the following equation.
“Number of reads” × VDR × {“FD capacity” + “Ccs capacity”} / “FD capacity”

  Therefore, the dynamic range expansion amount can be increased according to the number of readings.

(Second Embodiment)
FIG. 5 is a timing chart showing the drive timing of the solid-state imaging device according to the second embodiment of the present invention. The present embodiment is driven by the timing shown in FIG. 5 in the same circuit as the first embodiment. FIG. 5 is a drive timing chart in the pixel portion from the n-th row to the (n + 2) -th row of the present embodiment. This embodiment (FIG. 5) differs from the first embodiment (FIG. 3) in that the signal ΦSW is fixed at a high level during the charge accumulation period of the photodiode PD. By setting it as such operation | movement, operation | movement of the period T6 etc. which were 1st Embodiment becomes unnecessary. That is, it is not necessary to set the signal ΦRES to the high level in the period T6 or the like. Note that the signals ΦSEL_n, ΦSEL_n + 1, and ΦSEL_n + 2 in FIG. 10 may be applied as in the first embodiment.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS.
FIG. 6 is a circuit diagram illustrating a configuration example of the pixel portion in the light receiving region 101 of FIG. This embodiment (FIG. 6) is different from the first embodiment (FIG. 1) in that there is no storage capacitor Ccs and transistor SW. The drive timing of the present embodiment is the same as that except for the signal ΦSW in the drive timing chart of FIG. Even when there is no storage capacitor Ccs, the effect of this embodiment is the same as that of the first embodiment. In the charge accumulation period of the photodiode PD, the transfer switch TX is off, and when the charge overflows from the accumulation part of the photodiode PD, the overflowed charge flows into the floating diffusion part FD via the transfer switch TX.

  FIG. 7 is a diagram illustrating the photoelectric conversion characteristics of the solid-state imaging device. In the photoelectric conversion characteristics, the characteristics Aa to Ag indicate the same as those in the first embodiment (FIG. 4). The slopes of the characteristics Aa and Ab are equal because both the signal of the photodiode PD and the dynamic range expansion signal are voltage-converted by the capacitance of the floating diffusion portion FD. If such a format is used, the processing when the addition is appropriately performed by the processing circuit thereafter is simplified, the system load is reduced, and the processing time is increased.

  The feature of this embodiment is that the number of elements in one pixel portion is small, and it is possible to cope with a smaller pixel portion. Although the amount of expansion of the dynamic range is small, it can be compensated by increasing the number of readings.

  In the present embodiment, the amount of expansion of the dynamic range can be further increased by providing the photodiode PD with an overflow drain that discharges the overflowed charge through a path different from the transfer switch TX. In such a case, the same effect can be obtained. The photoelectric conversion characteristics in this case are as shown in FIG. 4, and the difference in the slopes of the characteristics Aa and Ab has the following relationship.

The amount of charge overflowing from the photodiode PD = A, the amount of charge discharged from the overflow drain = B, the amount of charge held in the floating diffusion portion FD = C, the slope of the characteristic Aa = α, and the slope of the characteristic Ab = β. The following equation holds.
A = B + C
α / β = A / C

  By providing an overflow drain, the dynamic range can be further expanded.

  Further, as a modification of the present embodiment, a configuration in which a Ccs portion is provided and the Ccs portion is composed only of a PN junction capacitance and does not have a capacitance due to a gate oxide film is conceivable. The Ccs portion has a PN junction capacitance composed of a semiconductor substrate and a high concentration impurity region.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram illustrating a configuration example of a camera system when a solid-state imaging device according to the fourth embodiment of the present invention is used in a camera. The sensor 802 in the figure corresponds to the sensor chip 100 in FIG. 2 and uses the solid-state imaging device according to the third embodiment. Of course, the solid-state imaging device according to another embodiment may be used. A signal output from the sensor 802, that is, a dynamic range expansion signal and a photodiode signal are held in the memory 804 via the processing circuit 803. The processing circuit 803 uses the memory 804 to add the dynamic range expansion signal and the photodiode signal. After the charge accumulation, the last photodiode signal is read from the sensor 802 to the processing circuit 803. The processing circuit 803 outputs the added signal to the image processing circuit 805. The image processing circuit 805 performs development processing. The timing generator 801 generates control signals for the sensor 802, the processing circuit 803, and the memory 804.

  In the third embodiment, as shown in FIG. 7, the processing circuit 803 has a photoelectric conversion characteristic in which the inclination of the photoelectric conversion characteristic Aa before saturation and the inclination of the photoelectric conversion characteristics Ab to Ae after saturation are equal, Only a simple addition process needs to be performed, and the processing circuit 803 can be simplified.

(Fifth embodiment)
FIG. 9 is a timing chart showing the drive timing of the solid-state imaging device according to the fifth embodiment of the present invention. This embodiment is an embodiment when used in combination with a mechanical shutter, and uses a circuit similar to the first embodiment. The mechanical shutter is opened at time t1, and the mechanical shutter is closed at time t3. The operation in the periods T1 to T15 is the same as the operation in FIG. However, the operations in the periods T1 to T3 are performed simultaneously.

  The exposure start is defined by opening the mechanical shutter at time t1, and the exposure end is defined by closing the mechanical shutter at time t3. Since the exposure start is defined by the mechanical shutter, similar to the first embodiment, even if the reset operation of the periods T1 to T3 is sequentially performed, a similar image can be obtained if the mechanical shutter is opened after the reset of all rows is completed. it can. If the mechanical shutter is closed at time t2, only the dark current information of the floating diffusion portion FD is included in the last dynamic range expansion signal. Therefore, the fixed pattern noise can be reduced by adding the first three signals and subtracting the last signal.

  The drive timing when the mechanical shutter is used in combination is not limited to that shown in FIG. 9, and a good image can be obtained by interlocking the mechanical shutter based on the above-described idea even at the drive timing shown in FIGS. Similarly to the first embodiment, the signals ΦSEL_n, ΦSEL_n + 1, and ΦSEL_n + 2 in FIG. 10 may be applied.

  As described above, in the first to fifth embodiments, the pixel portion including at least the photodiode PD, the transfer switch TX that transfers the signal of the photodiode PD, and the storage capacitor Ccs that holds the signal overflowing from the photodiode PD is provided. It is a solid-state imaging device arranged in two dimensions. Overflowing signals during the same accumulation period are read out multiple times, and the overflowing signal is reset after each reading.

  In the above-mentioned Patent Document 1, it is disclosed that the dynamic range expansion signal is read only once for the charge accumulation period of the photodiode. That is, in Patent Document 1, the readout of the dynamic range expansion signal is performed once for each readout of the photodiode. In the present embodiment, the dynamic range expansion signal is read a plurality of times during the charge accumulation period of the photodiode PD, and the dynamic range is expanded while ensuring the synchronism of the charge accumulation period of the photodiode PD and the storage capacitor Ccs. be able to.

  In the solid-state imaging devices of the first to fifth embodiments, the photodiode PD is a photoelectric conversion unit that generates charges by photoelectric conversion and accumulates the generated charges. The storage capacitor Ccs or the floating diffusion portion FD is a charge accumulation portion that accumulates charges overflowing from the photoelectric conversion portion PD. The row selection switch SEL is a reading unit for reading a signal based on the electric charge generated in the photoelectric conversion unit to the outside. The reading unit may include a vertical scanning circuit 104 that drives the row selection switch SEL. The column signal processing circuits 102a and 102b read out signals based on the charges accumulated in the charge accumulation unit Ccs or FD within one charge accumulation period for the charges generated by the photoelectric conversion unit PD. Process. The reset switch RES resets the charge accumulated in the charge accumulation unit Ccs or FD after each readout of the readout units 102a and 102b.

  In the first embodiment (FIG. 1), the charge storage unit is a storage capacitor Ccs. The transfer switch TX is a switch for transferring the charge accumulated in the photoelectric conversion unit PD to the floating diffusion unit FD. The switch SW is a connection switch for connecting the charge storage unit Ccs and the floating diffusion unit FD. Under the control of the row selection switch SEL, a signal based on the charge of the floating diffusion portion FD is read through the source follower transistor SF.

  In the third embodiment (FIG. 6), the charge storage unit is a floating diffusion unit FD. The switch TX is a transfer switch for transferring charges accumulated in the photoelectric conversion unit PD to the floating diffusion unit FD. By controlling the row selection switch SEL, a signal based on the electric charge of the floating diffusion portion FD is read out.

  The readout units 102a and 102b read the charge accumulated in the photoelectric conversion unit PD after reading the charge accumulated in the charge accumulation unit Ccs or FD a plurality of times within the one charge accumulation period. .

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

PD Photodiode TX Transfer switch RES Reset switch SF Source follower input MOS transistor SEL Row selection switch FD Floating diffusion part SW Switch Ccs Holding capacitor 100 Sensor chip 101 Light receiving area 102a, 102b Column signal processing circuits 103a, 103b Horizontal scanning circuit 104 Vertical scanning circuits 105a and 105b Read amplifier units 106a and 106b Common signal line units 107a and 107b Output line units

Claims (4)

An imaging apparatus having a plurality of pixels and a control unit,
Each of the plurality of pixels is
A photoelectric conversion unit for accumulating charges generated by photoelectric conversion;
A charge storage unit that stores charges from the photoelectric conversion unit;
Floating diffusion,
A transfer unit including a transistor for transferring the charge stored in the charge storage unit to the floating diffusion unit ;
An amplifying unit for amplifying a signal based on the charge of the floating diffusion unit ;
A reset unit for resetting the floating diffusion unit ,
The controller is configured to read the dynamic range expansion signal a plurality of times , and after the reset operation by the reset unit, to turn off the transistor from on, and from the charge storage unit by turning on the transistor the transfer of charge to the floating diffusion portion, as intends multiple rows for a single charge accumulation period in the photoelectric conversion unit, an imaging device and controls the transfer unit. Each of the plurality of pixels is
A readout unit for reading out the signal amplified by the amplification unit;
The control unit, after a reset operation by the reset unit, transfer of charges from the charge storage unit to the floating diffusion unit , and reading of the dynamic range expansion signal by the read unit after the transfer, and a reset by the reset unit after the reading, as intends multiple rows for a single charge accumulation period in the photoelectric conversion unit, controlling said reset unit and the transfer unit and the reading unit The imaging apparatus according to claim 1. The charge storage section, the image pickup apparatus according to claim 1 or claim 2, characterized in that it comprises a PN junction capacitance. An imaging device having a plurality of pixels;
A control unit for controlling the imaging device;
A signal processing device for processing a signal from the imaging device,
Each of the plurality of pixels is
A photoelectric conversion unit for accumulating charges generated by photoelectric conversion;
A charge storage unit that stores charges from the photoelectric conversion unit;
Floating diffusion,
A transfer unit including a transistor for transferring the charge stored in the charge storage unit to the floating diffusion unit ;
An amplifying unit for amplifying a signal based on the charge of the floating diffusion unit ;
A reset unit for resetting the floating diffusion unit ,
The controller is configured to read the dynamic range expansion signal a plurality of times , and after the reset operation by the reset unit, to turn off the transistor from on, and from the charge storage unit by turning on the transistor the transfer of charge to the floating diffusion portion, as intends multiple rows for a single charge accumulation period in the photoelectric conversion unit, an imaging system, characterized by controlling the imaging device.

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