JP5589601B2 - Integrated circuit element built-in substrate and integrated circuit element built into the integrated circuit element built-in substrate - Google Patents

Description

  The present invention relates to an integrated circuit element built-in substrate and an integrated circuit element built in the integrated circuit element built-in substrate.

  As electronic devices continue to become lighter, thinner, and smaller, integrated circuit elements themselves have become smaller and more highly integrated, and high-density mounting technology for semiconductor packages has been further developed. For connection between an integrated circuit element (IC, LSI, etc., hereinafter collectively referred to as LSI) and a wiring board of a package, wire bonding connection using a gold wire or flip chip connection using a solder ball or the like is used. ing.

  Wire bonding connection can be packaged at low cost when the number of LSI pads is small. However, as the pitch of LSI pads becomes narrower, it is necessary to reduce the wire diameter, and there is a problem in yield reduction in assembly processes such as wire breakage.

  The flip-chip connection has an advantage that high-speed signal transmission between the LSI and the wiring board is possible compared to the wire bonding connection. However, with the increase in the number of LSI pads and the narrowing of the pitch, the connection strength of the solder bumps is weakened, and defects such as the occurrence of cracks at the connection locations frequently occur.

  Therefore, in recent years, a package technology incorporating an LSI, a so-called LSI built-in technology has been proposed (for example, Patent Documents 1 and 2). This technology is expected as a high-density packaging technology that realizes further high integration and high functionality of semiconductor devices, and realizes package thinning, low cost, high frequency response, low stress connection, improved electromigration characteristics, etc. ing.

  By the way, as an LSI used for such an LSI-embedded technology, an LSI having an external terminal on the premise of wire bonding connection or flip chip connection as described above is used. In an LSI (chip) for wire bonding connection, external terminals are arranged at equal intervals on the outer peripheral edge of the chip, and has a shape suitable for high-speed connection. In the flip chip connection chip, solder bumps constituting external terminals are arranged in an array on one surface of the chip. Each solder bump is formed in the same shape regardless of the amount of current in order to make the solder height constant.

  On the other hand, as one of methods for realizing thinning, miniaturization, and weight reduction of a semiconductor device, there is a CSP technology (Chip Size Package or Chip Scale Package) that brings the semiconductor device close to the size of a semiconductor chip.

  In particular, W-CSP technology (Wafer Level-Chip Size Package or Wafer Level-Chip Scale Package) that does not use a lead frame or mounting substrate can be expected to reduce manufacturing costs and ultimately realize a small package. (For example, Patent Documents 3 to 5).

  In Patent Documents 3 and 4, the dense and small terminal arrangement of LSI is made sparse and large terminals by rewiring using W-CSP technology. Patent Document 5 shows a structure in which LSI contacts and external terminals are connected by a plurality of external electrodes, and a structure in which a plurality of contacts are aggregated by one external electrode and connected to one terminal. It is shown. In either case, the external terminals are formed in the same shape in an array.

  With the W-CPS technology, a small package can be obtained, but only one LSI is packaged. Of course, it seems that if a plurality of LSIs are arranged in parallel at the wafer level, it is possible to manufacture a small package including a plurality of LSIs. However, manufacturing different types of LSIs in parallel at the wafer level has a very poor manufacturing yield. Moreover, it may be difficult to manufacture in parallel due to element characteristics, which is not practical. On the other hand, the LSI built-in technology has an advantage that a plurality of types of LSIs can be packaged. Moreover, it is possible to mount a plurality of LSIs not only in the parallel direction but also in the vertical direction.

JP 2007-134568 A JP 2006-261246 A JP 2002-217377 A JP 2007-13146 A JP 2009-38127 A

  In order to further reduce the thickness of an LSI-embedded substrate, it is necessary to reduce the number of wiring layers. However, in conventional LSIs, connection terminals having the same shape are arranged in an array with a predetermined pitch, and this arrangement is a restriction on the routing of built-in wiring, and it is difficult to reduce the number of wiring layers.

According to one embodiment of the present invention,
An integrated circuit element;
A substrate insulating layer in which the integrated circuit element is embedded;
An integrated circuit element-embedded substrate comprising at least a part of a wiring structure electrically connected to the integrated circuit element,
The integrated circuit element includes a plurality of metal patterns for external connection separated from each other by a surface insulating layer on a surface layer, and the metal pattern has a first planar shape and a first planar shape. Having at least two different shapes with different second planar shapes;
The wiring structure includes a connection via connected to the metal pattern of the integrated circuit element, and a wiring connected to the connection via,
Each of the metal patterns has a connection portion between at least one metal pattern and the connection via, and at least one of the connection portions is formed at a position deviating from an array arrangement of a predetermined pitch, An integrated circuit element-embedded substrate is provided which has the same or different contact area as a connection portion with a connection via.

  According to the present invention, the metal pattern that constitutes the terminal of the built-in LSI has a plurality of different shapes, and the shape and the arrangement are such that the wiring of the built-in board can be easily pulled out, so that the LSI built-in substrate The number of wiring layers inside can be reduced.

It is a schematic sectional drawing which shows an example of a board | substrate with a built-in LSI. It is a top view which shows the terminal arrangement | positioning in a part of conventional LSI surface. It is a schematic perspective view explaining the wiring layer of the board | substrate with a built-in LSI which incorporates the conventional LSI. 2A is a plan view showing a terminal arrangement on a part of an LSI surface according to the first embodiment of the present invention, and FIG. 3B is a schematic cross-sectional view taken along line A-A ′. 1 is a schematic perspective view for explaining a wiring layer of an LSI built-in substrate incorporating an LSI according to a first embodiment of the present invention. It is a schematic sectional drawing which shows an example of LSI based on the 2nd Example of this invention. It is a schematic perspective view which shows the modification (3rd Embodiment) of the terminal arrangement in a part of surface of LSI which concerns on this invention. It is a top view which shows the other modification (4th Embodiment) of the terminal arrangement | positioning in a part of surface of LSI which concerns on this invention. It is a typical top view which shows the aspect of a connection via with the LSI circuit connected to the metal pattern of LSI concerning the present invention. It is a top view which shows the other example of wiring arrangement | positioning of the board | substrate with a built-in LSI which concerns on this invention. 10A is a plan view showing a terminal arrangement on a part of an LSI surface according to a fifth embodiment of the present invention, and FIG. 10B is a schematic sectional view taken along line A-A ′. The top view (a) which shows terminal arrangement in a part of LSI surface concerning the 6th example of the present invention, the schematic sectional view in the AA 'line, and the outline when built in a built-in substrate It is sectional drawing (c). 2 is a partial cross-sectional view illustrating an LSI circuit layer 12. FIG. FIG. 5 is a schematic cross-sectional view illustrating a surface layer 17, where (a) shows an LSI 1A according to a first embodiment, (b) shows an LSI 1C according to a third embodiment, and (c) shows a sixth. 1 shows an LSI 1F according to the embodiment. It is a schematic sectional drawing which shows the structure of LSI which has the back surface layer 17 '. It is a schematic sectional drawing which shows an example of the board | substrate with a built-in LSI which has a multilayer wiring layer. FIG. 17 is a process cross-sectional view illustrating an example of a manufacturing method of the LSI built-in substrate shown in FIG. 16. FIG. 17 is a process cross-sectional view illustrating an example of a manufacturing method of the LSI built-in substrate shown in FIG. 16.

  Hereinafter, an LSI according to the present invention and an LSI-embedded substrate incorporating the LSI will be described by way of specific embodiments, but the present invention is not limited only to these embodiments. The drawings are for facilitating understanding of the invention, and the scale and the like are different from the actual ones.

  FIG. 1 is a schematic cross-sectional view illustrating the structure of a substrate with a built-in LSI. 1 is a built-in integrated circuit element (LSI), 2 is a built-in insulating layer in which LSI 1 is embedded, 3 is a built-in wiring layer, and 4 is a LSI. The connection via connected to the terminal is shown. The internal wiring layer 3 and the connection via 4 constitute a wiring structure. This example shows the simplest structure. If the number of terminals increases due to multifunctional LSIs, a larger number of wiring structures are required.

  For example, consider the case of incorporating a conventional LSI. FIG. 2 is a plan view showing a part of the upper surface of a conventional flip-chip LSI. Terminals T having the same shape are arranged in an array, G is a ground terminal connected to a ground circuit (ground circuit), S is a signal terminal connected to a signal circuit, and S ′ is a signal to improve noise resistance. Signal terminals connected to a circuit (such as a signal circuit that requires high-speed operation or high-frequency operation), V1 and V2 are power supply terminals connected to a power supply circuit (for example, V1 is a 1.2V drive power supply circuit, V2 is 1.. Are respectively connected to the 5V drive power supply circuit). FIG. 3 is a perspective view illustrating the relationship between the LSI 1 and the wiring structure connected to the terminals on the LSI surface in the LSI built-in substrate. As shown in the figure, each signal terminal S is connected to a built-in wiring layer (signal wiring LS) formed on the surface of the first built-in insulating layer 21 via a connection via 41 formed in the first built-in insulating layer 21, respectively. Common wiring is connected to the ground terminal G and the power supply terminals (V1, V2) when they can be used. In order to have a structure in which a part of the ground wiring (LG1) intersects the signal wiring LS, the built-in wiring layer needs to be a separate layer. Also in the signal wiring, for example, in the signal wiring LS ′ for which noise resistance is to be improved, the noise resistance may be impaired due to crosstalk when the signal wiring LS ′ is arranged close to other signal wirings LS. Therefore, it is necessary to draw out such a signal wiring LS ′ in a different layer or a different direction from the other signal wirings LS. In the figure, each signal wiring LS is used as a first built-in wiring layer on the first built-in insulating layer 21, and ground wiring LG 1, LG 2, power supply wiring LV 1, LV 2 is used as a second built-in wiring layer on the second built-in insulating layer 22. , An example in which the signal wiring LS ′ is provided is shown. In addition, since each connection terminal 4 is provided with a connection via 4 to be connected to the wiring layer of the built-in substrate, the connection vias must be densely arranged. As the built-in LSI becomes multifunctional, the number of terminals increases, and it becomes increasingly difficult to route wiring (in this example, the signal wiring LS) while avoiding connection vias. 2 and 3 are created by the inventor in order to explain the problem of the present invention, and are not the structures disclosed in the prior art.

  On the other hand, in the LSI-embedded substrate according to the present invention, the built-in LSI has a metal pattern for external connection having a first planar shape and a second planar shape different from the first planar shape. Each of the metal patterns has a connection portion between at least one metal pattern and the connection via, and at least one of the connection portions is predetermined. It is formed at a position deviating from the array arrangement of the pitch, and is provided so as to have the same or different contact area as the connection portion between the other metal pattern and the connection via. Note that the “position deviating from the array arrangement of a predetermined pitch” does not include a minute deviation from the conventional array arrangement arranged at a predetermined pitch in a linear or lattice shape due to a manufacturing error, and is clearly intended. Thus, the position deviates from the conventional array arrangement. For example, even in a linear or grid arrangement, it means that the pitch is different from the pitch of other connecting portions, or that the linear or grid arrangement is deviated. Further, in the LSI according to the present invention, the metal pattern for external connection of the LSI has a plurality of arbitrary shapes without being limited to a single shape such as a conventional grid shape. The connection portion (connection via formation position) with the wiring structure can be formed at a position deviating from the conventional array arrangement. In particular, the metal pattern is formed so that the connection portion can be formed at a position where it is easier to route the internal wiring than in the case of the conventional array arrangement in consideration of the connection via formation position and the internal wiring extraction direction, interval, width, etc. Design the shape. For example, at least one metal pattern has a structure in which a built-in wiring immediately above that is connected to another metal pattern passes, or built-in wiring layers in a built-in substrate connected to each metal pattern of an LSI. In other words, the shape of the metal pattern is changed so that the three-dimensional intersection is reduced (or eliminated) and the connecting portion is arranged. This facilitates the routing of the built-in wiring in the built-in substrate, and the number of wiring layers can be reduced. Further, the number of connection vias to be formed can be reduced by consolidating each metal pattern connected to a plurality of power supply circuits and ground circuits into one metal pattern. Note that at least one connection portion between the connection via of the built-in substrate and the LSI metal pattern may be formed in one metal pattern, and a plurality of metal patterns having a large planar shape may be provided.

  The configuration of the present invention will be described in detail with reference to the drawings. 4A is a plan view showing a part of the upper surface of the first embodiment of the LSI according to the present invention, and FIG. 4B is a schematic sectional view taken along line AA ′. The circuit configuration is shown in FIG. This is equivalent to the conventional LSI shown in FIG.

  As shown in the figure, each metal pattern 18 has the entire metal pattern 18 protruding and exposed on the LSI surface. In the conventional structure, the ground terminals G that are divided into two rows with the signal terminals S interposed therebetween constitute one large metal pattern as a wiring pattern extending between at least two signal terminals S. At this time, the noise resistance is enhanced by forming the metal pattern 18 to be the ground terminal G in the vicinity of the signal terminal S ′ whose noise resistance is to be improved. In particular, it is preferable to arrange so as to surround half or more of the outer circumferential length, and it may be arranged so as to surround the entire circumference. Of the two types of power supply terminals (V1, V2), the common power supply terminal V1 is grouped into one large metal pattern 18 from the two terminals. Further, a part of the signal terminal S is a metal pattern 18 whose shape is changed from the grid shape of the conventional structure so that the connection via can be formed at a position where the wiring can be easily drawn. Furthermore, the ground circuit and power supply circuit are combined and the area is increased, so that the ground circuit and power supply circuit and the decoupling capacitor immediately below the metal pattern of the LSI shown in FIG. 4 can be formed, improving the power supply noise resistance of the LSI itself. Can be made.

  FIG. 5 shows a state in which the wiring layer of the built-in substrate is formed using the LSI 1A having the terminal shape changed as described above. As shown in the figure, in the conventional structure, the connection vias individually connected to the ground terminals G are set as one connection via and provided at a position different from the drawing direction of the signal wiring LS, so that the signal wiring LS can be easily drawn. ing. The ground terminal G and the power supply terminal V1 are integrated on the LSI 1A, and the ground wiring LG and the power supply wirings LV1 and LV2 can be drawn out to a region that does not intersect with the signal wiring LS. Further, the signal wiring LS ′ connected to the signal terminal S ′ whose noise tolerance is to be improved can be easily pulled out, so that the interval between the adjacent signal wirings LS can be widened. The influence of crosstalk can be reduced even if it is pulled out in the same direction as the signal wiring LS. Further, by arranging the signal wiring LS ′ connected to the signal terminal S ′ so as to pass over the modified ground terminal G, a microstrip structure is formed when the film thickness of the first built-in insulating layer 21 is appropriate. Furthermore, noise resistance can be improved.

  As described above, in the conventional structure (FIG. 3), two built-in wiring layers are formed, but according to the present invention, wiring can be drawn out by one built-in wiring layer.

  In the above example, the metal pattern on the LSI surface layer is described as a terminal, but the terminal here is expressed as a terminal protruding from the outermost insulating layer (passivation film) of the LSI.

As the LSI having such a terminal structure, a newly designed and manufactured LSI may be used, or an existing LSI may be improved. For example, as shown in the schematic cross-sectional view of FIG. 6, a passivation film 13 (general) is formed on the surface of LSI 1 (Si substrate 11, LSI circuit layer 12) having grid array terminals 19 (G, S, V2, etc.) having a conventional structure. Is formed with an inorganic insulating film such as SiON and SiO ₂ , and an organic insulating film such as polyimide, and then a rewiring layer is formed, whereby an existing LSI is formed into a metal pattern according to the second embodiment of the present invention. The LSI 1B having 18 can be improved.

  Note that the shape of the terminals does not have to be an arbitrary shape different from the grid shape (for example, a square shape and an octagonal shape) for all terminals, and may include a grid shape similar to the conventional one. As shown in FIG. 4, when the contour of the exposed shape of the metal pattern includes a linear component, it is preferable that the angle formed by the two connected linear components does not include an acute angle. If the angle formed by the two linear components becomes an acute angle, cracks are likely to occur in the insulating layer (resin layer) of the built-in substrate that comes into contact therewith, and therefore, it is desirable to form it at 90 degrees or more, preferably an obtuse angle or an arc shape. In the example shown in FIG. 4, the corner portion and the bent portion of the ground terminal G have a right angle or a chamfered obtuse angle. Also, when the surface wiring layer of the LSI is formed in an arbitrary shape and a passivation film is provided thereon to form the opening, it is preferable that the opening shape does not include an acute angle.

  The metal pattern (terminal or opening) exposed on the outermost surface can be a curve whose contour changes in curvature. FIG. 7 shows a modified example in which the passivation film 13 is provided on the metal pattern 18 on the surface of the LSI 1C, and the contour of the opening of the passivation film exposing the metal pattern 18 is formed by using a curve whose curvature changes (third embodiment). Example). Note that the underlying metal pattern 18 in this example may be a combination of linear patterns that are easy to form. As described above, in the present invention, it is possible to form a metal pattern (opening) having an arbitrary shape using only a curve other than a combination with a straight line. In this example, the opening shape is described, but a metal pattern having a terminal structure may be used.

  In the above example, the metal pattern is unified with the terminal structure protruding from the element surface and the opening structure retreating from the element surface, but may be a combination of both. For example, the metal pattern connected to the signal circuit has a terminal structure, the metal pattern connected to the power supply circuit and the ground circuit has an opening structure, and the connection via of the built-in substrate connected to the signal circuit is a via with a small diameter. The connection via connected to the circuit and the ground circuit may be connected with a via having a large diameter.

  In the built-in wiring layer in the built-in substrate, a larger current flows in the ground wiring and the power supply wiring than in the signal wiring. Therefore, as shown in FIGS. 3 and 5, the ground wiring and the power supply wiring are preferably wiring having a larger cross-sectional area than the signal wiring. This can also be said for the connection via 41 and the terminal on the surface of the LSI. Conventionally, the connection via and signal terminal of the signal wiring are matched to the via diameter and terminal shape suitable for the power supply terminal and the ground terminal. That is, the connection via and the signal terminal of the signal wiring are formed in a shape larger than the required via diameter and terminal shape. As a result, the number of signal terminals is limited by the chip size, which is a factor that hinders further multifunctionalization, lightness, and shortening. On the other hand, in the LSI according to the present invention, when newly designed and manufactured, the shape of the signal terminal can be made smaller than before, so that it is possible to make the LSI more multifunctional, lighter and thinner. . The average area of the metal pattern 18 connected to the power supply or ground circuit is preferably larger than the average area of the metal pattern 18 connected to the signal circuit, and the minimum of the metal pattern 18 connected to the power supply or ground circuit. The area is preferably equal to or greater than the maximum area of the metal pattern 18 connected to the signal circuit. In particular, it is preferable that there is at least one metal pattern 18 connected to a power supply or ground circuit that is twice or more the maximum area of the metal pattern 18 connected to the signal circuit. Further, the metal pattern 18 can be arranged arbitrarily in the LSI surface layer, but it is preferable that the distance between the metal patterns closest to each other is not narrowed toward the center of the plane of the device. Further, regarding the via diameter, when ground wiring and power supply wiring are aggregated, a larger amount of current flows, and it is preferable to increase the via diameter or share a plurality of vias in order to adjust impedance. There is a case.

  For example, FIG. 8 is a plan view of an LSI 1D according to the fourth embodiment of the present invention, and shows an example in which the signal terminals S are made smaller and denser than in the prior art. Further, the power supply terminals (V1, V2) and the ground terminal G are equal to or larger than the conventional ones. For example, the ground terminals G in the signal wiring drawing direction are collectively set as large terminals so that the connection via formation position (black circle portion) does not collide with the wiring drawing direction. In such a newly manufactured LSI, since the signal terminal shape can be reduced, the number of terminals within the same area can be increased, and wiring drawing can be facilitated by devising other terminal shapes. As a result, it is possible to make the LSI more multifunctional, lighter and thinner.

  Further, in the conventional LSI, since the grid terminals are arranged in an array, it is necessary to carefully design the layout of the wiring under the LSI terminals (an LSI circuit layer 12 described later). In the case of newly manufacturing, since the degree of freedom of terminal arrangement is increased, the LSI itself can be easily designed.

  For example, FIG. 9 is a schematic plan view showing an aspect of the connection via 16 with the LSI circuit connected to the metal pattern (terminal). At least some of the terminals (for example, the ground terminal G and the power supply terminal V1) can have a plurality of connection points with the lower terminal wiring of the LSI. In this example, the connection vias 16 are evenly arranged, but they need not be evenly arranged. As a result, the degree of freedom of LSI design is improved. Note that the connection via 16 in FIG. 9 is shown larger than the actual size for easy understanding.

  A further modification of the present invention will be described. In the example shown in FIG. 3 and FIG. 4 described above, the signal wiring LS ′ connected to the signal terminal S ′ is arranged so as to pass over the modified ground terminal G. However, the wiring passing over the ground terminal G is It is not limited only to such signal wiring LS ′, but other wiring may pass over the ground terminal G. For example, as shown in FIG. 10, the power supply line LV2 and the ground terminal G overlap to increase the capacitor capacity that functions as decoupling, thereby improving the operational stability of the LSI.

  In the example shown in FIG. 4 described above, the metal pattern 18 is shown in a form in which it protrudes and is exposed entirely on the surface of the LSI 1A. It may be a form.

  FIG. 11A is a plan view showing an LSI 1E according to the fifth embodiment of the present invention, and FIG. As shown in the figure, the metal pattern 18 has a shape in which part of the metal pattern 18 protrudes from the element surface. In this example, the post electrode 18A also serves as the connection via 41 in the built-in substrate. The present invention is not limited to this, and a conventional grid terminal shape may be used. In this case, even if the terminal shape is a conventional grid terminal shape, it suffices if the arrangement is such that at least one terminal deviates from the conventional array arrangement. In this example, the case where the diameters of the post electrodes 18A are different for impedance adjustment with respect to the metal patterns 18 to be connected to each other is shown, but the present invention is not limited to this. The size and arrangement of the exposed portion of the metal putter 18 may be appropriately selected within the prescribed range of the present invention in consideration of the connection with the wiring structure of the built-in substrate.

  In the above embodiments, the metal pattern 18 for external connection of the LSI has been shown to be at least partially exposed to the outside. However, the LSI according to the present invention is assumed to be built in the built-in substrate. Therefore, it is possible to use a metal pattern 18 that is not exposed to the outside.

  12A and 12B show an LSI 1F according to the sixth embodiment in which the metal pattern 18 is not exposed. FIG. 12A is a plan view, FIG. 12B is a cross-sectional view taken along the line AA ′, and FIG. ) Shows a cross-sectional view when built in a built-in substrate. As shown in the plan view of FIG. 4A, the metal pattern 18 is formed in the same pattern as that shown in FIG. 4 except that it is not exposed on the element surface. When the via hole for the connection via 41 is formed in the first built-in insulating layer 21 when it is built in the built-in substrate, the via hole is formed through the surface insulating layer 14 of the LSI 1F to expose the metal pattern 18. Then, by forming the connection via 41 and the first built-in wiring layer 31, the LSI 1F and the wiring structure of the built-in substrate can be connected. By using the LSI 1F in which the metal pattern 18 is not exposed on the element surface in this way, the problem that cracks are likely to occur in the insulating layer (resin layer) of the built-in substrate is solved.

Next, an LSI manufacturing method according to the present invention will be described.
The inventors of the present invention have previously proposed a technique for reducing the number of LSI terminals by consolidating common wiring systems in Japanese Unexamined Patent Application Publication No. 2009-71045. However, also in this proposal, terminals for external connection are arranged in an array. In the present invention, this technique can be used to form the metal pattern of the surface layer into a plurality of arbitrary shapes and / or arrangements as shown in the above embodiment.

  FIG. 13 is a partial cross-sectional view schematically showing the configuration of the LSI circuit layer 12 according to the above embodiment of the present invention. Referring to FIG. 13, in the LSI circuit layer 12, first, a source electrode 122 and a drain electrode 123 are formed on the surface of the semiconductor substrate 11 so as to be separated from each other. A gate electrode 121 is formed on the sandwiched channel region via a gate insulating film (not shown). These gate electrode 121, source electrode 122 and drain electrode 123 constitute a MOS (Metal Oxide Semiconductor) transistor 124. A plurality of MOS transistors 124 are provided on the semiconductor substrate 11.

  A first insulating layer 127 covered with an insulating film 129 is formed on the surfaces of the MOS transistor 124 and the semiconductor substrate 11. A plug 125 connected to the source electrode 122 and the drain electrode 123 is formed on the first insulating layer 127 on the semiconductor substrate 11. A first wiring layer 126 is provided on the first insulating layer 127. The first wiring layer 126 includes a wiring 128 and an insulating film 129. The wiring 128 is electrically connected to the source electrode 122 and the drain electrode 123 by a plug 125 formed in the first insulating layer 127, respectively. Further, a first insulating layer 127 is provided on the first wiring layer 126, and the first wiring layer 126 is provided thereon. The first insulating layer 127 includes an insulating film 129 and a first via 130. The wirings 128 of the upper and lower first wiring layers 126 of the first insulating layer 127 are electrically connected by corresponding first vias 130. Furthermore, the LSI circuit layer 12 is configured by alternately stacking the first insulating layers 127 and the first wiring layers 126.

  The wiring 128 and the first via 130 of the LSI circuit layer 12 are mainly made of copper or aluminum, for example, and can be formed by a damascene method, for example. In the damascene method, a trench (trench) is formed in the insulating film in the shape of a desired wiring pattern or via pattern by dry etching, a barrier metal and a power supply layer (not shown) for electrolytic plating are sputtered, and CVD (Chemical Vapor Deposition) ) Method, ALD (Atomic Layer Deposition) method, etc., and after filling the trench with copper by electrolytic copper plating, leave copper only in the trench (trench) by CMP (Chemical Mechanical Polishing) method This is a method for obtaining a desired wiring.

  The thickness of the first insulating layer 127 is, for example, 0.2 to 1.6 μm. In addition, among the plurality of first insulating layers 127, it is desirable that at least one first insulating layer 127 provided near the semiconductor substrate 11 uses a low-k material. As a low-k material, for example, a porous silicon oxide film is used, and its elastic modulus at 25 ° C. is 4 to 10 GPa.

  As shown in FIG. 14, an insulating passivation film 13 made of an inorganic material or an organic material is provided on the LSI circuit layer 12, and a second wiring layer 15 and a second insulating layer 14 are provided thereon. ing. The wiring on the surface of the second wiring layer 15 and the LSI circuit layer 12 (128 in FIG. 13) is electrically connected through the third via 119. Further, the second insulating layer 14 and the second wiring layer 15 are alternately stacked to form the surface layer 17. The plurality of second wiring layers 15 are electrically connected by second vias 16 provided in the second insulating layer 14. On the outermost second insulating layer 14 (passivation film 13), a metal pattern 18 serving as an external terminal is provided. The metal pattern 18 is electrically connected to the second wiring layer 15 through the corresponding second via 16. The metal pattern 18 is provided similarly to the second wiring layer 15 and is patterned into the shape and arrangement shown in the above embodiment. That is, the second wiring layer 15 on the outermost surface becomes the metal pattern 18. 14A shows an LSI 1A according to the first embodiment, FIG. 14B shows an LSI 1C according to the third embodiment, and FIG. 14C shows an LSI 1F according to the sixth embodiment. Shows the case. In the present invention, the passivation film 13 and the second insulating layer 14 are not distinguished from each other, and means that the end surface of the wiring layer formation is the passivation film 13.

  The second wiring layer 15 can be made of copper, for example, and the thickness thereof can be 5 μm. The second wiring layer 15 is formed by a wiring forming method different from the LSI circuit layer 12 such as a subtractive method, a semi-additive method, and a full additive method. The subtractive method is a method in which a resist obtained by forming a copper foil provided on a substrate or a resin in a desired pattern is used as an etching mask, and after the etching is performed, the resist is removed to obtain a desired wiring pattern. In the semi-additive method, a power supply layer is formed by electroless plating, sputtering, CVD, etc., then a resist with a desired pattern is formed, electrolytic plating is deposited in the resist openings, and power is supplied after removing the resist. In this method, a desired wiring pattern is obtained by etching a layer. In the full additive method, an electroless plating catalyst is adsorbed on the surface of a substrate or resin, a pattern is formed with a resist, and the catalyst is activated while leaving the resist as an insulating layer. In this method, a desired wiring pattern is obtained by depositing metal on the portion.

  Further, the second wiring layer 15 and the metal pattern 18 may have an adhesion layer (not shown) between the passivation film 13 or the second insulating layer 14 in contact with the semiconductor substrate 11 side. The adhesion layer may be a material having adhesion to the material of the passivation film 13 or the second insulating layer 14, such as titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum, or an alloy thereof. Of these, titanium, tungsten, tantalum, chromium, molybdenum and alloys thereof are preferable, and titanium, tungsten and alloys thereof are most preferable. Furthermore, the surface of the passivation film 13 or the second insulating layer 14 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Furthermore, it is preferable to form by means of sputtering as a means for increasing the adhesion. Due to the presence of an adhesion layer between the second via 16 and the metal pattern 18 or the second wiring layer 15 and the bonding area between the second via 16 and the metal pattern 18 or the second wiring layer 15, When the area of the adhesion layer of the second wiring layer 15 is large, the second insulating layer 14 including the periphery of the second via is corrected to the metal pattern 18 and the second wiring layer 15. Therefore, the metal pattern 18 around the adhesion layer, the second wiring layer 15, the second via 16, and the second insulating layer 14 move in substantially the same direction, so that the second via 16, the metal pattern 18, and the second The joint interface with the wiring layer 15 is less deformed, and even the second via 16 having a small via diameter can effectively prevent breakage at the joint interface.

  The second wiring layer 15 is configured to be thicker than the first wiring layer (126 in FIG. 13) of the LSI circuit layer 12. The thickness of the second wiring layer 15 is, for example, 3 to 12 μm, and 5 to 10 μm is particularly suitable. When the thickness is 3 μm or more, the wiring resistance is increased and the electrical characteristics of the power supply circuit in the LSI are not deteriorated. If the thickness is 12 μm or less, there is no limitation on the number of layers due to the occurrence of large undulations reflecting the irregularities of the wiring layer on the surface of the second insulating layer 14 covering the second wiring layer 15. Warpage of the entire LSI due to an increase in the thickness of the layer 17 itself is suppressed. The thickness of the metal pattern 18 may be equal to that of the second wiring layer 15 or may be thicker than that of the second wiring layer 15. For example, when an insulating layer is provided on the metal pattern 18, the surface of the insulating layer is not necessarily flat, and a shape reflecting the unevenness of the metal pattern 18 may be formed on the LSI surface.

  The second insulating layer 14 (passivation film 13) is made of, for example, an organic material. For example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole) and polynorbornene resin. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. The organic material may be either photosensitive or non-photosensitive. By using an organic material for the second insulating layer 14, stress applied to the inside of the LSI from the metal pattern 18 when the LSI is built in the built-in substrate is relieved mainly by deformation of the second insulating layer 14, and the LSI circuit layer The stress propagation to 12 can be effectively reduced.

  The surface of the metal pattern 18 is, for example, at least selected from the group consisting of copper, aluminum, gold, silver, and a solder material in consideration of connectivity with the connection via of the embedded substrate connected to the surface of the metal pattern 18. It can be formed of a kind of metal and alloy. From the viewpoint of cost, it is preferably composed of only copper. In addition, the metal pattern 18 can have a configuration in which a plurality of layers are laminated. For example, a nickel layer and a gold layer are laminated on a copper layer, and the gold layer is a surface. Can be 3 μm, and the thickness of the gold layer can be 1 μm.

  In FIG. 14, the second insulating layer 14 and the second wiring layer 15 are shown as two layers each, but the present invention is not limited to this, and the number of layers may be configured as necessary. Further, the second wiring layer 15 may constitute the metal pattern 18 as a single layer. In FIG. 13, the first wiring layer 126 and the first insulating layer 127 are each shown as eight layers. However, the number of layers is not limited to this, and the number of layers may be configured as necessary.

  The material of the first wiring layer 126 and the second wiring layer 15 is made of at least one metal selected from the group consisting of copper, aluminum, nickel, gold, and silver, for example. In particular, copper is preferable from the viewpoint of electrical resistance value and cost. Further, nickel can prevent an interface reaction with other materials such as an insulating material, and can be used as an inductor or a resistance wiring utilizing characteristics as a magnetic material.

  Since the thickness of the second wiring layer 15 of the surface layer 17 is twice or more that of the first wiring layer 126 of the LSI circuit layer 12, it has an allowable current amount of at least twice or more. For this reason, in the second wiring layer 15 of the surface layer 17, a plurality of power supply system wirings and ground system wirings using the same voltage can be bundled into one wiring. By combining these plural wirings into one, the number of electrical connection points between the surface layer 17 formed on the surface of the LSI circuit layer 12 and the second wiring layer 15 is reduced, and a part of the metal pattern 18 is connected to the via 16. By forming a plurality of connection points, the number of surface terminals can be further reduced.

  The minimum design rule of the first wiring layer 126 in the LSI circuit layer 12 of the LSI is preferably: wiring width / wiring interval (L / S) = 0.01 μm / 0.01 μm. It is preferable that the width is 0.01 μm or more and the minimum wiring interval is 0.01 μm or more.

  The minimum design rule of the second wiring layer 115 of the surface layer 17 is preferably L / S = 2 μm / 2 μm, that is, the second wiring layer 115 has a minimum wiring width of 2 μm or more and a minimum wiring interval. It is preferable that it is 2 micrometers or more.

  The thickness of the built-in wiring (third wiring layer) of the built-in substrate is preferably set to be larger than the set thickness of the second wiring layer. The minimum design rule for the internal wiring of the internal substrate is preferably L / S = 5 μm / 5 μm, that is, the internal substrate wiring has a minimum wiring width of 5 μm or more and a minimum wiring interval of 5 μm or more. Is preferred.

  As described above, there is a design rule difference in the wiring width and thickness, and therefore, a difference occurs in the wiring capacitance and the resistance value. Also, with respect to the insulating layer, the insulating layer (third insulating layer) of the built-in substrate is thicker, so that the parasitic capacitance can be reduced.

  The ability to consolidate power supply and ground increases as the wiring capacitance increases and the resistance value decreases, so the wiring width and thickness are as follows: Built-in substrate (third wiring layer)> Surface layer (second wiring layer)> LSI circuit layer It is preferable to satisfy the relationship of (first wiring layer). On the other hand, in order to obtain a capacitance with a capacitor (for example, a decoupling capacitor configured between a power source and a ground) configured using an insulating layer sandwiched between wiring layers, the dielectric constant of the insulating layer is high, Since a thinner thickness is advantageous, the relationship of the dielectric constant and thickness of the insulating layer satisfies the relationship of LSI circuit layer (first insulating layer)> surface layer (second insulating layer)> built-in substrate (third insulating layer). It is preferable.

  In the above embodiment example, the configuration in which the metal pattern 18 is provided only on one side of the LSI (the surface side on which the LSI wiring layer 12 is formed) is shown. However, in the present invention, the other side (LSI wiring layer 12 is formed on the opposite side). A surface layer 17 ′ having a metal pattern 18 ′ may also be formed on the rear surface facing the front surface side. FIGS. 15A to 15C show modifications of the LSIs 1A, 1C, and 1F shown in FIG. 14, respectively. LSIs 1A ′, 1C ′, and 1F ′ having a surface layer 17 ′ formed on the back surface. FIG. The second wiring layer 15 ′ and the metal pattern 18 ′ in the surface layer 17 ′ do not have to be the same pattern as the second wiring layer 15 and the metal pattern 18 in the surface layer 17. What is necessary is just to adjust suitably considering drawer | drawing-out. The electrical connection to the back surface layer 17 ′ side is provided with the through-substrate via 60 in these examples, but is not limited thereto, and may be connected by providing a wiring layer on the side surface of the LSI. Since the connection length is shortened, it is preferable to connect via the substrate through via 60. By providing such a through-substrate via 60 and effectively utilizing the back surface, the number of terminals can be further reduced, and the wiring structure of the built-in substrate can be easily routed. Furthermore, heat dissipation and noise shield characteristics can be further improved. When such a back surface layer 17 ′ is provided, at least one of the metal pattern 18 of the surface layer 17 and the metal pattern 18 ′ of the back surface layer 17 ′ may be any shape or arrangement pattern as described above. Further, the exposed form of the metal patterns 18 and 18 ′ (exposed in a convex shape, exposed in a concave shape or not exposed) does not need to be the same, considering the wiring structure of the built-in substrate formed on the front side and the back side. What is necessary is just to select suitably.

  Finally, another example of the LSI-embedded substrate according to the present invention is shown. FIG. 16 shows a case where the built-in wiring layer is formed in multiple layers. In the figure, reference numerals 21 to 26 denote first to sixth built-in insulating layers, 31 to 36 denote first to sixth built-in wiring layers, 41 to 45 denote connection vias, 51 denotes a passivation film, and 52 denotes an external substrate. A ball grid is shown. In this example, the case of having six wiring layers is described, but this is a fan-out from an LSI by using multilayer wiring. As described with reference to FIG. 5, by using the LSI 1A according to the present invention, it is possible to reduce one or more wiring layers as compared with the case of using the conventional LSI 1 having arrayed terminals. It is.

  The first to sixth built-in insulating layers 21 to 26 can be formed using, for example, a photosensitive or non-photosensitive organic material. As the organic material, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), and polynorbornene resin can be applied. Moreover, you may use the material which impregnated the woven fabric and nonwoven fabric formed with the glass cloth, the aramid fiber, etc. with at least 1 sort (s) of resin chosen from these resin groups. Moreover, you may use what added the inorganic filler and the organic filler to the resin etc. which are chosen from these resin groups, or a silicon resin. Of course, the present invention is not limited to these, and various materials including inorganic materials can be applied without departing from the spirit of the present invention.

  The LSI 1A can be fixed by providing an adhesive layer. For example, a semi-cured resin called Die Attachment Film (DAF), epoxy resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), etc. The resin paste or silver paste is suitable. Of course, it is not limited to these.

  The connection via 41 is formed by filling a via hole penetrating from the surface of the first built-in insulating layer 21 to the metal pattern 18 (not shown) of the LSI 1 with a conductor. The connection via 41 can be formed simultaneously with the formation of the first built-in wiring layer 31 by forming a via hole in the first built-in insulating layer 21 with a laser, for example. Further, as shown in FIG. 11, by using a part of the metal pattern 18 as a post electrode, this can be suitably applied as the connection via 41.

  The first internal wiring layer to the sixth internal wiring layers 31 to 36 are, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium, or An alloy containing these as a main component or a conductive resin made of a resin containing a conductive filler is suitable, but is not limited thereto. From the viewpoint of electrical resistance value and cost, it is desirable to form with copper.

  The thickness, width, wiring interval, etc. of each built-in wiring layer are appropriately set according to the design rules as described above.

  Next, an example of a method for manufacturing an LSI-embedded substrate will be described with reference to the manufacturing process cross-sectional views of FIGS. 17 (a) to 18 (g).

  First, the fourth built-in wiring layer 34 is formed on the main surface of the support body 50 (see FIG. 17A). Then, the support body 50 and the sixth built-in wiring layer 34 are covered with the fourth built-in insulating layer 24 (see FIG. 17B). As the support 50, any one of resin, metal, glass, semiconductor, ceramic, or a combination thereof can be used. Further, in order to clarify the position where the LSI 1A is mounted, a position mark (not shown) may be appropriately provided on the support 50.

  Next, an LSI 1A according to the present invention is prepared. Then, the LSI 1A is mounted on the upper layer of the support 50 at a predetermined position (see FIG. 17B). Thereafter, the first built-in insulating layer 21 is formed so as to cover the fourth built-in insulating layer 24 and the LSI 1A (see FIG. 17C). The LSI 1A is mounted on the support 50 using a semiconductor mounting machine in a face-up state.

  The first built-in insulating layer 21 is formed so as to bury the LSI 1A. Further, the first built-in insulating layer 21 disposed around the LSI 1A may include a reinforcing layer made of a resin layer reinforced with glass cloth or the like, and when such a reinforcing layer is included, the LSI 1A mounting portion Alternatively, the first built-in insulating layer 21 may be formed by pasting together those that have been opened by punching or the like and then filling with a filling resin.

  Subsequently, a via hole 41A penetrating from the surface of the first built-in insulating layer 21 to the surface of the metal pattern 18 (not shown) of the LSI 1A is provided. At the same time, a via hole 42A penetrating from the surface of the first built-in insulating layer 21 to the surface of the fourth built-in wiring layer 34 is formed (see FIG. 17D). For example, the via holes 41A and 42A can be formed using a laser processing method. When using an LSI in which the post electrode 18A is formed like the LSI 1E shown in FIG. 11, the formation of the via hole 41A is not necessary. When the metal pattern 18 is not exposed on the element surface as in the LSI 1F shown in FIG. 12, the via hole 41A is formed so as to penetrate the surface insulating layer on the element surface. Unlike the case of an LSI having a conventional array grid, the via hole 41A is, for example, aligned on an XY stage based on the arrangement information of the metal pattern 18 of the LSI according to the present invention to be used. The via hole 41A may be formed at a position where the wiring can be easily pulled out by laser irradiation or the like.

  Next, a conductor is formed inside the via holes 41A and 42A, and the first built-in wiring layer 31 is formed on the first built-in insulating layer 21 (see FIG. 18E). By filling the via hole 41A with a conductor, the connection via 41 is formed, and by filling the via hole 42A with a conductor, the first built-in insulating layer through via 42 is formed.

  Further, the first built-in insulating layer 21 and the first built-in wiring layer 31 are covered with the second built-in insulating layer 22, and the connection via 43 and the second built-in wiring layer 32 are formed in the same manner. Further, the second built-in insulating layer 22 and the second built-in wiring layer 32 are covered with the third built-in insulating layer 23, and the connection via 44 and the third built-in wiring layer 33 are similarly formed (see FIG. 18E).

  Thereafter, the support 50 is removed. In the case of a support made of a copper alloy, the support 50 can be removed using an alkaline wet etching solution.

  After the support 50 is removed, the fifth built-in insulating layer 25, the connection via 45, the fifth built-in wiring layer 35, the sixth built-in insulating layer 26, the connection via 46, and the sixth built-in wiring layer are formed on the fourth built-in wiring layer 34. 36 is formed in the same manner as described above (see FIG. 18F).

  Finally, a passivation film 51 such as a solder resist having an opening is formed on the sixth built-in wiring layer 36, and a ball grid 52 such as BGA connected to the sixth built-in wiring layer 36 is formed on the passivation film 51 side. Through the above-described steps and the like, the LSI built-in substrate shown in FIG.

1 Integrated circuit elements (LSI)
1A to 1F LSI according to the present invention
DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 LSI circuit layer 13 Passivation film 14 2nd insulating layer 15 2nd wiring layer 16 Under-terminal connection via 17 Surface layer 18 Metal pattern 2 Built-in insulating layer 21 1st built-in insulating layer 22 2nd built-in insulating layer 23 3rd Built-in insulating layer 24 Fourth built-in insulating layer 25 Fifth built-in insulating layer 26 Sixth built-in insulating layer 3 Built-in wiring layer 31 First built-in wiring layer 32 Second built-in wiring layer 33 Third built-in wiring layer 34 Fourth built-in wiring layer 35 Fifth built-in wiring layer 36 Sixth built-in wiring layer 4 Connection via 41 Element connection via 42 Built-in insulating layer through via 43 to 45 Wiring interlayer connection via 51 Passivation film 52 Ball grid 50 Support substrate 60 Through-substrate via

Claims (35)

An integrated circuit element;
A substrate insulating layer in which the integrated circuit element is embedded;
An integrated circuit element-embedded substrate comprising at least a part of a wiring structure electrically connected to the integrated circuit element,
The integrated circuit element includes a plurality of metal patterns for external connection separated from each other by a surface insulating layer on a surface layer, and the metal pattern has a first planar shape and a first planar shape. Having at least two different shapes with different second planar shapes;
The wiring structure includes a connection via connected to the metal pattern of the integrated circuit element, and a wiring connected to the connection via,
Each of the metal patterns has a connection portion between at least one metal pattern and the connection via, and at least one of the connection portions is formed at a position deviating from an array arrangement of a predetermined pitch, A substrate with a built-in integrated circuit element, which is provided so as to have the same or different contact area as a connection portion with a connection via.   2. The integrated circuit element built-in according to claim 1, wherein the connection portion is provided at a position where a first wiring connected to each metal pattern through a connection via can be drawn without intersecting each other according to a predetermined design rule. substrate.   2. The integrated circuit element-embedded substrate according to claim 1, wherein a first wiring connected to another metal pattern via a connection via passes on the at least one metal pattern.   2. The integrated circuit element built-in substrate according to claim 1, wherein at least one of the metal patterns has a wiring pattern extending between at least two of the other metal patterns.   The metal pattern in the integrated circuit element is exposed on the surface of the element before being incorporated, and a connection portion with the connection via is disposed in the exposed portion. An integrated circuit element built-in substrate according to claim 1.   6. The integrated circuit element-embedded substrate according to claim 5, wherein an area of the exposed portion in one metal pattern of the integrated circuit element is different from an area of the exposed portion in another metal pattern.   The integrated circuit element is not exposed before the metal pattern is covered with the surface insulating layer before being embedded, and an opening for forming the connection via penetrates the substrate insulating layer and the surface insulating layer. 5. The integrated circuit element built-in substrate according to claim 1, wherein a connection portion of the metal pattern is formed.   7. The integrated circuit element-embedded substrate according to claim 5, wherein the connection portion of the metal pattern is a part of a terminal pattern protruding and exposed from a surface insulating layer of the integrated circuit element.   The integrated circuit element-embedded substrate according to claim 8, wherein all of the metal pattern protrudes from the surface insulating layer and is exposed.   7. The integrated circuit element built-in substrate according to claim 5, wherein the metal pattern is exposed in an opening pattern opened in a surface insulating layer of the integrated circuit element, and a part of the metal pattern constitutes a connection portion.   11. The integrated circuit element-embedded substrate according to claim 8, wherein an outline of the exposed portion of the metal pattern includes a linear component, and an angle formed by two connected linear components does not include an acute angle.   11. The integrated circuit element-embedded substrate according to claim 8, wherein an outline of the exposed portion of the metal pattern is configured by a curve with a changing curvature.   13. The integrated circuit according to claim 1, wherein metal patterns connected to at least one circuit of the integrated circuit element are aggregated into a pattern having a larger area than a metal pattern connected to another circuit. Circuit element built-in substrate.   The metal pattern is connected to the signal circuit, power supply circuit, and ground circuit of the integrated circuit element, respectively, and the maximum area of the metal pattern connected to the signal circuit is the maximum of the metal pattern connected to the power supply circuit or the ground circuit. The integrated circuit element built-in substrate according to claim 1, wherein the substrate is smaller than the area.   The substrate with a built-in integrated circuit element according to claim 14, wherein a part of the metal pattern connected to the ground circuit is disposed in proximity to at least one of the metal patterns connected to the signal circuit.   The wiring in the wiring structure connected to either the metal pattern connected to the signal circuit or the metal pattern connected to the power supply circuit is arranged at a position passing over the metal pattern connected to the ground circuit. The integrated circuit device-embedded substrate according to claim 14 or 15.   The integrated circuit element-embedded substrate according to claim 1, wherein at least one of the metal patterns has a plurality of connection portions with circuit wirings under the metal pattern.   18. The integrated circuit element built-in according to claim 1, wherein the metal pattern is formed by forming a rewiring layer on a surface of an integrated circuit element having external terminals arranged in a straight line or a lattice. substrate.   19. The integrated circuit element built-in substrate according to claim 1, wherein the metal pattern is formed on a surface side of the integrated circuit element on which a circuit pattern is formed.   The integrated circuit element-embedded substrate according to any one of claims 1 to 19, wherein the metal pattern is formed on both a surface side on which a circuit pattern of the integrated circuit element is formed and a back surface side facing the surface. A semiconductor element embedded in an integrated circuit element embedded substrate,
The surface layer includes a plurality of metal patterns for external connection, separated from each other by a surface insulating layer,
The metal pattern has at least two shapes of a first planar shape and a second planar shape different from the first planar shape,
Each of the metal patterns is at least partially exposed on the surface of the element, and the total area of the exposed portions in one metal pattern is different from the total area of the exposed portions in the other metal patterns. Circuit element. A semiconductor element embedded in an integrated circuit element embedded substrate,
The surface layer includes a plurality of metal patterns for external connection, separated from each other by a surface insulating layer,
The metal pattern has at least two shapes of a first planar shape and a second planar shape different from the first planar shape,
Each of the metal patterns is exposed at least partially on the surface of the element, and the arrangement of the exposed portions is an arrangement deviated from the array arrangement of a predetermined pitch. A semiconductor element embedded in an integrated circuit element embedded substrate,
The surface layer includes a plurality of metal patterns for external connection, separated from each other by a surface insulating layer,
The metal pattern has at least two shapes of a first planar shape and a second planar shape different from the first planar shape,
The integrated circuit device, wherein the metal pattern is covered with a surface insulating layer and is not exposed.   23. The integrated circuit device according to claim 21, wherein the exposed portion of the metal pattern has a shape protruding from a surface insulating layer.   25. The integrated circuit device of claim 24, wherein all of the metal pattern protrudes from the surface insulating layer to form an exposed portion.   23. The integrated circuit element according to claim 21, wherein the exposed portion of the metal pattern is a pattern receding from an upper surface of the surface insulating layer in an opening pattern opened in the surface insulating layer of the semiconductor element.   27. The integrated circuit device according to claim 21, wherein an outline of the exposed portion of the metal pattern includes a linear component, and an angle formed by two connected linear components does not include an acute angle.   27. The integrated circuit device according to claim 21, wherein an outline of the exposed portion of the metal pattern is configured by a curve with a changing curvature.   29. The integrated circuit device according to claim 21, wherein at least one of the metal patterns has a wiring pattern extending between at least two of the other metal patterns.   30. The integrated circuit element according to claim 21, wherein metal patterns connected to at least one type of circuit are aggregated into a pattern having a larger area than metal patterns connected to other circuits.   The metal pattern is connected to the signal circuit, the power supply circuit, and the ground circuit, respectively, and the maximum area of the metal pattern connected to the signal circuit is smaller than the maximum area of the metal pattern connected to the power supply circuit or the ground circuit. The integrated circuit device according to claim 30.   32. The integrated circuit device according to claim 31, wherein a part of the metal pattern connected to the ground circuit is disposed in proximity to at least one of the metal patterns connected to the signal circuit.   The integrated circuit element according to any one of claims 21 to 32, wherein at least one of the metal patterns has a plurality of connection portions with circuit wiring under the metal pattern.   34. The integrated circuit element according to claim 21, wherein the metal pattern is formed on a surface side of the integrated circuit element on which a circuit pattern is formed.   34. The integrated circuit element according to any one of claims 21 to 33, wherein the metal pattern is formed on both a surface side on which a circuit pattern of the integrated circuit element is formed and a back side opposite to the surface side.