JP3462385B2 - Multilayer circuit board - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board for mounting an electronic component such as a semiconductor chip having connection electrodes arranged in a grid pattern or a semiconductor device having external connection terminals arranged in an area array.

[0002]

2. Description of the Related Art In recent semiconductor devices, logic devices have become more sophisticated and have higher densities, and the number of inputs / outputs has increased to further increase the packaging density. For this reason, products have been provided in which the electrodes are arranged in a grid pattern on the electrode formation surface of the semiconductor chip to compensate for the lack of space for forming the electrodes.
FIG. 6 shows a semiconductor chip 4 by a normal flip chip connection.
This is an example in which is mounted on the circuit board 5. This semiconductor chip 4
Is an array of electrodes 6 on the periphery, and all the electrodes 6 and the circuit pattern 7 are connected on one plane.

FIG. 7 shows an example of forming a land 8 and a circuit pattern 7 provided on a circuit board on which a semiconductor chip is mounted. In this example, the lands 8 are arranged in two rows, and the circuit patterns 7 connected to the inner lands 8 are drawn out from the middle of the adjacent lands 8 on the outer side to draw the circuit patterns 7 from all the lands 8 on one plane. . However, when the electrodes are arranged in a large number of rows on the electrode formation surface, it becomes impossible to draw the wiring from all the lands on one plane, depending on the land interval and the number of lands.

As a method of solving such a problem, a circuit board on which semiconductor chips are mounted is formed in multiple layers, and a circuit pattern is appropriately arranged on each circuit board to be laminated so that the circuit pattern is provided on all electrodes of the semiconductor chip. There is a way to connect. FIG. 8 shows an example in which a semiconductor chip 4 having a large number of electrodes 6 arranged in a grid pattern is mounted on a multilayer circuit board.
If such a multilayer circuit board is used, all the electrodes 6 arranged in a grid pattern and the circuit patterns 7 and 7a can be electrically connected to each other to electrically connect the external connection terminals 9 to the electrodes 6. . In the figure, 7a is a circuit pattern of the inner layer, 5a-
5d is a circuit board of the 1st layer-4th layer.

[0005]

As described above, when a semiconductor chip in which electrodes are arranged in a grid pattern is mounted on a circuit board and the number of electrodes is not so large, a multilayer circuit board in which two or more circuit boards are laminated is provided. It ’s enough, but 30 × 30
When mounting a semiconductor chip in which an extremely large number of electrodes such as pins and 40 × 40 pins are mounted, 6 to 1
A large number of layers, such as 0 layers, will be required.

In the case of forming a multilayer circuit board by laminating circuit boards on which circuit patterns are formed with high density, a high density wiring method such as a build-up method is used. However, in the manufacture of a multilayer circuit board, there are major problems in terms of product yield, reliability, and manufacturing cost. That is, when a circuit board is formed in multiple layers, a via for electrically connecting the circuit pattern and the circuit pattern between the layers is formed for each layer and sequentially stacked up. Extremely high precision is required, and reliability is not always high even now. Further, in the case of forming a multi-layer, it is required that all layers have no defects, which causes a problem that technical difficulty increases.

Therefore, it is extremely effective to reduce the number of wiring layers as a method for manufacturing a multilayer circuit board with high yield. The present invention relates to a semiconductor chip in which electrodes are arranged in a grid pattern with multiple pins such as 40 × 40 pins on the mounting surface side, or a multilayer circuit board on which electronic components such as semiconductor devices in which electrodes are arranged in a grid pattern on the mounting surface side are mounted. As a multilayer circuit board on which these semiconductor chips or semiconductor devices are mounted, the number of laminated circuit boards is reduced,
The purpose of this is to improve the manufacturing yield of the multilayer circuit board and provide it as a highly reliable product.

[0008]

The present invention has the following constitution in order to achieve the above object. That is, a land formed in the same arrangement as the arrangement of the electrodes of the electronic component in which a large number of electrodes are arranged in a vertical and horizontal lattice arrangement on the mounting surface side, and one end is connected to the land and the other end is the land. in a multilayer circuit board but the circuit board by laminating a plurality and a circuit pattern formed is led out from the arrayed area, and electrically connects the lands through the vias between layers, the circuit Placed on the outermost periphery of a specific circuit board among the boards
A land that is, the outermost circumference of the land is connected, distribution of each of the lands, which are arranged in stacked circuit board directly above
With respect to the placement position, every other one of the outermost and outermost lands is deviated toward the outside and the inside in the direction orthogonal to the row direction.
It is characterized in that the circuit patterns are arranged in a zigzag shape, and at least two circuit patterns are drawn out from between adjacent lands of the lands arranged on the outermost periphery.

Further, it is arranged on the outermost periphery of the specific circuit board.
Lands to be, stacked circuit directly on the circuit board
The deviation amount based on the arrangement position of the land arranged on the board is adjusted by another land arranged on the specific circuit board.
Arrangement of the circuit board lands stacked directly on the circuit board
It is characterized in that it is equal to the amount of deviation from each position in the same direction . In addition, the land pitch p, the circuit pattern line width w, the circuit pattern interval s, the land diameter c, and the minimum displacement amount Δy that displaces the land in the circuit board.
_min , the maximum deviation Δy _max , and the specific circuit board
3. The multilayer circuit board according to claim 2, wherein the amount of deviation .DELTA.y of the land arranged on the outermost circumference is within the range represented by the following formula. Δy _min = ((w + s + p) ² −p ² ) ^½ / 2 Δy _max = p−s−c Δy _min ≦ Δy ≦ Δy _max

In addition, the circuit pattern is drawn from the outermost peripheral land of the first-layer circuit board on which electronic parts are mounted, and the circuit is extended from the innermost one row of lands to the adjacent outermost peripheral lands. The pattern is pulled out, and the outermost lands of the second-layer circuit board are arranged with respect to the respective layout positions of the lands formed on the first-layer circuit board.
Te, in a direction perpendicular to the column direction of the outermost periphery of the land, one
Every other second, in a zigzag pattern that is offset outward and inward.
And location, the outermost periphery of the land of the circuit board, the second inside
It is characterized in that the circuit pattern is drawn from the land of the row, and the circuit pattern is drawn from the outermost land of the third-layer circuit board and the land of one row inside the land. In addition, the layout of the lands and the circuit patterns formed on the circuit boards of the respective layers laminated in the fourth layer or more is determined by the second layer and the third layer.
It is characterized in that the land and the circuit pattern are repeatedly arranged in layers.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a multilayer circuit board according to the present invention will be described below in detail with reference to the accompanying drawings. The multilayer circuit board of the present embodiment enables efficient extraction of the circuit pattern by devising the arrangement of the lands arranged on each circuit board to be laminated in multiple layers, and as a result, the circuit board required for the multilayer circuit board It is characterized by reducing the number of layers.

FIG. 1 shows the layout of the lands 10 and the lands 10 on the first-layer circuit board that constitutes the multilayer circuit board of this embodiment.
An example of arrangement of the circuit pattern 12 extracted from FIG. In the figure, a part of the plurality of lands 10 arranged on the circuit board is shown. The receiving lands of the second and subsequent layers that are electrically connected to the lands 10 of the first layer will also be referred to as lands in this specification. Since electronic components such as a semiconductor chip having electrodes arranged in a grid pattern or a semiconductor device having electrodes arranged in a grid pattern are mounted on the first-layer circuit board, the lands 10 are arranged in the same grid pattern as these electrode arrangements. To be done.

In the present embodiment, the circuit pattern 12 drawn out from the land 10 on the circuit board of the first layer is formed by the same drawing method as the conventional example shown in FIG. The circuit pattern 12 is pulled out from the two rows of lands of the land 10b. That is, the circuit pattern 12 is drawn outward from the land 10a in the outermost row as it is, and the circuit pattern 12 is drawn out through the middle of the lands 10a adjacent in the outermost row for the land 10b inside thereof.

Assuming that the circuit pattern 12 is drawn from the two rows of lands 10a and 10b on the outer periphery of the first-layer circuit board, the next second-layer circuit board is most likely to be based on the arrangement of the first layer. The third row from the outer row and the land 1 inside
The circuit pattern 12 may be extracted for 0. In the second-layer circuit board, lands are provided by being electrically connected to the third row in the first layer and all the lands 10 inside thereof. The lands thus formed on each layer of the multilayer circuit board are the rest except that the circuit pattern 12 is connected prior to the layer, and as shown in FIG. The number is decreasing.

By the way, when the circuit boards are laminated and the lands are electrically connected between the layers, there is also a method in which the positions of the lands on the upper and lower circuit boards are made to completely coincide with each other. As shown in FIG. 2, the land 10B in the lower layer is laterally displaced from the land 10A in the upper layer. This is because the through hole 20 is arranged in the vicinity of the peripheral edge of the land 10 and the through hole 20 and the land 10 are displaced in order to secure a bonding area for bonding an external connection terminal such as a solder ball. is there. Upper and lower lands 1
The displacement amount of 0 is about the diameter of the land 10, and the land 10B in the lower layer is one land less than the land 10A in the upper layer.
It is arranged by translating horizontally by about one degree. Since the lands are arranged in the rectangular area, the direction in which the lands 10 move in parallel is a direction corresponding to each of the four sides and orthogonal to the side direction.

FIG. 3 shows the layout of the lands 14 and the circuit pattern 12 of the second-layer circuit board. As described above, the second-layer circuit board is laterally displaced by about one land with respect to the land arrangement of the first-layer circuit board. The characteristic point is that all the lands 14a arranged in the outermost row are not displaced in the same direction, but every other one, the displacement direction is opposite to the displacement direction of the other lands 14b by 180 °. Is to That is, in the second layer, the lands 14 are displaced inward with respect to the arrangement of the lands 10 of the first layer in the direction orthogonal to the side direction, but for the lands 14a taken every other row in the outermost row, , The other land 14b is arranged to be displaced outward.

In FIG. 3, reference numeral 10 indicates the arrangement position of the land 10 on the first layer to which the circuit pattern 12 is not connected. Reference numeral 14 is a land formed on the second layer.
As for the lands 14a arranged in the outermost row in the layer, every other land 14a is displaced outward, contrary to the displacement direction of the other lands 14b in the second layer. Outermost land 14a, 14b
By arranging the lands in this way, the lands 14a, 14
b has a zigzag plane arrangement.

As described above, the lands 14a and 14b arranged in the outermost row in the second layer are arranged in a zigzag shape because the lands 14a and 14b adjacent to each other by displacing the lands 14a and 14b in the opposite directions, This is to widen the interval of 14b so that two circuit patterns 12 can be passed between the adjacent lands 14a and 14b. Even when the lands are arranged in a regular grid pattern and only one circuit pattern 12 can pass between the adjacent lands, the lands 14a and 14b
The adjacent lands 14a and 1 by arranging zigzag
It is possible to pass two circuit patterns 12 between 4b, which makes it possible to improve the extraction efficiency of the circuit patterns 12.

That is, when arranging the lands 14 in the second layer, if the lands 14 of the first layer are arranged in parallel while maintaining the lattice arrangement, the extraction efficiency of the circuit pattern 12 cannot be improved. By arranging the lands 14 as in this embodiment, it is possible to improve the extraction efficiency of the circuit pattern 12. In this embodiment, the distance between the outermost rows of lands 14a and 14b is widened, thereby making it possible to draw out two circuit patterns 12 between adjacent lands 14a and 14b, and as shown in FIG. , Land 1 for 3 rows from the outer circumference on the 2nd layer
It became possible to draw out the circuit pattern 12 for No. 4. In the embodiment, the land 1 that is displaced in the opposite direction is used.
Although the displacement amount with respect to the corresponding land in the first layer for 4a is set to be equal to the displacement amount of the other land that is normally displaced, the displacement amounts in the reverse displacement are adjacent. Since the purpose is to widen the space between the lands 14a and 14b to secure a sufficient space for passing the circuit pattern 12, it is not always necessary to match the common displacement amount.

FIG. 4 shows an example in which the outermost lands 14a and 14b are arranged in a zigzag pattern to increase the number of drawn circuit patterns 12. In FIG. 4 (a), the land 14 is arranged by simply translating the entire land, and in FIG. 4 (b), the land 14 is arranged.
This is a case where a and 14b are arranged in a zigzag array. Figure 4 (a)
In the case of the regular grid-like arrangement of No. 2, only one circuit pattern 12 can pass in the middle of the adjacent lands 14, but two in the middle of the adjacent lands 14a and 14b due to the zigzag arrangement. The circuit pattern 12 can be passed through.

Generally, the conditions under which one or more circuit patterns can be passed between adjacent lands are: land pitch (center-to-center distance) p, circuit pattern line width w, circuit pattern spacing s, land diameter. It is given by c as follows. p> w + 2s + c The following conditions are added to the above conditions for the condition that only one circuit pattern can pass between the adjacent lands in the grid-like arrangement. p <2w + 3s + c

Therefore, when only one circuit pattern can be passed between the adjacent lands, two adjacent circuit patterns can be passed between the adjacent lands by displacing the adjacent lands in the opposite directions in the y direction. The minimum distance between lands required to be able to perform (the distance between the centers of lands arranged in zigzag as shown in Fig. 4 (b) is q) q _min and y
The minimum deviation amount Δy _min in the direction is given by the following equation. Since q _min = p + w + s q _min = (p ² + (2Δy _min ) ² ) ^1/2 ,
Rewriting Δy _min , Δy _min = ((w + s + p) ² −p ² ) ^1/2 ÷ 2. Further, the maximum displacement amount Δy _max that can be moved when the displacement is made in the y direction is Δy _max = p−s−c in consideration of the land positional relationship in the adjacent layer. As a result, the designable Δy is Δy _min ≦ Δy
Given by ≤ Δy _max .

Therefore, even under the condition that only one circuit pattern can pass between the lands, the lands in the outermost row are arranged in a zigzag pattern, and the deviation amount Δy in the y direction is set to the above Δy.
By setting it to be _min or more, it becomes possible to pass two or more circuit patterns between the lands in the outermost row. FIG. 3 shows a case where such a condition is satisfied, and two circuit patterns 1 are provided between the lands 14a and 14b arranged in a zigzag pattern in the outermost row.
It is an example of arranging through 2.

As can be seen from FIG. 3, there are five circuit patterns 12 arranged between the outer lands 14a arranged in a zigzag pattern in the outermost row. That is, one circuit pattern 12 is drawn out from the land 14b sandwiched between the outer lands 14a, and two circuit patterns 12 are drawn out between the diagonally arranged lands 14a and 14b, thereby adjoining each other. Five circuit patterns 12 are arranged between the outer lands 14a.

As described above, in designing the circuit pattern 12, it is necessary to consider that the condition that the required number of circuit patterns 12 can be arranged between the outermost rows of lands 14a is satisfied. In the example shown in FIG. 3, when every other land is selected from the reference grid array, the condition that five circuit patterns can be arranged between the selected lands should be satisfied.

In a regular lattice in which lands are arranged at equal intervals, n lands are arranged side by side, and if there are no (n-2) lands in the middle except the lands at both ends, the lands at both ends are Except for the number of wirings that can be arranged between the lands at both ends, m is given by the following equation. m = {p × (n−1) −c−s} ÷ (w + s)

If this condition is applied to the example of FIG. 3, five circuit patterns 12 are arranged between the lands in the arrangement of three lands.
Must be arranged, m> 5 when n = 3
Must be satisfied. That is, it must satisfy the condition of (2p-c-s) / (w + s)>5p> (5w + 6s + c) / 2.

As shown in FIG. 3, if the five circuit patterns 12 can be arranged between the outermost lands 14a, the circuit patterns 12 can be most efficiently extracted from the inner lands 14. If at least four circuit patterns 12 can be arranged between the lands 14a in the outermost row, it is possible to improve the extraction efficiency as compared with the case of simply passing one circuit pattern between the lands. If four circuit patterns can be arranged by eliminating the intermediate land, the circuit pattern that can be arranged only three in the arrangement of three lands is inferior to the above example in drawing efficiency, but compared with the conventional example. The withdrawal efficiency can be improved.

FIG. 5 shows the arrangement of the lands 16 and the arrangement of the circuit patterns 12 on the third layer. 14 is a land on the second layer from which the circuit pattern 12 is not drawn out. In the third layer, the circuit pattern 12 is drawn out from the sixth row counted from the first layer and the land 16 inside thereof. The arrangement of the lands 16 and the circuit pattern 12 in the third layer is the same as in the case of the first layer, and the circuit pattern 12 is drawn out from the outer two rows of lands 16a and 16b. Since the land 14 of the second layer is displaced by one land as a whole with respect to the arrangement of the land 10 in the first layer, the third layer is reversely arranged with respect to the arrangement of the second layer as a whole. Deviate, first
It is returned to an arrangement that roughly matches the land arrangement in the layer.

As described above, in the third layer, as shown in FIG. 5, the lands 16 are arranged so as to be moved in parallel as a whole while maintaining the lattice-like arrangement.
The space of 6b does not spread, and the lands 16a, 16b
Only one circuit pattern 12 can be inserted between them. Therefore, as in the case of the first layer, one circuit pattern 1 is provided between the adjacent lands 16a and 16b.
The circuit pattern 12 is pulled out from the outer two rows of lands 16a and 16b by passing through 2.

When the lands are arranged further inside after the fourth layer, the circuit pattern 12 may be extracted from the lands by repeating the above method. That is, in the third layer, the lands 16 return to an arrangement substantially the same as the arrangement of the lands 10 in the first layer. Alternately, the lands of the fourth layer are arranged so as to be displaced in the direction opposite to the direction in which they are displaced as a whole, so that the two circuit patterns 12 can be passed between the lands in the outermost row, It is sufficient to draw out the circuit pattern 12 for the three rows of lands. Then, when the land is left inside, the circuit pattern is drawn from the two rows of lands outside.

As described above, by setting the array of lands in each layer and pulling out the circuit pattern 12, it is possible to draw out the circuit pattern more efficiently than the conventional method of pulling out the circuit pattern from the two outer rows of lands. It becomes possible to do. Actually, in a 30 × 30 grid array,
With the square-shaped electrode arrangement excluding the 12 × 12 array portion in the central portion, and when the land diameter is 150 μm, the line width of the circuit pattern is 45 μm, and the interval is 45 μm, four layers are formed by the same method as this embodiment. The circuit pattern can be extracted from all the electrodes, whereas the conventional method requires five layers.

Further, in the case of the method of the present embodiment, the circuit pattern is drawn from the outer two rows of lands for the odd-numbered layers counted from the surface on which the electronic component such as the semiconductor chip is mounted, and the even-numbered layers. For, the circuit pattern is drawn from the outer three rows of lands. Therefore, similar to the conventional drawing method, the circuit patterns are drawn in order from the outside where the lands are arranged, and there is an advantage that the drawing order can be improved without significantly changing the conventional wiring order.

In the multilayer circuit board of this embodiment, when the lands are formed in each layer and the multi-layer formation is performed, the arrangement of the lands is appropriately set, but the lands are patterned by the build-up method or the like. It is easy to form, and the normal processing steps can be applied as is,
It is also effective in that the number of steps is not particularly increased and there is no particular restriction in manufacturing. Also, of course, because the number of laminated circuit boards can be reduced,
It facilitates the manufacture of multilayer circuit boards and improves the yield,
There is an advantage that a good product can be manufactured and the manufacturing cost can be reduced.

In the above embodiment, when the lands are arranged in a regular grid pattern, a maximum of one circuit pattern can pass between the adjacent lands. However, the present invention has such a condition. However, the present invention is not limited to this case, and can be applied to a case where a plurality of circuit patterns such as two and three can be passed between adjacent lands. For example, when two circuit patterns can be passed between the adjacent lands, three or more circuit patterns can be passed between the adjacent lands by arranging the lands in a zigzag pattern as described above. If so, the extraction efficiency of the circuit pattern can be increased correspondingly, and the circuit pattern can be formed more efficiently.

[0036]

As described above, the multilayer circuit board according to the present invention makes it possible to efficiently draw out a circuit pattern from the area in which the lands are arranged, thereby reducing the number of layers of the multilayer circuit board. Therefore, it is possible to improve the manufacturing yield of the multilayer circuit board and provide the multilayer circuit board with high reliability. Further, the multilayer circuit board according to the present invention is a method of drawing out the circuit pattern from the outside of the land to the inside in order, and it is possible to draw out the circuit pattern efficiently without significantly changing the conventional wiring order. And so on.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an arrangement of lands and circuit patterns on a first-layer circuit board that constitutes a multilayer circuit board according to the present invention.

FIG. 2 is an explanatory diagram showing a planar arrangement of lands electrically connected between layers.

FIG. 3 is an explanatory diagram showing an arrangement of lands and circuit patterns on a second-layer circuit board that constitutes a multilayer circuit board.

FIG. 4 is an explanatory diagram showing an enlarged layout of lands and circuit patterns.

FIG. 5 is an explanatory diagram showing an arrangement of lands and circuit patterns on a third-layer circuit board that constitutes the multilayer circuit board.

FIG. 6 is an explanatory diagram showing a method of mounting a semiconductor chip by flip chip connection.

FIG. 7 is an explanatory diagram showing a conventional circuit pattern drawing method.

FIG. 8 is a cross-sectional view showing a state in which a semiconductor chip is mounted on a multilayer circuit board.

[Explanation of symbols]

4 semiconductor chips 5 circuit board 6 electrodes 9 External connection terminal 10, 10a, 10b land 12 circuit patterns 14, 14a, 14b Land 16, 16a, 16b Land 20 through holes

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoaki Takubo 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Toshiba Industrial Research Institute (56) Reference JP-A-9-275172 (JP, A) Flat 9-172105 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12

Claims (5)

(57) [Claims] 1. A land formed in the same arrangement as the arrangement of the electrodes of an electronic component in which a large number of electrodes are arranged in a vertical and horizontal lattice arrangement on the mounting surface side, and one end is connected to the land and the other end is formed. A multi-layer circuit board in which a plurality of circuit boards each having a circuit pattern formed by being drawn out from the area in which the lands are arranged to the outside are stacked, and the lands are electrically connected via vias between the layers. The outermost periphery of a specific circuit board among the circuit boards
That the land, the outermost periphery of the lands are connected, with respect to the arrangement position of each of the lands, which are arranged in stacked circuit board directly, in a direction perpendicular to the column direction of the outermost periphery of the land, one Tsuo
The zigzag shape, which is offset toward the outside and inside
Then , at least two circuit patterns are drawn out from between adjacent lands of the lands arranged on the outermost periphery. 2. Located on the outermost periphery of the specific circuit board
Lands that, the circuit board stacked directly on the circuit board
The deviation amount based on the arrangement position of the land arranged on the
Arrangement position of land on the circuit board stacked directly on the road board
2. The multilayer circuit board according to claim 1 , wherein the displacement amounts are respectively equal to the displacement amounts in the same direction . 3. A land pitch p on the circuit board,
The line width w of the circuit pattern, the interval s of the circuit pattern, the land diameter c, the minimum displacement amount Δy _min for displacing the land, and the maximum displacement amount Δy _max are arranged on the outermost periphery of the specific circuit board.
3. The multilayer circuit board according to claim 2, wherein the amount of deviation .DELTA.y of the land to be placed is within a range represented by the following formula. Δy _min = ((w + s + p) ² −p ² ) ^½ / 2 Δy _max = p−s−c Δy _min ≦ Δy ≦ Δy _max 4. A circuit pattern is drawn from an outermost peripheral land of a first-layer circuit board on which electronic parts are mounted, and a circuit is extended from the innermost one row of lands to the adjacent outermost peripheral lands. The pattern is drawn out, and the outermost lands of the second-layer circuit board are arranged with respect to the respective layout positions of the lands formed on the first-layer circuit board.
Te, in a direction perpendicular to the column direction of the outermost periphery of the land, one
Every other second, in a zigzag pattern that is offset outward and inward.
And location, the outermost periphery of the land of the circuit board, the second inside
4. The multilayer circuit board according to claim 3, wherein the circuit pattern is drawn from the land of the row, and the circuit pattern is drawn from the outermost land of the third-layer circuit board and the land of one row inside the outermost land. 5. A configuration in which a land and a circuit pattern are formed on a circuit board of each layer laminated in a fourth layer or more, and the land and the circuit pattern are repeated in the second layer and the third layer. The multilayer circuit board according to claim 4, wherein