JPH11297885A - Multilayer circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a multilayer circuit t board provided with connection electrodes arranged in lattice and mounted with an electronic part to be lessened in number of layers, easily manufactured, and enhanced in yield. SOLUTION: An electronic part is mounted on a first circuit board, a circuit pattern is led out from all outermost lands 10a located on the periphery of a region of the first circuit board where lands 10 are arranged and which is mounted with an electronic part and the lands 10 arranged on and near the diagonal lines of the region. Furthermore, as to a second circuit board and following circuit boards, a circuit pattern is led out from all outermost lands 10a located on the periphery of a region where lands 10 are arranged and lands 10e arranged on the side edges of a blank space which is formed in the direction of a diagonal line by leading out a circuit pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board for mounting electronic components such as a semiconductor chip having connection electrodes arranged in a grid or a semiconductor device having external connection terminals arranged in an area array.

[0002]

2. Description of the Related Art In recent semiconductor devices, logic devices have become more sophisticated and higher in density, and the number of inputs and outputs has increased. For this reason, by arranging a large number of electrodes in a grid pattern on the electrode forming surface of the semiconductor chip, a product that compensates for a shortage of space for arranging connection electrodes has been provided. FIG. 18 shows an example in which the semiconductor chip 4 is mounted on the circuit board 5 by ordinary flip chip connection. The semiconductor chip 4 has the electrodes 6 arranged only on the periphery of the electrode forming surface.
And the circuit pattern 7 are connected.

FIG. 19 shows an example of forming lands 8 and circuit patterns 7 provided on a circuit board on which a semiconductor chip is mounted. In this example, the lands 8 are arranged in two rows, and the circuit patterns 7 connected to the inner lands 8 are drawn out from the middle of the outer adjacent lands 8 so that the circuit patterns 7 are drawn from all the lands 8 in one plane. . However, in a case where the electrodes are arranged in a large number of rows in an area array on the electrode forming surface, wiring cannot be drawn out from all the lands in one plane, depending on the land spacing and the number of lands. .

As a method of solving such a problem, a circuit board on which a semiconductor chip is mounted is formed in multiple layers, and a circuit pattern is appropriately arranged on each of the stacked circuit boards, so that the circuit pattern is formed on all the electrodes of the semiconductor chip. There is a way to connect. FIG. 20 shows an example in which a semiconductor chip 4 having a large number of electrodes 6 arranged in a grid pattern is mounted on a multilayer circuit board. If such a multilayer circuit board is used, all the electrodes 6 of the semiconductor chip 4 can be electrically connected to the circuit patterns 7 and 7a, and the external connection terminals 9 and the electrodes 6 can be electrically connected. In the same figure, 7a is the circuit pattern of the inner layer, 5
Reference numerals a to 5d denote circuit boards of first to fourth layers.

[0005]

As described above, when a semiconductor chip is mounted on a circuit board, if the number of electrodes is not so large, a multilayer circuit board in which about two circuit boards are stacked can be used. When mounting a semiconductor chip on which an extremely large number of electrodes such as 30 × 30 pins and 40 × 40 pins are mounted, the circuit boards must be stacked in many layers such as 6 to 10 layers.

In order to form a multilayer circuit board by laminating circuit boards on which circuit patterns are formed at high density, a high-density wiring method such as a build-up method is used. However, the production of multilayer circuit boards has significant problems in terms of product yield, reliability, and production cost. In other words, when a circuit board is formed in multiple layers, a circuit pattern is formed for each layer, and the circuit patterns are electrically connected between the layers by vias and sequentially laminated, so that the manufacturing process is extremely accurate. And the reliability of the product is not always high even now. In the case of laminating a plurality of layers, it is necessary that all the layers have no defect, so that technical difficulty is further increased.

For these reasons, it is very effective to reduce the number of wiring layers in order to manufacture a multilayer circuit board with good yield. The present invention mounts an electronic component such as a semiconductor chip in which electrodes are arranged in a lattice with multiple pins such as 30 × 30 pins or 40 × 40 pins on the mounting surface, or a semiconductor device in which electrodes are arranged in a lattice on the mounting surface. The present invention relates to a multi-layer circuit board that reduces the number of layers of the multi-layer circuit board on which these semiconductor chips or semiconductor devices are mounted, thereby improving the production yield of the multi-layer circuit board and providing a highly reliable product. It is intended to be.

[0008]

The present invention has the following arrangement to achieve the above object. That is, lands formed in the same arrangement as a large number of connection electrodes arranged in a grid on the mounting surface side of the electronic component to be mounted, and electrically connected to the circuit pattern between layers via vias, The electronic component is mounted on a multilayer circuit board in which a circuit board having one end connected to the land and the other end drawn out of the region in which the land is arranged is stacked. For the first layer circuit board,
A circuit pattern is drawn from all lands arranged on the outermost periphery in a region where the lands are arranged, lands arranged on a diagonal line of the region, and lands arranged in the vicinity of the diagonal line. Regarding the substrate, the circuit pattern is formed from all the lands arranged on the outermost periphery in the area where the lands are arranged, and the lands arranged on the side edges of the empty space formed in the diagonal direction by extracting the circuit pattern in the upper layer. It is characterized by being drawn out.

In the circuit board of the first layer, a circuit pattern is formed from lands arranged on a diagonal line of the region and lands arranged on one side of the diagonal line and in a row parallel to the diagonal line. It is characterized by being drawn out. Further, a circuit pattern is preferentially drawn from a land arranged on the outer peripheral side in the vicinity of the center position of each side of the area where the lands are arranged.

Also, a plurality of connection electrodes arranged in a grid on the mounting surface side of the electronic component to be mounted are formed in the same arrangement, and are electrically connected to circuit patterns between layers through vias. In a multilayer circuit board in which a circuit board having a land and one end connected to the land and the other end drawn outward from the area where the land is arranged is formed, the electronic component is With respect to the first-layer circuit board to be mounted, circuit patterns are drawn from all lands arranged on the outermost periphery in a region where lands are arranged, and lands arranged near a diagonal near the corner, Regarding the circuit board of the second layer and thereafter, all the lands arranged on the outermost periphery in the area where the lands are arranged, and the vacant space formed near the corner by drawing out the circuit pattern in the upper layer From arranged lands in the vicinity of over scan, wherein the circuit pattern of the empty space as a lead space of the circuit pattern is drawn.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a multilayer circuit board according to the present invention will be described below in detail with reference to the accompanying drawings. When a circuit pattern is drawn out from a region where lands are arranged on a circuit board, the circuit pattern is drawn out between adjacent lands. The condition that at least one circuit pattern can be passed between adjacent lands is as follows: land pitch (center distance) p, circuit pattern line width w, circuit pattern interval s, land diameter c, p> w + 2s + c
Is to satisfy. The multilayer circuit board according to the present invention,
It is assumed that the land pitch of the circuit board constituting each layer, the line width of the circuit pattern, and the like satisfy these conditions.

(Embodiment 1) FIGS. 1 to 5 show a first embodiment of a multilayer circuit board. This embodiment shows an example of drawing out the circuit pattern 7 when the lands 10 are arranged in a regular lattice with 30 × 30 pins. Land pitch 240μm, land diameter 110μm, circuit pattern line width 43μm, circuit pattern spacing 43μm

FIG. 1 shows an example of the layout of lands 10 and the extraction of circuit patterns 7 on a first-layer circuit board to which electronic components are bonded. Note that the layout of the lands 10 provided on the first-layer circuit board matches the layout of the connection electrodes of the electronic components mounted on the multilayer circuit board. The characteristic feature of the circuit pattern 7 drawing method shown in FIG. 1 is that the circuit pattern 7 is drawn from all of the outermost lands 10a in the rectangular area where the lands 10 are arranged, and is drawn on the diagonal line of the rectangular area. The land 10b to be arranged and the land 10c to be arranged on one row parallel to the diagonal on one side of the diagonal
The circuit pattern 7 is preferentially extracted from the circuit pattern 7.

Land 10 from which circuit pattern 7 is drawn
As for the lands located at the center of the rectangular area in b and 10c, as shown in FIG. 1, the circuit pattern 7 is linearly drawn to the outside of the area where the lands 10 are arranged between the adjacent lands 10. As a result, the circuit pattern 7 outside the land arrangement region is arranged such that the circuit pattern 7 drawn from the land 10a disposed on the outermost periphery of the land arrangement region and the circuit pattern 7 drawn from the inside of the land arrangement region alternately. Will be placed in.

The lands arranged near the corners of the land arrangement area include the lands 10b arranged on the diagonal line and the lands 10c arranged in a row parallel to the lands.
The circuit pattern 7 can be drawn from other lands. In FIG. 1, 10d is a circuit pattern other than the land.
It is the land which pulled out. This is due to the fact that the circuit pattern 7 is easily drawn out in the vicinity of the corner of the land arrangement region.

FIG. 2 shows a land 10 on the second-layer circuit board.
And drawing of the circuit pattern 7 are shown. The first
It is not necessary to arrange the lands 10 in the second layer for the lands from which the circuit patterns 7 are drawn out in the second layer. Therefore, the land 10 arranged on the second layer is a land from which the circuit pattern 7 is not drawn out on the circuit board of the first layer. The lands 10 arranged in the second layer and the lands 10 in the first layer are electrically connected between the layers by vias.

The method of extracting the circuit pattern 7 from the second-layer circuit board is the same as the method of extracting the circuit pattern 7 from the first-layer circuit board with respect to the land 10a located at the outermost periphery of the land arrangement region. Are drawn in the diagonal direction by drawing out all the circuit patterns 7 and drawing out the lands 10b arranged diagonally in the first layer and the lands 10c arranged in a row parallel to the diagonal in the first layer. The circuit pattern 7 is preferentially drawn from the land 10e arranged on the side edge of the empty space.

By drawing the circuit pattern 7 from the lands 10b arranged on the diagonal line and the lands 10c arranged on the row parallel to the diagonal line on the first layer circuit board,
An empty space is formed in the diagonal direction on the second-layer circuit board. Withdrawing the circuit pattern 7 from the land 10e arranged on the side edge of the empty space in the second layer means that the circuit space is expanded so as to expand the diagonal empty space in the land arrangement area arranged on the circuit board. That is, a land from which the pattern 7 is drawn is selected. Also in the second layer, the lands 10d arranged near the corners in the land arrangement area are drawn out preferentially.

FIG. 3 shows a land 10 on the third-layer circuit board.
And drawing of the circuit pattern 7 are shown. In the third layer as well, all the circuit patterns 7 are drawn out for the outermost lands 10a in the land arrangement area, and the lands 10e arranged on the side edges of the free space formed diagonally in the inner part of the land arrangement area. The circuit pattern 7 is preferentially drawn out of FIG.

FIG. 4 shows a land 10 on the fourth-layer circuit board.
And drawing of the circuit pattern 7 are shown. Also in the fourth layer, the circuit pattern 7 is drawn out for all the outermost lands 10a of the land arrangement area, and the lands 10e arranged on the side edges of the free space formed diagonally in the inner part of the land arrangement area. The circuit pattern 7 is preferentially drawn out of FIG. In the fourth layer, the circuit pattern 7 is drawn out through a vacant space formed widely in the diagonal direction.

FIG. 5 shows the land 10 on the fifth-layer circuit board.
And drawing of the circuit pattern 7 are shown. Since the lands 10 remaining in the fifth layer are few, the circuit patterns 7 can be easily drawn from all the lands 10, and the design for drawing the circuit patterns 7 can be appropriately selected.

According to the multilayer circuit board of the present embodiment, the circuit pattern 7 can be drawn from all the lands 10 by using the five-layer circuit board. According to the conventional method in which two rows of circuit patterns are drawn out from the outer periphery of the land arrangement region, seven layers are required, but according to the method of the present embodiment, the number of stacked circuit boards can be effectively reduced.

(Embodiment 2) FIGS. 6 to 10 show a second embodiment of the multilayer circuit board. In the present embodiment, 30 as in the first embodiment.
This is an example of drawing out a circuit pattern 7 in a case where lands 10 are arranged in a regular lattice with × 30 pins. Land pitch 350μm, land diameter 120μm, circuit pattern line width 50μm, circuit pattern spacing 50μm

FIG. 6 shows a land 10 on the first-layer circuit board.
And drawing examples of the circuit pattern 7 are shown. The feature of the present embodiment is that the circuit pattern 7 is preferentially drawn from the lands 10 arranged on the diagonal line of the land arrangement area, and the lands arranged in the vicinity of the corner of the land arrangement area in the diagonal direction. This is to extract the circuit pattern 7 from 10f. That is, the circuit pattern 7 is preferentially extracted from the corners of the land arrangement area based on the concept of preferentially extracting the circuit pattern 7 from the lands 10 arranged in the diagonal direction of the land arrangement area. .

FIG. 7 shows lands 10 on the second-layer circuit board.
And drawing of the circuit pattern 7 are shown. Also in the second layer, for the outermost land 10a, the circuit pattern 7 is drawn out from all the lands 10a, and the land arranged near the corner of the land arrangement area and the land arranged diagonally and near both sides thereof The circuit patterns 7 are preferentially drawn from the lands 10f arranged in the area.

FIG. 8 shows the land 10 on the third-layer circuit board.
FIG. 9 shows the arrangement of the lands 10 and the extraction of the circuit pattern 7 on the fourth-layer circuit board. In any of the circuit boards, the lands arranged diagonally in the vicinity of the corner of the land arrangement area are preferentially drawn.

As can be seen from the drawing method of the circuit pattern 7 shown in FIGS. 7, 8 and 9, in the case of this embodiment, the space vacated by drawing the circuit pattern 7 in the upper layer is used in the circuit layer. There is an advantage that it can be used as a space for drawing out the pattern 7. That is, by preferentially extracting the circuit pattern 7 from the land 10f near the diagonal near the corner of the land arrangement area, an empty space at the corner of the land arrangement area is widened. Used without waste.

FIG. 10 shows the arrangement of the lands 10 on the fifth layer and the extraction of the circuit pattern 7. Also in the case of the present embodiment, five layers are formed similarly to the first embodiment, but the land 10 remaining on the fifth layer is small compared to the first embodiment, and the circuit The drawing of the pattern 7 has been completed. As shown in FIG. 10, when a vacant space other than the area occupied by the land 10 and the circuit pattern 7 is large in the circuit board, a commonly used layer such as a power supply layer and a ground layer is formed and used in the vacant space. can do.

(Embodiment 3) FIGS. 11 and 12 show a third embodiment of the multilayer circuit board. This embodiment is also an example of drawing out the circuit pattern 7 in the case where the lands 10 are arranged in a regular lattice with 30 × 30 pins, similarly to the first and second embodiments. However, in this embodiment, the wiring width and the wiring interval of the circuit pattern 7 are smaller than those in the above-described example.
This is an example of a case where three circuit patterns 7 can be passed therebetween. Land pitch 350 μm, land diameter 100 μm, circuit pattern line width 25 μm, circuit pattern spacing 25 μm

FIG. 11 shows a land 1 on the first-layer circuit board.
2 shows the arrangement of 0 and the drawing of the circuit pattern 7. The method of extracting the circuit pattern 7 in this embodiment is the same as that of the above-described embodiment. 10 and the lands 10 arranged on the diagonal line of the land arrangement region and in the vicinity thereof are preferentially drawn.

In this embodiment, three lands 10
Since it is possible to pass through the circuit patterns 7, the circuit patterns 7 can be drawn from the lands 10 arranged diagonally to the land arrangement area and the lands 10 in a plurality of rows on both sides thereof. FIG. 12 shows the arrangement of the lands 10 and the extraction of the circuit patterns 7 on the second-layer circuit board. In this embodiment, the circuit patterns 7 are drawn from all the lands 10 in the second layer.

Under the same conditions as in this embodiment, when a circuit pattern is drawn by a conventional circuit pattern drawing method, three circuit boards are required. On the other hand, in the present embodiment, the circuit board can be formed of two layers, which is effective in reducing the number of stacked circuit boards. In this embodiment, if wiring is provided on both sides of the circuit board, it is not necessary to stack the circuit boards.

(Embodiment 4) FIGS. 13 to 17 show a fourth embodiment of the multilayer circuit board. This embodiment is an example of drawing out the circuit pattern 7 in the case of having a square-shaped land arrangement area in which a land of a normal lattice arrangement of 22 × 22 pins at the center is removed from a land of a normal lattice arrangement of 42 × 42 pins. Is shown. Land pitch 240μm, land diameter 110μm, circuit pattern line width 43μm, circuit pattern spacing 43μm

In this embodiment, the circuit pattern 7 is extracted from the outermost land 10a in the land arrangement area, and the land 10b arranged diagonally in the land arrangement area and the land 10e in the vicinity thereof are preferentially extracted from the land 10e.
And the circuit pattern 7 is preferentially extracted from the land 10g arranged on the outer peripheral side near the center position of each side of the land arrangement area.

FIG. 13 shows land 1 on the first layer circuit board.
FIG. 14 shows the arrangement of the lands 10 and the extraction of the circuit pattern 7 on the second-layer circuit board. Regarding the lands drawn from the diagonal direction in the land arrangement area, the circuit patterns 7 are drawn from lands 10e arranged on the side edges of the empty space formed diagonally.

FIG. 15 shows land 1 on the third-layer circuit board.
FIG. 16 shows the arrangement of the lands 10 and the extraction of the circuit pattern 7 on the fourth-layer circuit board. It can be seen that the circuit pattern 7 is preferentially drawn out of the land near the center in the diagonal direction of the land arrangement area and on each side of the land arrangement area.

FIG. 17 shows land 1 on the fifth layer circuit board.
2 shows the arrangement of 0 and the drawing of the circuit pattern 7. The land remaining until the fifth layer is very small,
The drawing of the circuit pattern from the land has been completed up to the layer. If the conventional method of extracting the circuit patterns two rows at a time from the outer periphery of the land arrangement area is applied to the conditions of this embodiment, five circuit boards are required. On the other hand, according to the method of the present embodiment, it can be said that the circuit pattern is efficiently extracted in that almost all of the circuit patterns are completely extracted in approximately four layers.

[0038]

As described above, the multilayer circuit board according to the present invention makes it possible to efficiently draw out a circuit pattern from an area where lands are arranged, thereby reducing the number of layers of the multilayer circuit board. Thus, it is possible to improve the production yield of the multilayer circuit board and to provide a highly reliable multilayer circuit board. Further, the multilayer circuit board according to the present invention is based on a method in which circuit patterns are sequentially drawn inward from the outside of the lands to the inside, so that it is possible to efficiently draw circuit patterns without significantly changing the conventional wiring order. And so on.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an arrangement of lands and circuit patterns on a first-layer circuit board in a first embodiment of a multilayer circuit board.

FIG. 2 is an explanatory diagram showing an arrangement of lands and circuit patterns on a second-layer circuit board in the first embodiment of the multilayer circuit board;

FIG. 3 is an explanatory diagram showing an arrangement of lands and circuit patterns on a third-layer circuit board in the first embodiment of the multilayer circuit board;

FIG. 4 is an explanatory diagram showing an arrangement of lands and circuit patterns on a fourth-layer circuit board in the first embodiment of the multilayer circuit board.

FIG. 5 is an explanatory diagram showing an arrangement of lands and circuit patterns on a fifth-layer circuit board in the first embodiment of the multilayer circuit board.

FIG. 6 is an explanatory diagram showing an arrangement of lands and circuit patterns on a first-layer circuit board in a second embodiment of the multilayer circuit board.

FIG. 7 is an explanatory diagram showing an arrangement of lands and circuit patterns on a second-layer circuit board in a second embodiment of the multilayer circuit board.

FIG. 8 is an explanatory diagram showing an arrangement of lands and circuit patterns on a third-layer circuit board in the second embodiment of the multilayer circuit board.

FIG. 9 is an explanatory diagram showing an arrangement of lands and circuit patterns on a fourth-layer circuit board in the second embodiment of the multilayer circuit board.

FIG. 10 is an explanatory diagram showing an arrangement of lands and circuit patterns on a fifth-layer circuit board in the second embodiment of the multilayer circuit board.

FIG. 11 is an explanatory diagram showing an arrangement of lands and circuit patterns on a first layer circuit board in a third embodiment of the multilayer circuit board.

FIG. 12 is an explanatory diagram showing an arrangement of lands and circuit patterns on a second-layer circuit board in a third embodiment of the multilayer circuit board.

FIG. 13 is an explanatory diagram showing an arrangement of lands and circuit patterns on a first-layer circuit board in a fourth embodiment of the multilayer circuit board.

FIG. 14 is an explanatory diagram showing an arrangement of lands and circuit patterns on a second-layer circuit board in a fourth embodiment of the multilayer circuit board.

FIG. 15 is an explanatory diagram showing an arrangement of lands and circuit patterns on a third-layer circuit board in a fourth embodiment of the multilayer circuit board.

FIG. 16 is an explanatory diagram showing an arrangement of lands and circuit patterns on a fourth-layer circuit board in a fourth embodiment of the multilayer circuit board.

FIG. 17 is an explanatory diagram showing an arrangement of lands and circuit patterns on a fifth-layer circuit board in a fourth embodiment of the multilayer circuit board.

FIG. 18 is an explanatory diagram showing a method of mounting a semiconductor chip by flip chip connection.

FIG. 19 is an explanatory diagram showing a conventional circuit pattern drawing method.

FIG. 20 is a cross-sectional view showing a configuration in which a semiconductor chip is mounted on a multilayer circuit board.

[Explanation of symbols]

Reference Signs List 4 semiconductor chip 5 circuit board 6 electrode 7 circuit pattern 10, 10a, 10b, 10c, 10d, 10e, 10
f land

Claims (4)

[Claims] An electronic component to be mounted is formed in the same arrangement as a large number of connection electrodes arranged in a grid on the mounting surface side of an electronic component to be mounted, and is electrically connected to a circuit pattern between layers via a via. A multi-layer circuit board having a land and a circuit board having one end connected to the land and the other end drawn out of the region in which the land is arranged and formed outside; Regarding the first layer of the circuit board to be mounted, the circuit is composed of all the lands arranged on the outermost periphery in the area where the lands are arranged, the lands arranged on a diagonal line of the area, and the lands arranged near the diagonal line. The pattern is drawn, and for the circuit boards of the second and subsequent layers, all the lands arranged on the outermost periphery in the region where the lands are arranged, and the circuit pattern is drawn and diagonally drawn in the upper layer Multilayer circuit board, characterized in that being drawn circuit patterns from lands positioned on the side edge of the free space formed in the direction. 2. A circuit pattern comprising a land arranged on a diagonal line of the region and a land arranged on one column parallel to the diagonal line on one side of the diagonal line on the first layer circuit board. 2. The device according to claim 1, wherein the device is drawn.
The multilayer circuit board according to the above. 3. The circuit pattern according to claim 1, wherein a circuit pattern is preferentially drawn from a land arranged on an outer peripheral side near a center position of each side of the area where the lands are arranged. Multilayer circuit board. 4. A plurality of connection electrodes arranged in a grid on the mounting surface side of an electronic component to be mounted in the same arrangement and electrically connected to a circuit pattern between layers via a via. In a multilayer circuit board, a circuit board having a land and a circuit pattern having one end connected to the land and the other end drawn out from the region where the land is arranged is formed. With respect to the first-layer circuit board to be mounted, circuit patterns are drawn from all lands arranged on the outermost periphery in a region where lands are arranged, and lands arranged near a diagonal near the corner, For the second and subsequent layers of the circuit board, all the lands arranged on the outermost periphery in the region where the lands are arranged, and the empty space formed near the corner by extracting the circuit pattern in the upper layer Multilayer circuit board, characterized in that the arranged land near, the circuit pattern of the empty space as a lead space of the circuit pattern is drawn out of.