JPH11260955A - Multi-layer circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the highly reliable product, by decreasing the number of wiring layers constituting a multi-layer circuit board and increasing the manufacturing yield rate. SOLUTION: A via connecting land, which has the interval larger than the interval of vias 16 provided at a core substrate 10 at wiring layers 12a and 12b formed on one surface of the core substrate 10 and is selected at the arrangement, where the maximum number of the land can be selected, and the drawing land, to which a wiring is connected, other than these via-connecting lands, are selected. For the land located at the outer surface of the region where the above described lands are arranged, the wirings are withdrawn from both the drawing land and the via connecting land at the same time. For the drawing lands which are aligned in the inside of the above described region, at least one wiring is aligned between the neighboring lands, and the lands which are arranged at the diagonal-line position in the above described region and the vicinity hereof are withdrawn preferentially. Thus, the wirings are withdrawn from all the drawing lands and electrically connected to the vias 16 penetrating the core substrate 10. For the via-connecting lands, where the wirings are not withdrawn at the wiring layers 12a and 12b formed on one surface, the lands are electrically connected to the vias 16 penetrating the core substrate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer circuit board on which electronic components such as a semiconductor chip having connection electrodes arranged in a plane in a grid or a semiconductor device having external connection terminals arranged in a plane in a lattice are mounted.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration of a semiconductor device in which a semiconductor chip 4 is mounted on a circuit board 5 by flip-chip connection. In this semiconductor device, a connection electrode 6 provided on an electrode forming surface of a semiconductor chip 4 is provided with a land 8 provided on a circuit board 5.
And the wiring 7 is drawn out from each land 8. The wiring 7 drawn out from the mounting area of the semiconductor chip 4 is electrically connected to an external connection terminal such as a solder ball or a lead pin for mounting the semiconductor device.

In the case of electronic components such as semiconductor chips and semiconductor devices, connection electrodes or solder balls are formed in a grid pattern on the entire surface of the semiconductor chip on which the electrodes are formed or on the mounting surface of the semiconductor device in order to cope with high integration and high density. And the like, in which external connection terminals are arranged. In such products, wiring cannot be drawn out from all connection electrodes or external connection terminals with only a single layer.Therefore, wiring layers should be multi-layered, and wiring patterns in each wiring layer should be determined so that wiring does not interfere. ing.

[0004] When the wiring layers are multi-layered as described above, it is general to use a core substrate that supports the wiring layers and form a wiring layer provided with a predetermined wiring pattern on the core substrate. FIG. 7 shows a configuration of a semiconductor device in which wiring layers 12 a and 12 b are provided on a core substrate 10. Of the wiring layers 12a and 12b provided on both surfaces of the core substrate 10, the wiring layer 12a provided on one surface on which the semiconductor chip 4 is mounted is a layer from which the wiring 7 electrically connected to the connection electrode 6 of the semiconductor chip is drawn. And a wiring layer 12b provided on the other surface of the core substrate 10.
Are formed by laminating the same number of layers as the wiring layers 12a provided on one surface of the core substrate 10 so that the semiconductor device does not warp.

The connection electrodes 6 of the semiconductor chip 4 and the core substrate 1
The external connection terminals 14 provided on the other surface of the core substrate 1
0 is electrically conducted through a via 16 provided through the hole. Since the vias 16 are formed by processing the through holes of the core substrate 10, the vias 16 need to be arranged at a certain interval or more, and the external connection terminals 14 also need to be arranged at a constant interval. The wiring 7 has a pattern formed in consideration of the arrangement of the vias 16 or the external connection terminals 14. Depending on the product, a common ground layer may be provided on the wiring layer 12b provided on the other surface of the core substrate 10 in addition to a conductor portion for electrically connecting the external connection terminal 14 and the via 16.

[0006]

As shown in FIG. 7, a circuit board on which a semiconductor chip having a large number of connection electrodes arranged in a grid pattern on an electrode formation surface necessarily requires a multi-layered wiring layer. And the technical difficulties in manufacturing increase accordingly. As a method of electrically connecting to the connection electrodes of the semiconductor chip to form wiring in multiple layers, there is a build-up method and the like, but the manufacturing process of these multilayer formation requires extremely high precision, and mass production of multilayer circuit boards is performed. However, such a process has a problem in improving the manufacturing yield and reliability.

[0007] In particular, when the wiring layers are formed by laminating multiple layers such as six to ten layers, even if one of the layers is defective, the entire product is defective. The difficulty is greatly increased. Therefore, in the production of such a multilayer circuit board, reducing the number of wiring layers is extremely effective in improving the production yield and providing a highly reliable product. Further, since the same number of wiring layers are provided on both surfaces of the core substrate 10 in order to prevent warpage of the semiconductor device, if the number of wiring layers increases on one surface, the number of wiring layers in the semiconductor device as a whole inevitably increases. There is also the problem of doing it. The present invention proposes a multilayer circuit board which solves such problems in the production of a multilayer circuit board, improves the production yield, and can be provided as a highly reliable product.

[0008]

The present invention has the following arrangement to achieve the above object. That is, on one surface of the core substrate on which the electronic components are mounted, a plurality of connection electrodes are arranged in a grid pattern in the same arrangement as the connection electrodes of the electronic component. A plurality of wiring layers each having a land that is electrically connected to each other, and a wiring formed by connecting one end to the land and drawing the other end to the outside from an area in which the land is arranged, and On the other surface, the wiring formed on the wiring layer on the one surface and the external connection terminal mounted on the mounting surface of the core substrate are electrically connected via a via provided through the core substrate. In the multilayer circuit board formed by laminating the same number of wiring layers as the wiring layers formed on the one surface, the wiring layers provided with the wirings to be connected are formed on the core substrate by the wiring layers formed on the one surface. Is there an interval longer than the via interval to be provided? A land for via connection selected in an arrangement in which the most lands can be selected, and a land for drawing, to which wiring is connected, other than the land for via connection, are selected. With respect to the lands located on the outer periphery, wiring is drawn out from both the lands for drawing and the lands for via connection, and at least one drawing land arranged between the adjacent lands is arranged inside the region. By drawing out the lands arranged in the diagonal position of the region and its vicinity through the wiring with priority, the wiring is drawn out from all the lands for drawing out and electrically connected to the via penetrating the core substrate, The land for via connection from which the wiring is not drawn out in the wiring layer formed on the one surface is the core base. And wherein the connecting vias electrically penetrating the. Also, the lands for via connection are arranged in a staggered arrangement selected from every other arrangement of lands arranged in a lattice.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the multilayer circuit board according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows a schematic configuration of an embodiment of a multilayer circuit board. The semiconductor device according to the present embodiment has a wiring layer 1 formed by laminating a plurality of layers on both surfaces of a core substrate 10 similarly to the semiconductor device shown in FIG.
2a and 12b are provided, and the via 16
And the connection electrodes 6 of the semiconductor chip 4 and the external connection terminals 14 are electrically connected by flip-chip connection.

As in the conventional example, in order to prevent the semiconductor device from warping, the number of wiring layers 12a formed on one surface of the core substrate 10 and the number of wiring layers 12b formed on the other surface are the same. On the wiring layer 12a on the side on which the semiconductor chip 4 is mounted, a wiring 7 is formed, one end of which is connected to the connection electrode 6 of the semiconductor chip 4 and the other end of which is drawn out from a region where the connection electrode 6 is arranged. . The difference between the configuration of the semiconductor device of the present embodiment and the conventional semiconductor device shown in FIG. 7 is that the lead-out wiring 7 is provided on one surface of the core substrate 10 and the other surface of the core substrate 10 is provided at the same time. The provision of the wiring electrically connected to the external connection terminal 14 is to reduce the total number of wiring layers constituting the semiconductor device by sharing the wiring on both sides of the core substrate 10.

The present invention relates to the arrangement of the wiring 7 for sharing the wiring on both sides of the core substrate 10 and minimizing the number of wiring layers 12a and 12b as described above.
Hereinafter, first, the wiring layer 12 on one surface of the core substrate 10 will be described.
The wiring 7 at a will be described.

FIGS. 2 to 5 show an arrangement example in which the wiring 7 is drawn out from the area where the lands are arranged in a 30 × 30 lattice.
The land has a land diameter of 130 μm and a land pitch of 350 μm
m, the wiring 7 has a wiring width of 70 μm,
It is drawn out according to the wiring rule of 0 μm.
FIG. 2 shows a method of drawing out lands and wirings 7 in a first wiring layer for bonding the semiconductor chip 4, and FIGS. 3 to 5 show methods of drawing out lands and wirings 7 provided in the second to fourth layers. In the drawing, one of the land areas arranged in a 30 × 30 grid is divided into four crosses, and the other areas are omitted. The layout of the lands and the wirings 7 in other regions than the illustrated one is symmetrical to the illustrated one.

In the first wiring layer shown in FIG. 2, all the connection electrodes 6 of the semiconductor chip 4 and the lands are connected.
Each land has one-to-one correspondence with the connection electrode 6, and the number of lands and the land arrangement interval match the number and arrangement interval of the connection electrodes 6. The lands provided in each wiring layer are arranged at the same interval as the lands in the upper layer, and are electrically connected between adjacent layers via vias. However, the land from which the wiring 7 is drawn out in the layer is electrically connected to the via 16 provided in the core substrate 10 on the drawing end side, and it is not necessary to form a land corresponding to the land in the next layer. FIG.
As shown in FIGS. 5 to 5, the reason why the number of lands in each layer decreases from the first layer to the fourth layer is that the lands that have been drawn out do not form lands in the next layer.

In the multilayer circuit board of this embodiment, the vias 16 provided on the core substrate 10 and the lands are electrically connected even in the plane area where the semiconductor chip 4 is mounted. When considering the wiring 7, first, a land for via connection to be electrically connected to the via 16 arranged in the plane area on which the semiconductor chip 4 is mounted is selected, and the land 16 for via connection is selected. The method of drawing out the wiring 7 is determined on the basis of the arrangement. The lands other than the via connection lands 16 are lead-out lands for connecting the wiring 7.

A resin substrate is usually used for the core substrate 10. However, when forming the vias 16 in the resin substrate, a hole is formed by drilling. It is necessary to secure about 500 μm. Since the land pitch in this embodiment is 350 μm, of the lands arranged in a lattice,
When selecting a land to be connected to the via 16 in the region where the is mounted, it is necessary to select at least an interval of about 400 μm.

In the first wiring layer shown in FIG. 2, a land 20 indicated by a black circle is selected as a land for via connection to be connected to the via 16 in a region where the lands are arranged, and is indicated by a white circle. The land 22 is selected as a land for drawing out the wiring 7. Since the land pitch of the embodiment is 350 μm, by selecting every other land arranged in a lattice, it is possible to secure a sufficient installation interval for forming the via 16. The via connection lands of the embodiment are staggered with every other land selected from a grid-like arrangement.

When the wiring 7 is drawn out from each wiring layer, the wiring 7 may be efficiently drawn out from the lead-out lands 22 excluding the via connection lands 20.
FIG. 2 shows an example of drawing out the wiring 7 in the first layer.
As shown in the drawing, even if the land 20 is selected as the land 20 for via connection, the land 20a for via connection arranged on the outer periphery of the land arrangement area is not used for via connection. The wiring 7 is arranged as a land from which the wiring 7 is drawn. This means that if the lands 20 for via connection remain in the outer peripheral row when the wiring 7 is pulled out, it hinders the drawing of the wiring 7 from the inner drawing land 22, and as a whole, the wiring 7 is efficiently drawn. Is no longer possible.

The wiring 7 can be drawn out from the inner lead-out land 22 by passing it between adjacent lands. However, when the wiring 7 is drawn out from the inner lead-out land 22, the semiconductor chip 4 The wiring 7 is preferentially extracted from the extraction lands 22b arranged in the vicinity of the diagonal line. When pulling out the wiring 7 from the inner drawing land 22, the wiring 7 is drawn out preferentially from the land 22 b at the diagonal position and the land 22 b near the diagonal line because of the conventional drawing method of drawing out the wiring 7 sequentially from the outer peripheral side. In this case, since many lands remain on the center side in the diagonal direction, priority is given to extraction from lands near the diagonal where lands tend to remain, so that the overall wiring extraction efficiency can be increased.

The method of drawing out the wiring 7 in the second layer shown in FIG. 3 is similar to the method described above. That is, the first
Of the lead-out lands 22 remaining except for the land pulled out by the layer, the lead-out lands 22 arranged on the outer peripheral side lead out the wiring 7 and
The wiring 7 is also drawn out of the via connection land 20a located at the outermost periphery of the via connection land 20. As for the inner drawing land 22, a portion near the diagonal is drawn out preferentially.

The method of drawing out the wiring 7 in the third layer shown in FIG. 4 is the same, and the wiring 7 is drawn out from the drawing land 22 and the via connection land 20 on the outermost periphery.
The inside drawing land 22 is drawn out preferentially from the land near the diagonal line. By arranging the wirings 7 in this manner, many lands 20 for via connection remain at the center.

FIG. 5 shows an arrangement of the wiring 7 in the fourth layer. In the fourth layer, the remaining lands 22 for drawing out the wiring 7 are slight, and the wiring 7 is drawn out from all of the lands 22 for drawing. In the fourth layer, the via connection lands 20 on the outermost periphery are connected to the wiring 7.
Is pulled out. Thus, with respect to the wiring layer 12a provided on one surface of the core substrate 10 in the multilayer circuit board of the present embodiment, the wiring 7 has been completely drawn out in a four-layer configuration with the wiring patterns shown in FIGS.

Of the lands formed on the fourth layer shown in FIG. 5, the lands to which the wiring 7 is not connected are lands 20 for via connection.
The wiring layer 12 electrically connected to the via 16 provided on the core substrate 10 and provided on the other surface of the core substrate 10
It is electrically connected to the land and wiring of b. The wiring for the wiring layer 12b provided on the other surface of the core substrate 10 may be obtained by extracting the wiring 7 only from the land 20 remaining in the fourth layer and electrically connecting to the external connection terminal 14. The lands 20 are arranged at the same interval as the vias 16 and the interval between the adjacent lands 20 is sufficient to extract the wiring 7, so that the wiring can be easily extracted from the wiring layer 12 b.

In this embodiment, the core substrate 10
The wiring does not become complicated for the wiring layer 12b provided on the other surface of the semiconductor device, so that a ground layer and a power supply layer commonly used are formed in addition to the lead-out wiring for connecting to the external connection terminal 14. It is possible.

Wiring layer 1 provided on the other surface of core substrate 10
2b is a wiring layer 12a provided on one surface of the core substrate 10.
And the same number of layers. In the present embodiment, the wiring layer 1 on one surface
Since 2a has a four-layer structure, the wiring layer 12b on the other surface also has four layers.
It has a layer structure. Thus, considering the number of layers on both sides of the core substrate 10, the semiconductor device of the present embodiment is 4 + 2 +
It will be completed with a four-layer structure of four. In the case of the conventional wiring method with a 30 × 30 grid land arrangement in the present embodiment, seven wiring layers are required on one side of the core substrate. Therefore, the conventional method requires a 16 layer configuration of 7 + 2 + 7. In comparison with the method, according to the method of the present embodiment, it is possible to greatly reduce the total number of layers.

As described above, forming wiring layers in multiple layers by a build-up method or the like involves considerable technical difficulties. Therefore, as described above, the wiring layers 12a provided on both surfaces of the core substrate 10 are provided. , 12b, respectively, to reduce the total number of wiring layers 12a, 12b is extremely effective in suppressing the occurrence of product defects and obtaining a highly reliable semiconductor device. In the above embodiment, a case of a 30 × 30 land arrangement has been described as an example. However, the concept of the present invention is applicable to land arrangements of various patterns having different land diameters, land pitches, wiring widths, wiring intervals, and the like. Although the above embodiment is an example in which one wiring is passed between adjacent lands, the present invention can be similarly applied to a case where two or more wirings can be passed between adjacent lands. is there.

[0026]

According to the multilayer circuit board of the present invention, as described above, a land for via connection and a land for extraction are selected, and a plurality of wirings are efficiently extracted, thereby forming a plurality of wirings on both surfaces of the core substrate. It is possible to reduce the number of wiring layers of the multilayer circuit board formed by laminating the wiring layers, thereby suppressing the occurrence of defects in the multilayer circuit board and improving the manufacturing yield, and reducing the manufacturing cost and reducing the reliability. It has a remarkable effect, such as being able to be provided as a highly productive product.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a cross-sectional configuration of a multilayer circuit board according to the present invention.

FIG. 2 is an explanatory diagram showing wiring on a first layer in the multilayer circuit board of the embodiment.

FIG. 3 is an explanatory diagram showing wiring in a second layer in the multilayer circuit board of the embodiment.

FIG. 4 is an explanatory diagram showing wiring in a third layer in the multilayer circuit board of the embodiment.

FIG. 5 is an explanatory diagram showing wiring in a fourth layer in the multilayer circuit board of the embodiment.

FIG. 6 is an explanatory view showing a method of mounting a semiconductor chip by flip chip connection.

FIG. 7 is an explanatory diagram showing a conventional configuration of a multilayer circuit board having a core board.

FIG. 8 is an explanatory diagram showing a conventional wiring drawing method.

[Explanation of symbols]

 Reference Signs List 4 semiconductor chip 5 circuit board 6 connection electrode 7 wiring 8 land 10 core substrate 12a, 12b wiring layer 14 external connection terminal 16 via 20, 20a land for via connection 22, 22a, 22b land for drawing out

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomoaki Takubo 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture

Claims (2)

[Claims] An electronic component having a plurality of connection electrodes arranged in a lattice pattern on one surface of a core substrate on which electronic components are mounted, the same arrangement as the connection electrodes of the electronic component, and via a via. A plurality of wiring layers having a land electrically connected between the layers and a wiring formed by being pulled out from the region where one end is connected to the land and the other end is arranged outside the land are stacked, On the other surface of the core substrate, a wiring formed on the wiring layer on the one surface and an external connection terminal mounted on a mounting surface of the core substrate through a via provided through the core substrate. In a multilayer circuit board formed by laminating the same number of wiring layers as the wiring layers formed on the one surface, the wiring layers provided with the wires to be electrically connected are formed on the one surface, There is an interval longer than the via interval provided on the core substrate. And a land for via connection selected in an arrangement in which the largest number of lands can be selected, and a lead-out land other than these via connection lands to which wiring is connected, and an area where the lands are arranged With respect to the lands located on the outer periphery, wires are drawn out from the lead-out lands and the via connection lands together, and the lead-out lands arranged inside the region have at least one land between adjacent lands. By preferentially pulling out the diagonal position of the region and lands arranged in the vicinity thereof through the book wiring, wiring is drawn out from all the drawing lands and electrically connected to vias penetrating the core substrate. The via connection lands from which the wiring is not drawn out in the wiring layer formed on the one surface are the same as those described above. A multilayer circuit board electrically connected to vias penetrating through the board. 2. The multilayer circuit board according to claim 1, wherein the lands for via connection are arranged in a staggered arrangement selected from every other arrangement of lands arranged in a lattice.