JP3664743B2 - Burn-in board - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a burn-in board used for testing a semiconductor device.
[0002]
2. Description of the Related Art In recent years, semiconductor devices have increased in number of high heat generating devices as the number of gate array type pins increases, and the speed has increased, and downsizing of package pins has been progressing in response to demand for miniaturization. As a result, various process failures and assembly failures at the time of manufacture are increasing, and it is necessary to perform burn-in.
[0003]
In addition, devices with different power supply pin arrangements in the same package are increasing, and the burn-in board used at the time of burn-in is forced to be multi-layered, and the response is required without shortening the supply time of the device.
[0004]
Therefore, it is necessary to provide a burn-in board that maintains the characteristics without reducing the number of mounted packages.
[0005]
[Prior art]
As the number of pins of a semiconductor device increases, the package becomes a PGA (Pin Grid Array) type, and a burn-in board for performing burn-in is also multilayered accordingly. In order to mitigate noise due to the narrow pin pitch, a ground (GND) is interposed for each layer.
[0006]
For example, a burn-in board for a PGA type semiconductor device in which pins are arranged at a pitch of 0.3 mm is composed of 6 layers, and the pin arrangement is 100 mils (2.54 mm) horizontally and vertically, and approximately 70 mils (1.796 mm) diagonally. The burn-in board for PGA type semiconductor devices is composed of 10 layers.
[0007]
FIG. 10 shows a pattern configuration diagram of a conventional burn-in board. 10A and 10B show one of a plurality of foot patterns of an IC socket into which a semiconductor device on a burn-in board is inserted. FIG. 10A shows six layers (five layers on a base substrate). 10B shows a case of 10 layers (9 layers on the base substrate).
[0008]
10A, pin patterns (for example, φ0.7 mm) 12 are regularly arranged at a pitch of 0.3 mm in each of the four regions 11a to 11d, and the outer two rows are the first layer. A lead pattern 13a is formed, and lead patterns 13b to 13e are sequentially formed in the second to fifth layers for each column. One of these lead patterns 13 a to 13 e is formed between the pin patterns 12.
[0009]
Then, the pins of the IC socket are inserted into the pin pattern 12 and soldered.
[0010]
In FIG. 10B, pin patterns 15 are arranged around the empty area 14 at a pitch of 100 mils in the horizontal and vertical directions and about 70 mils in the diagonal direction. The outer two rows are the first layer, and the lead pattern 16a (for example, width 0.35 mm, the same applies hereinafter) is formed, and the lead patterns 16a to 16h are sequentially formed from the second layer to the eighth layer for each row. The inner two rows are the ninth layer, and the lead pattern 16i is formed. Also in this case, one lead pattern 16 a to 16 i is formed between the pin patterns 15.
[0011]
Therefore, when the pin patterns 15 from the sixth layer to the ninth layer are normally assigned as power supply pins, the widths of the lead patterns 16f to 16i serving as power supply patterns are, for example, 0.35 mm, which is the same as that of the signal lead patterns 16a to 16e. It becomes.
[0012]
[Problems to be solved by the invention]
However, as mentioned above, when manufacturing burn-in boards for narrow pin pitch and high heat generation devices, increase the number of stacked boards and increase the power supply layer, or reduce the number of devices mounted. However, there is a problem that the manufacturing process is increased and the number of burn-in boards is increased, resulting in an increase in cost. In addition, when the burn-in board is made into a multilayer board, there is a problem that it takes days when producing repeats.
[0013]
Furthermore, since the power supply lead patterns 16f to 16i can be formed only with the same width as the signal lead patterns 16a to 16e, there is a problem that they are easily affected by noise due to power supply current fluctuations.
[0014]
Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a burn-in board that is easy to manufacture by reducing noise interference and reducing costs.
[0015]
[Means for Solving the Problems]
The above-mentioned problem is that a predetermined number of holding parts for holding a PGA type semiconductor device where burn-in is performed, lead holes into which a plurality of lead pins extending downward are inserted, and wiring patterns corresponding to the lead holes In the burn-in board formed, all the lead holes are formed, and the wiring pattern corresponding to the lead holes in a predetermined row is formed among the lead holes. A first substrate formed on each of the both surfaces and corresponding to the lead hole in which the wiring pattern is formed, the unnecessary length portion being cut and removed, and inserted and fixed; and the first pin in the lead pin insertion direction. The lead hole is formed so as to be superposed on the first substrate, and the lead hole is formed except for the lead hole in which the wiring pattern of the first substrate is formed. The wiring patterns corresponding to all or predetermined rows of the formed lead holes are formed on both surfaces, and the lead pins corresponding to the lead holes formed with the wiring patterns are unnecessary length portions. And the second substrate that is inserted and fixed by being cut and removed.
[0016]
Further, the wiring pattern is formed on a predetermined number of substrates located above the second substrate, the predetermined number being stacked below the second substrate according to the number of lead pins of the holding unit. The lead holes except for the lead holes are formed, and the wiring patterns corresponding to all or predetermined rows of the formed lead holes are formed on both sides, and the wiring patterns are formed. The lead pins corresponding to the lead holes are inserted and fixed by cutting off unnecessary length portions.
[0017]
[Action]
As described above, a predetermined number of substrates are arranged to overlap the first substrate and below in the lead pin insertion direction. These substrates are formed with lead holes corresponding to lead pins other than the lead pins that are inserted into a substrate positioned above, connected and fixed, and unnecessary length portions are cut off. Further, among the lead holes, wiring patterns corresponding to the lead holes in a predetermined row are respectively formed on both surfaces of each substrate, and the lead pins corresponding to the lead holes in which the wiring patterns are formed are cut off and removed by unnecessary length portions. Inserted and connected and fixed.
[0018]
In this way, since the substrates with wiring patterns formed on both sides are arranged according to the semiconductor device, it is cheaper and easier to manufacture than a multi-layer with a single substrate, without reducing the number of mounting, and in a short period of time. It becomes possible to manufacture with. In addition, the signal system and the power supply system can be separated from each other, and the power supply wiring pattern can be formed with a sufficient thickness to mitigate noise interference caused by power supply current fluctuations.
[0019]
【Example】
FIG. 1 shows a configuration diagram of an embodiment of the present invention. In FIG. 1A, a burn-in board 21 includes a first substrate 23 on which a predetermined number of IC sockets 22 which are holding portions for inserting and holding semiconductor devices (not shown) are mounted, and a first substrate 23. The second substrate 24, the third substrate 26, the fourth substrate 26, and the fifth substrate 27 are stacked in the insertion direction of lead pins (described later) of the IC socket 22.
[0020]
These first to fifth substrates 23 to 27 are attached with screws 29 with four spacers 28 interposed therebetween. Further, a connector (or a connection pin) 30 for supplying power and transmitting / receiving signals is provided at one end. Note that wiring patterns are formed on both surfaces of the first to fifth substrates 23 to 27 (described in FIGS. 2 to 6).
[0021]
Therefore, FIG. 1B shows an enlarged view of a portion of one socket 22, and the lead pin 31 of the IC socket 22 is inserted into the burn-in board 21. That is, as shown in FIG. 1C, lead holes 32 are formed in the first substrate 23 so as to correspond to all of the lead pins 31 of the IC socket 22, and the lead pins 31 a in the three outer rows of the lead pins 31. Is connected and fixed to the first substrate 23, and unnecessary length portions are cut and removed.
[0022]
Further, the lead pins 31b in the three outer rows of the lead pins 31 other than the lead pins 31a are connected and fixed to the second substrate 24, and unnecessary length portions are cut and removed. Among the remaining lead pins 31, the outer one row of lead pins 31c is connected and fixed to the third substrate 25, and unnecessary length portions are cut and removed. Further, among the remaining lead pins 31, the outer one row of lead pins 31d is the first one. 4 is fixedly connected to the substrate 26 and unnecessary length portions are cut and removed.
[0023]
Then, the innermost one row of lead pins 31e is connected and fixed to the fifth substrate 27, and unnecessary length portions are cut and removed.
[0024]
Incidentally, as described above, FIG. 1C shows the lead hole 32 formed in the first substrate 23. For example, the white portion is a signal system, the black portion is a power system, The innermost row in the system is the ground (GND). Therefore, when corresponding to the lead pins 31 (31 a to 31 e) of the IC socket 22 shown in FIG. 1B, the outer three rows of lead holes 32 a correspond to the lead pins 31 a connected and fixed to the first substrate 23. Further, the lead hole 32b corresponds to the lead pin 31b connected and fixed to the second substrate 24 disposed below. Similarly, the lead hole 32c is the lead pin 31c, the lead hole 32d is the lead pin 31d, and the lead hole 31e is the lead pin 31e. Correspond to each.
[0025]
Here, FIG. 1D shows a part of FIG. 1C, and the formation pitch of the lead holes 32 and the wiring pattern will be described.
[0026]
1 (C) and 1 (D), the lead holes 32 have, for example, a pitch of d ₁ = 100 mils (2.54 mm) in the horizontal and vertical directions, and an array formed with d ₂ = about 70 mils (1.796 mm) in the diagonal direction. Is done. Further, the lead pattern 33 drawn out from the signal system lead holes 32a and 32b may be a power system for the signal system lead holes 32a and 32b depending on different devices. If a current of 400 mmA per pin flows, it is formed with a width of 0.4 mm (1 mm per 1A). Therefore, when the lead pattern 33a is formed with a width of 0.4 mm, the distance d ₄ between the lead holes 32a and 32b and the lead pattern 33 is 0.35 mm.
[0027]
2 to 6 are explanatory diagrams of the double-sided patterns of the first to fifth substrates of FIG. 2 to 6, black portions are shown as lead holes in which patterns are formed.
[0028]
FIG. 2 shows the first substrate 23, FIG. 2A shows the component surface (surface on which the IC socket 22 is mounted), and FIG. 2B shows the solder surface (back surface). That is, lead holes 32 (32a to 32e) corresponding to all the lead pins 31 (31a to 31e) of the IC socket 22 to be mounted are formed in the first substrate 23. The lead holes 32 to be formed are formed with land portions (not shown) for connecting and fixing with solder on both sides of the substrate (the same applies to the following).
[0029]
On the component side shown in FIG. 2A, lead patterns 33 serving as signal lines are formed in the outer two rows of lead holes 32a, and on the solder side shown in FIG. A pattern 33 is formed. Note that the land portion and the lead pattern described above become a wiring pattern on the substrate.
[0030]
As shown in FIG. 1B, the lead pin 31 of the IC socket 22 is inserted into the lead hole 32 and connected and fixed by solder, and the unnecessary length portion of the lead pin 31a is cut and removed. .
[0031]
FIG. 3 shows the second substrate 24, FIG. 3 (A) shows the component surface, and FIG. 3 (B) shows the solder surface. In the second substrate 24 shown in FIGS. 3A and 3B, lead holes 32b to 32e other than the lead hole 32a in which the lead pattern 33 is formed on the first substrate 23 positioned above are formed. Is done.
[0032]
In the component surface shown in FIG. 3A, lead-out patterns 33 serving as signal lines are formed in the outer two rows of lead holes 32b, and in the solder surface shown in FIG. 3B, the lead holes 32b in the third row from the outside are formed. A drawer pattern 33 is formed. Then, as shown in FIG. 1 (B), the lead pin 31b of the IC socket 22 is inserted into the lead hole 32b in which the lead pattern 33 is formed, connected and fixed by solder, and unnecessary length portions are cut and removed. The
[0033]
FIG. 4 shows a third substrate, FIG. 4A shows the component surface, and FIG. 4B shows the solder surface. In the third substrate 25 shown in FIGS. 4A and 4B, other than the lead holes 32a and 32b in which the lead pattern 33 is formed on the first and second substrates 23 and 24 positioned above. Lead holes 32c to 32e are formed.
[0034]
In the component surface shown in FIG. 4A and the solder surface shown in FIG. 4B, a power supply surface 34 is formed as a wiring pattern including only the outer row of lead holes 32c. Then, as shown in FIG. 1B, the lead pin 31c of the IC socket 22 is inserted into the lead hole 32c in which the power supply solid surface 34 is formed and connected and fixed by solder, and unnecessary length portions are cut and removed. The
[0035]
FIG. 5 shows the fourth substrate 26, in which FIG. 5A shows the component surface and FIG. 5B shows the solder surface. In the fourth substrate 26 shown in FIGS. 5A and 5B, other than the lead holes 32a to 32c in which the lead pattern 33 is formed on the first to third substrates 23 to 25 positioned above. Lead holes 32d and 32e are formed.
[0036]
On the component surface shown in FIG. 5A and the solder surface shown in FIG. 5B, a power supply surface 34 is formed as a wiring pattern including only the outer row of lead holes 32d. Then, as shown in FIG. 1 (B), the lead pin 31 of the IC socket 22 is inserted into the lead hole 32d in which the power supply solid surface 34 is formed, connected and fixed by solder, and unnecessary length portions are cut and removed. Is done.
[0037]
FIG. 6 shows the fifth substrate 27, FIG. 6A shows the component surface, and FIG. 6B shows the solder surface. In the fifth substrate 27 shown in FIGS. 6A and 6B, other than the lead holes 32 a to 32 d in which the lead pattern 33 is formed by the first to fourth substrates 23 to 26 positioned above. An inner lead hole 32e is formed.
[0038]
In the component surface shown in FIG. 6A and the solder surface shown in FIG. 6B, a power supply surface 34 is formed as a wiring pattern including only the outer row of lead holes 32e.
[0039]
As shown in FIG. 1B, the lead pin 31e of the IC socket 22 is inserted into the lead hole 32e in which the power supply surface 34 is formed, and is connected and fixed by solder.
[0040]
In mounting the IC socket 22 on the burn-in board 21 composed of the first to fifth substrates 23 to 27 shown in FIGS. 2 to 6, the IC socket 22 is first inserted into the first substrate 23 and soldered. After the attachment, the lead pin 31a is cut, and then the remaining lead pins 31b to 31e are inserted into the second substrate 24 and soldered, and then the lead pin 31b is cut and then soldered and lead-cut to perform mounting. May be.
[0041]
In addition, the first to fifth substrates 23 to 27 are stacked and assembled. On the other hand, the lead pins 31 of the IC socket 22 are cut to a predetermined length in advance, and the first IC socket 22 is stacked. It may be mounted by inserting into the lead holes 32a to 32e of the fifth substrates 23 to 27 and soldering by solder reflow or the like.
[0042]
In this way, when performing burn-in of a multi-pin narrow pitch, high heat-generating semiconductor device, it is possible to manufacture at a lower cost than by stacking single substrates by stacking double-sided substrates without reducing the number of mounted devices. It is easy and can be manufactured in a short period of time. Further, the signal system and the power supply system (including the ground GND) can be separated by the first to fifth substrates 23 to 27, and the power supply wiring pattern can be formed on the power supply plane 34, thereby providing the power supply current. It is possible to mitigate noise interference caused by fluctuation.
[0043]
Next, FIG. 7 shows a configuration diagram of another embodiment of the present invention. FIG. 7 shows a part of the burn-in board 21 (one IC socket), and the first substrate 41 and the second substrate each having wiring patterns (described in FIGS. 8 and 9) formed on both surfaces. An IC socket 43 is mounted on these boards. In this case, among the lead pins 44 of the IC socket 43, the outer three rows of lead pins 44a are inserted into the first substrate 41 and fixed by soldering, and unnecessary length portions are cut and removed. The remaining three rows of lead pins 44b are inserted into the second substrate 42 and connected and fixed by solder.
[0044]
Thereby, like the said Example, it can manufacture at low cost, easy manufacture, and a short period of time.
[0045]
8 and 9 are explanatory views of the double-sided patterns of the first and second substrates of FIG.
[0046]
FIG. 8 shows the first substrate 41, FIG. 8A shows the component surface, and FIG. 8B shows the solder surface. Corresponding to all of the lead pins 44 of the IC socket 43, the first substrate 41 is formed with lead holes 46 having a diameter of 0.7 mm at a pitch of 0.3 mm, for example, in the four regions 45a to 45d.
[0047]
In the component surface of FIG. 8A, lead patterns 47 are formed as wiring patterns in the two outer rows of lead holes 46a of the lead holes 46, and in the solder surface of FIG. 8B, the third row of lead holes 46a from the outside. A drawer pattern 47 is formed on the substrate. The lead holes 46 a on both sides correspond to the lead pins 44 a of the IC socket 43.
[0048]
In other words, the lead pin 44a of the IC socket 43 is inserted into the lead hole 46a and connected and fixed by solder, and an unnecessary length portion is cut and removed.
[0049]
FIG. 9 shows the second substrate 42, FIG. 9A shows the component surface, and FIG. 9B shows the solder surface. Of the lead holes 46 corresponding to the lead pins 44 of the IC socket 43 in the four regions 45a to 45d, the second board 42 has lead holes other than the lead holes 46a in which the lead pattern 47 is formed on the first board 42. 46b is formed. The lead hole 46 b corresponds to the lead pin 44 b of the IC socket 43.
[0050]
9A, lead patterns 47 are formed as wiring patterns in the outer two rows of lead holes 46b of the lead holes 46b, and in the innermost row of lead holes 46b in the solder surface of FIG. 9B. A lead pattern 47 is formed.
[0051]
The lead pin 44b of the IC socket 43 is inserted into the lead hole 46b and connected and fixed by solder.
[0052]
【The invention's effect】
As described above, according to the present invention, a predetermined number of substrates on which wiring patterns are formed on both sides are arranged in accordance with the semiconductor device to be burned in, and the lead pins of the holding portion are sequentially connected and fixed to each substrate to eliminate unnecessary length. By adopting a configuration in which the portion is cut and removed, the noise interference can be reduced and the cost can be reduced, and the manufacturing can be facilitated and the manufacturing can be performed in a short time.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a double-sided pattern of the first substrate of FIG.
3 is an explanatory diagram of a double-sided pattern of the second substrate of FIG. 1. FIG.
FIG. 4 is an explanatory diagram of a double-sided pattern of the third substrate of FIG.
5 is an explanatory diagram of a double-sided pattern of the fourth substrate in FIG. 1. FIG.
6 is an explanatory diagram of a double-sided pattern of the fifth substrate in FIG. 1. FIG.
FIG. 7 is a configuration diagram of another embodiment of the present invention.
8 is an explanatory diagram of a double-sided pattern of the first substrate of FIG. 7. FIG.
FIG. 9 is an explanatory diagram of a double-sided pattern of the second substrate of FIG.
FIG. 10 is a pattern configuration diagram of a conventional burn-in board.
[Explanation of symbols]
21 Burn-in board 22, 43 IC socket 23, 41 First substrate 24, 42 Second substrate 25 Third substrate 26 Fourth substrate 27 Fifth substrate 28 Spacer 29 Screw 30 Connector 31, 44 Lead pins 32, 46 Lead holes 33, 47 Drawer pattern 34 Power supply surface

Claims (4)

There are lead holes (32, 46) into which a plurality of lead pins (31, 44) extending downward of a predetermined number of holding parts (22, 43) holding PGA type semiconductor devices where burn-in is performed. In the burn-in board formed and formed with wiring patterns (33, 34, 47) corresponding to the lead holes (32, 46), for mounting the holding portions (22, 43), The lead holes (32, 46) are formed, and the wiring patterns (33, 47) corresponding to the lead holes (32a, 46a) in a predetermined row of the lead holes (32, 46) are formed on both sides. The lead pins (31a, 44a) corresponding to the lead holes (32a, 46a) in which the wiring patterns (33, 47) are formed are inserted after cutting unnecessary length portions. A first substrate connected fixed (23 and 41),
The wiring pattern (33, 47) of the first substrate (23, 41) is formed so as to overlap the first substrate (23, 41) in the lead pin insertion direction. The lead holes except the lead holes (32a, 46a) are formed, and the wiring patterns (33, 46b) corresponding to all or predetermined rows of the lead holes (32b, 46b) among the formed lead holes. 47) is formed on both surfaces, and the lead pins (31b, 44b) corresponding to the lead holes (32b, 46b) in which the wiring patterns (33, 47) are formed are inserted by cutting off unnecessary length portions. And the second substrate (24, 42) to be connected and fixed;
A burn-in board characterized by comprising: A board (25-27) arranged in a predetermined number below the second board (24) according to the number of lead pins (31) of the holding part (22), and located above. The lead holes except for the lead holes in which the wiring patterns are formed on a predetermined number of substrates are formed, and the wiring patterns (33 corresponding to all or predetermined rows of the formed lead holes). , 34) are formed on both sides, and the lead pins (31c-31e) corresponding to the lead holes (32c-32e) in which the wiring patterns (33, 34) are formed are removed by cutting off unnecessary length portions. The burn-in board according to claim 1, wherein the burn-in board is inserted and fixed. The wiring pattern formed on any one of the substrates includes a land portion for connecting and fixing the lead pins (31, 44), a signal line (33, 47), and a power line or a power plane (34). 3. The burn-in board according to claim 1, wherein the burn-in board is formed including at least one of them. The connection part (30) which supplies a power supply to the said 1st board | substrate (23, 41) and the following board | substrates (24-27, 42) which were piled up, and transmits / receives a signal is provided. Item 3. Burn-in board according to item 1 or 2.

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