JP5587283B2 - Power supply circuit and control method of power supply circuit - Google Patents

Description

  The present invention relates to a power supply circuit and a control method for the power supply circuit.

  As a conventional power supply circuit, a circuit as shown in FIG. 1 is known (see Patent Document 1). The power supply circuit amplifies a difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage to generate an error voltage, and generates a desired output voltage from the input voltage so as to reduce the error voltage In the predetermined period after the power supply device is started, the upper limit value of the error voltage is lower than a steady value, and the higher the input voltage is, the higher the input voltage is. This is a power supply device having a clamp circuit that is set to be lower as the height is higher.

JP 2009-44779 A

  According to the conventional power supply circuit shown in FIG. 1, in the power supply device using the PWM dimming signal, soft start with no dependency on input voltage and excellent response speed can be realized.

  However, in the conventional power supply circuit shown in FIG. 1, when the input voltage (VIN) rapidly decreases in the steady state after the start-up is completed, the step-up ratio changes in an increasing direction, so that the output voltage (VOUT) ) Takes time to return until the load (LED) can be driven at a constant current, and during that period, the current value (ILED) flowing through the load (LED) decreases. Since the power supply circuit performs a boosting operation only when the dimming signal (DIM) is HIGH, flickering occurs when the load (LED) is a light emitting element such as an LED element. The dimming signal (DIM) is a signal for intermittently operating the boost converter unit (930).

  In order to facilitate comparison with the present invention, the timing chart of FIG. 2 showing each signal in the conventional power supply circuit described above is a constant instead of a resistance element connected between the load (LED) and the ground. The operation when a current source is provided is shown, and the constant current source is also turned on when the dimming signal (DIM) is HIGH and turned off when the light control signal is LOW.

  During the period (a) in the steady state, the input voltage (VIN) is controlled to the desired output voltage (VOUT) by the drive signal (PWM), and the current flowing through the load (LED) is also stable.

  However, during the period of (b) when the input voltage (VIN) suddenly decreases, when the dimming signal (DIM) is in the LOW state, the constant current source is off, so the output voltage (VOUT) does not decrease. When the optical signal (DIM) becomes HIGH, the constant current source is turned on and current starts to flow through the load (LED), so that the output voltage (VOUT) also rapidly decreases. Since the output voltage (VOUT) is not boosted enough to drive the load (LED) at a constant current, the current (ILED) flowing through the load (LED) decreases, and flickers when the load (LED) is a light emitting element. It is not preferable because it will be confirmed.

  After the output voltage (VOUT) rapidly decreases, the duty ratio of the drive signal (PWM) gradually increases and the output voltage (VOUT) also gradually increases. And the electric current (ILED) which flows into load (LED) also becomes high gradually. However, when the duty ratio of the dimming signal (DIM) is low, the time required until the output voltage (VOUT) is sufficiently boosted becomes long, and the flicker phenomenon becomes remarkable.

  Therefore, an object of the present invention is to control a power supply circuit and a power supply circuit capable of driving the load at a constant current while suppressing a decrease in the value of the current flowing through the load even when the input voltage is suddenly reduced. Is to provide a method.

  An aspect of the present invention devised to achieve the above object includes a converter unit that converts an input voltage and outputs an output voltage for driving a load, and a regulator for intermittently operating the converter unit. When a light signal is input, the power supply circuit includes a control unit that outputs a drive signal to the converter unit to perform a step-up / step-down operation. The control unit has the input voltage decreased below a predetermined value. When this is detected, the drive signal is output to the converter unit even if the dimming signal is not input.

  Another aspect of the present invention devised to achieve the above object includes a converter unit that converts an input voltage and outputs an output voltage for driving a load, and an intermittent operation of the converter unit. A control method of a power supply circuit including a control unit that outputs a drive signal to the converter unit to perform a step-up / down operation when a dimming signal is input, wherein the input voltage is lower than a predetermined value And detecting that the input voltage is lower than the predetermined value in the first step, the converter unit outputs the drive signal even if the dimming signal is not input. The second step of outputting to

  In each of the above aspects, it is preferable to output the drive signal to the converter unit for a certain period when it is detected that the input voltage has decreased below the predetermined value. It is preferable that it is equal to or longer than the time required for returning the load to a voltage that can drive the load.

  According to the power supply circuit and the control method for the power supply circuit of the present invention, in the power supply circuit that performs PWM dimming control, when the input voltage suddenly decreases, the current value flowing through the load is prevented from decreasing and the load is determined. Current drive is possible.

It is a block diagram showing an example of the power supply circuit using the prior art PWM dimming control. 3 is a timing chart for explaining a control method in the power supply circuit shown in FIG. 1. It is a block diagram which shows the principle structure of the power supply circuit which concerns on this invention. 3 is a timing chart for explaining the operation of the power supply circuit according to the present invention and the control method for the power supply circuit according to the present invention. It is a block diagram which shows the specific structure of this invention circuit. It is a circuit diagram which shows the drive circuit 100 in FIG. 5 in detail. 3 is a timing chart showing the operation of the drive circuit 100. It is a circuit diagram which shows the constant current part 10 in FIG. 5 in detail. It is a circuit diagram which shows the 1st signal generation part 200 in FIG. 5 in detail. FIG. 6 is a circuit diagram illustrating in detail a second signal generation unit 300 in FIG. 5. FIG. 6 is a circuit diagram illustrating in detail a third signal generation unit 400 in FIG. 5. FIG. 6 is a circuit diagram showing in detail a control signal generation circuit 510 in FIG. 5. FIG. 6 is a circuit diagram illustrating in detail a dimming signal generation circuit 520 in FIG. 5.

<Principle Configuration of Power Supply Circuit According to the Present Invention>
The power supply circuit shown in FIG. 3 has a terminal (N1) to which an input voltage (VIN) is connected, a terminal (N2) and a terminal (N3) to which a load (LED) is connected, and one end of the terminal (N1). A boost converter unit (30) having a coil (L) to be connected and a power MOS-FET (M1) as an output transistor, a constant current unit (10) connected to a terminal (N3), and an input voltage (VIN) A control unit (20) that outputs a drive signal (PWM) to a power MOS-FET (M1) that generates an output voltage (VOUT) from the terminal to the terminal (N2). The boost converter unit (30) converts the input voltage (VIN) and outputs an output voltage (VOUT) for driving the load.

  When the first dimming signal (DIM1) is input, the control unit (20) outputs a drive signal (PWM) to the boost converter unit (30), and the input voltage (VIN) has decreased below a predetermined value. When this is detected, the drive signal (PWM) is output to the boost converter unit (30) even if the first dimming signal (DIM1) is not input.

  The control unit (20) includes a dimming signal control circuit (500) and a drive circuit (100). The drive circuit (100) generates and outputs a drive signal (PWM) based on the feedback voltage (VFB) based on the output voltage (VOUT) and the second dimming signal (DIM2).

  When the first dimming signal (DIM1), which is a PWM dimming signal, is input to the dimming signal control circuit (500), the second dimming signal (DIM2) is output. The first dimming signal (DIM1) is a signal for causing the boost converter unit (30) to operate intermittently. The dimming signal control circuit (500) can also output the second dimming signal (DIM2) regardless of the first dimming signal (DIM1). That is, the dimming signal control circuit (500) converts the first signal (S1) based on the current flowing through the load (LED), the second signal (S2) based on the output voltage (VOUT), and the input voltage (VIN). Based on at least one signal selected from the group consisting of the third signal (S3) based on this, when the input voltage (VIN) falls below a predetermined value, the drive signal (PWM) is sent to the power MOS-FET (M1). ) Is output for a certain period, a second dimming signal (DIM2) is generated. The predetermined period is preferably equal to or longer than the time required for the output voltage (VOUT) to return the load (LED) to a voltage that can drive the constant current.

  In order to reduce the noise component, the capacitor (C1) is connected to the terminal (N1). In order to store the energy stored in the coil (L), the capacitor (C2) is connected to the terminal (N2). In order to realize efficient operation, the first dimming signal (DIM1) is input to the constant current unit (10) in addition to the dimming control circuit (500). Moreover, the LED element is used as load (LED).

  The present embodiment is an example in which the present invention is applied to a power supply circuit having a boost converter unit. However, the present invention can be applied not only to a boost converter but also to a power supply circuit having a step-down converter.

<Operating principle>
(1) Steady state (period (a) in FIG. 4)
When the input voltage (VIN) is constant and the output voltage (VOUT) is also kept constant, the first dimming signal (DIM1) is output as it is as the second dimming signal (DIM2).

  Then, the drive circuit (100) outputs a drive signal (PWM) for converting the input voltage (VIN) into a desired output voltage (VOUT) based on the feedback voltage (VFB) and the second dimming signal. To do.

(2) When the input voltage (VIN) suddenly drops (period (b1) in FIG. 4)
Next, an operation when the input voltage (VIN) is rapidly decreased will be described.

  In the conventional power supply device shown in FIG. 1, when the input voltage (VIN) suddenly decreases as shown in FIG. 2, the dimming signal (DIM) becomes HIGH and the current starts to flow to the load (LED). Since the output voltage (VOUT) also decreased and the current flowing through the LED element decreased until the steady state was restored, flickering occurred.

  In the power supply circuit of the present invention shown in FIG. 3, it is possible to detect from the first to third signals that the input voltage (VIN) has dropped sharply. The second dimming signal (DIM2) when at least one of the first to third signals indicates that the input voltage (VIN) has dropped sharply is the first dimming signal. Regardless of (DIM1), the drive signal (PWM) is output to the power MOS-FET (M1) constituting the boost converter section (30) for a certain period. During this period, the duty ratio of the drive signal (PWM) increases, and the output voltage (VOUT) immediately rises. When the first dimming signal is turned on during or after the lapse of a certain period, a current flows through the LED element of the load (LED) due to the increased output voltage (VOUT). It is possible to suppress flickering of the LED element.

  When the first dimming signal is turned on, the duty ratio of the drive signal (PWM) gradually decreases and the output voltage (VOUT) gradually decreases.

  Finally, the duty ratio of the drive signal (PWM) becomes a predetermined value, and the value of the output voltage (VOUT) also becomes a predetermined value.

  Thus, since a current flows through the LED element of the load (LED) due to the increased output voltage (VOUT), a sufficient current flows through the LED element, and flickering of the LED element can be suppressed.

  That is, when the output voltage (VOUT) is lower than the forward voltage of the LED element when driven at a constant current, the current flowing through the LED element is reduced, and flickering occurs. However, according to the power supply circuit shown in FIG. Since the output voltage (VOUT) can be made sufficiently higher than the forward voltage of the LED element when driven at a constant current, a sufficient current flows through the LED element, and flickering of the LED element can be suppressed. .

  FIG. 5 is a block diagram showing a specific configuration of the circuit of the present invention. In the power supply circuit shown in the figure, the dimming signal control circuit (500) includes a control signal generation circuit (510) and a dimming signal generation circuit (520), and the control signal generation circuit (510) includes a first signal. The third signal (S1 to S3) is input, and the dimming signal control signal (S10) is output. The dimming signal generation circuit (520) is connected to the terminal (N5) to which the first dimming signal (DIM1) is input, and further receives the dimming signal control signal (S10).

  In addition, the first signal generation unit (200) that receives the signal from the constant current unit (10) and generates the first signal (S1) based on the current flowing through the load (LED), and the signal from the terminal. A second signal generator (300) for generating a second signal (S2) based on the output voltage (VOUT) and a third signal (S3) based on the input voltage (VIN) upon receiving a signal from the terminal Is further provided with a third signal generation unit (400).

  By adopting the above configuration, when the first dimming signal (DIM1) is inputted from the terminal (N5) to the dimming signal generation circuit (520) in the steady state, the inputted first dimming signal. (DIM1) is output to the drive circuit (100) as the second dimming signal (DIM2) for the drive circuit (100) to generate the drive signal (PWM).

  On the other hand, when the input voltage (VIN) suddenly decreases, the control signal generation circuit (510) detects the decrease by the first to third signals, and even if the first dimming signal (DIM1) is not input. A control signal for controlling the dimming signal generation circuit (520) is generated so that the optical signal generation circuit (520) generates the second dimming signal (DIM2), and the dimming signal generation circuit (520) is generated. Output. That is, it consists of a first signal (S1) based on the current flowing through the load (LED), a second signal (S2) based on the output voltage (VOUT), and a third signal (S3) based on the input voltage (VIN). Based on at least one signal selected from the group, the drive signal (PWM) is supplied to the power MOS-FET (M1), which is an output transistor, for a certain period (in FIG. 4), regardless of the first dimming signal (DIM1). It is possible to easily realize the generation of the second dimming signal (DIM2) to be output during a period in which S10 indicates a low level. The predetermined period is preferably a time required for the output voltage (VOUT) to return to a voltage that can drive the load (LED) at a constant current or longer.

  For example, the current itself flowing through the load (LED) is used as the first signal (S1), the output voltage (VOUT) itself is used as the second signal (S2), or the input voltage (VIN) itself is used as the third signal. (S3) can be used, but the input voltage (VIN) is drastically increased by including the signal generators (200, 300, 400) that generate the first to third signals (S1 to S3). A configuration for determining whether or not the voltage has decreased is preferable for efficient and highly accurate determination.

  In the circuits of FIGS. 3 and 5 described above, preferably, the constant current unit (10), the control unit (20), the power MOS-FET (M1), and the resistor (R) are integrated as a driver IC and are externally attached. Terminals (N1, N3, N4, N5) can be provided as terminals. A terminal (N2) may be further provided as an external terminal.

<Specific Example of Drive Circuit 100>
The circuit shown in FIG. 6 is an example of a specific circuit of the drive circuit (100) in FIG.

  The drive circuit (100) is a step-up PWM control DC-DC converter including an error amplifier (101), a switch (102), a PWM comparator (103), a flip-flop circuit (104), and a multiplexer (105). . When the first dimming signal (DIM1) is HIGH by the multiplexer (105), the driving circuit (100) uses the feedback voltage (VFB) as a feedback voltage, and the first dimming signal (DIM1) is LOW. At this time, a voltage (VREF−α) slightly smaller than the reference voltage (VREF) is used as the feedback voltage (where 0V <α <VREF). The error amplifier (101) amplifies the difference between the output signal (VFB1) of the multiplexer (105) that is input to the inverting input terminal and the reference voltage (VREF) that is input to the non-inverting input terminal, and the COMP terminal voltage, which is an error voltage. (COMP). When the output signal (VFB1) of the multiplexer (105) is larger than the reference voltage (VREF), the COMP terminal voltage (COMP) decreases. When the output signal (VFB1) of the multiplexer (105) is smaller than the reference voltage (VREF), the COMP terminal voltage (COMP) increases. The switch (102) is turned on when the second dimming signal (DIM2) is HIGH. It turns off when the second dimming signal (DIM2) is LOW, and holds the COMP terminal voltage (COMP). Since the held COMP terminal voltage (COMP) is a voltage corresponding to the switch-on time of the power MOS-FET (M1), when the second dimming signal (DIM2) is switched from LOW to HIGH, a predetermined Outputs a PWM signal with a duty ratio that is a switch-on time.

  The PWM comparator (103) uses a signal (SLOPE + SENSE) obtained by adding the sense current signal (SENSE) of the power MOS-FET (M1) and the slope compensation signal (SLOPE) as shown in the timing chart of FIG. 7 as a non-inverting input terminal. When compared with the COMP terminal voltage (COMP) input to the inverting input terminal and the inverting input terminal is larger than the non-inverting input terminal, the output becomes LOW and the inverting input terminal is the non-inverting input. When it is smaller than the terminal, its output becomes HIGH, and the flip-flop circuit (104) is reset. In the flip-flop circuit (104), the Q output is held HIGH at the rising edge of the clock (CLOCK), and the power MOS-FET (M1) is turned on. When the output of the PWM comparator (103) is HIGH, it is reset and the Q output becomes LOW, and the power MOS-FET (M1) is turned off. Further, by taking the AND of the Q output and the clock (CLOCK), there is a period in which the power MOS-FET is always turned off while the clock (CLOCK) is LOW. In this way, the switch-on time of the power MOS-FET is generated. When the load increases, the switch on time increases, and when the load decreases, the switch on time decreases.

<Specific Example of Constant Current Unit 10>
The circuit shown in FIG. 8 is an example of a specific circuit of the constant current unit (10).

  The constant current unit (10) has a power MOS-FET (M2) whose drain is connected to the terminal (N3), a source connected to the ground via the resistor RM2, and an inverting input terminal that is a power MOS-FET (M2). A first comparator (11) composed of an operational amplifier having a non-inverting input terminal connected to the first reference voltage (VREF1) and an output connected to the power MOS-FET (M2). Prepare. From the viewpoint of synchronizing with the first dimming signal (DIM1), the first dimming signal (DIM1) is input to the enable terminal of the first comparator (11) in FIG. The first comparator (11) is enabled during a period corresponding to the ON period of the first dimming signal (DIM1). During the off period of the first dimming signal (DIM1), the first comparator (11) is disabled, and by setting its output to LOW, the power MOS-FET (M2) is turned off and no current flows.

  A first reference voltage (VREF1) for flowing a desired current to the load (LED) is input to the non-inverting input terminal of the first comparator (11), and the current determined by the resistor RM2 is sunk from the terminal (N3). The At this time, the output of the first comparator (11) is stabilized at a certain voltage depending on the capability of the power MOS-FET (M2).

<Specific Example of First Signal Generation Unit 200>
The circuit shown in FIG. 9A is an example of a specific configuration of the first signal generation unit (200) in the power supply circuit shown in FIG. 5, and the second reference voltage ( VREF2) is connected and the output of the first comparator (11) connected to the non-inverting input terminal is based on the current flowing in the load (LED) by the output of the second comparator (201) composed of an operational amplifier. A first signal (S1) is generated.

  When the input voltage (VIN) rapidly decreases, the output voltage (VOUT) decreases, and the current flowing through the load (LED) also decreases rapidly. Therefore, the first comparator (10) of the constant current unit (10) 11) raises its output to try to pass load current. At this time, when the output of the first comparator (11) becomes equal to or higher than the second reference voltage (VREF2) connected to the inverting input terminal of the second comparator (201), the first signal (S1) becomes HIGH. This makes it possible to determine that the input voltage (VIN) has dropped sharply.

<Another Specific Example of First Signal Generation Unit 200>
The circuit shown in FIG. 9B is another example of the specific configuration of the first signal generator (200) in the power supply circuit shown in FIG. 5, and the third reference is connected to the non-inverting input terminal. The voltage (VREF3) is connected, and the source of the power MOS-FET (M2) is connected to the inverting input terminal. By the output of the second comparator (202) composed of an operational amplifier, the current flowing to the load (LED) is changed. A first signal (S1) based on is generated.

  Similarly to the description of FIG. 9A, when the input voltage (VIN) rapidly decreases, the output voltage (VOUT) decreases, and the current flowing through the load (LED) also decreases rapidly. Since the source voltage of the MOS-FET (M2) becomes LOW, the third reference voltage (VREF3) becomes larger, the output of the third comparator (202) becomes HIGH, and the input voltage (VIN) suddenly increases. It becomes possible to determine that it has been lowered.

<Specific Example of Second Signal Generation Unit 300>
The circuit shown in FIG. 10 is an example of a specific circuit of the second signal generation unit (300) in the power supply circuit shown in FIG.

  The second signal generation unit (300) includes a third comparator configured by an operational amplifier in which the terminal (N3) is connected to the inverting input terminal and the fourth reference voltage (VREF4) is connected to the non-inverting input terminal. Based on the output of (301), a second signal (S2) based on the output voltage (VOUT) is generated.

  Similarly to the description of FIG. 9A, when the input voltage (VIN) rapidly decreases, the current flowing through the load (LED) also decreases rapidly. Therefore, the drain voltage of the transistor (M2) is the fourth reference. It becomes smaller than the voltage (VREF4), the output of the third comparator (301) becomes HIGH, and it is possible to determine that the input voltage (VIN) has dropped rapidly.

<Specific Example of Third Signal Generation Unit 400>
The circuit shown in FIG. 11 is an example of a specific circuit of the third signal generation unit (400) in the power supply circuit shown in FIG.

  In the third signal generation unit (400) in FIG. 11, the fifth reference voltage (VREF5) is input to the non-inverting input terminal, and the voltage based on the input voltage (VIN) is input to the inverting input terminal. A third signal (S3) based on the input voltage (VIN) is generated by the output of the comparator (401).

  When the input voltage (VIN) rapidly decreases, the non-inverting input terminal voltage of the operational amplifier (402) decreases and the circuit operates to return to the sixth reference voltage (VREF6). At that time, when the non-inverting input terminal voltage of the operational amplifier (402) becomes equal to or lower than the fifth reference voltage (VREF5) which is the non-inverting input terminal voltage of the comparator (401), the output of the fourth comparator (401) is HIGH. Thus, it is possible to determine that the input voltage (VIN) has dropped rapidly.

<Specific Example of Control Signal Generation Circuit 510>
The circuit shown in FIG. 12A is an example of a specific circuit of the control signal generation circuit (510) in the power supply circuit shown in FIG.

  According to the control signal generation circuit (510) of FIG. 12A, when the reset terminal (R) of the flip-flop (512) is HIGH, the output terminal (QB) becomes HIGH, and the dimming signal control signal (S10 ) Becomes HIGH, so that the normal mode is set.

  The signal at the output terminal (QB) is input to the reset terminal of the timer (513). The output of the timer (513) is LOW when the reset terminal (R) is HIGH.

  The output terminal (QB) of the flip-flop (512) is latched LOW at the rising edge of S1, S2 or S3. The reset of the timer (513) is canceled by latching the output terminal (QB) of the flip-flop (512) to LOW. The timer (513) outputs HIGH after outputting LOW for a certain period after the reset is released. Thereby, the dimming signal control signal (S10) becomes LOW for a certain period and shifts to the forced boosting mode.

  Here, the forced boost mode is a mode in which the drive circuit (100) is operated with the dimming DUTY set to 100% regardless of the first dimming signal (DIM1). The normal mode is a mode in which the drive circuit (100) and the constant current unit (10) operate with the first dimming signal (DIM1).

  Then, the dimming signal control signal (S10) becomes HIGH after a certain period and shifts to the normal mode.

  When the output of the timer (513) changes from LOW to HIGH, the output Q of the flip-flop (515) is latched to HIGH at the rising edge of the clock (CLOCK), resets the flip-flop (512), and resets the timer (513). To do.

<Another Specific Example of Control Signal Generation Circuit 510>
The circuit shown in FIG. 12B is another example of a specific circuit of the control signal generation circuit 510 in the power supply circuit shown in FIG.

  According to the control signal generation circuit (510) of FIG. 12 (b), when the reset terminal (R) of the flip-flop (516) is HIGH, the dimming signal control signal (S10) becomes LOW and enters the forced boost mode. . When the dimming signal control signal (S10) is HIGH, the normal mode is set.

  When the input voltage (VIN) decreases, the third signal (S3) becomes HIGH, the flip-flop (516) is reset, and the mode proceeds to the forced boost mode. Further, when the input (VIN) decreases and the first dimming signal (DIM1) becomes HIGH, the first signal (S1) or the second signal (S2) becomes HIGH, and the flip-flop (516) is turned on. Reset to forced boost mode.

  Since the first signal (S1) and the second signal (S2) are LOW when the current flowing through the load (LED) is a set value, the output voltage (VOUT) is increased as much as possible by driving the set current. For example, when the first dimming signal (DIM1) is HIGH, the dimming signal control signal (S10) is latched HIGH at the rising edge of the clock (CLOCK), and shifts to the normal mode.

  In the comparator (519), a signal obtained by dividing the voltage of the terminal (N2) by the resistance divider circuit is input to the non-inverting input terminal, and the seventh reference voltage (VREF7) is input to the inverting input terminal.

  When the output voltage (VOUT) is boosted in the forced boost mode, the comparator (519) increases the divided signal, and the comparator (519) outputs when the voltage becomes equal to or higher than the seventh reference voltage (VREF7). Becomes HIGH.

  The output of the comparator (519) is input to the set terminal (S) of the flip-flop (516). When the output of the comparator (519) is HIGH, the dimming signal control signal (S10) is HIGH, Enter mode.

<Specific Example of Dimming Signal Generation Circuit 520>
The circuit shown in FIG. 13 is an example of a specific circuit of the dimming signal generation circuit (520) in the power supply circuit shown in FIG.

  According to the dimming signal generation circuit (520), if the dimming signal control signal (S10) is HIGH, the second dimming signal (DIM2) is during the period in which the first dimming signal (DIM1) is HIGH. HIGH is output to LOW during the period when the first dimming signal (DIM1) is LOW. That is, the first dimming signal (DIM1) is equal to the second dimming signal (DIM2).

  When the dimming signal control signal (S10) is LOW, the second dimming signal (DIM2) is HIGH regardless of the first dimming signal (DIM1), and the duty ratio of the dimming signal is set to 100. %. That is, when the dimming signal control signal (S10) is LOW, the drive signal (PWM) is applied to the power MOS-FET (M1) of the boost converter unit (30) until the output voltage (VOUT) reaches a desired value. ) Is output.

  As a result, even if the output voltage (VOUT) due to the sudden drop in the input voltage (VIN) also suddenly drops, the output voltage (VOUT) is immediately returned to the original state to determine the load (LED). In order to solve the problem of the prior art, since the power supply circuit that performs PWM dimming control operates in such a way that it can be driven by current, the current flowing to the load (LED) decreases but it takes time to recover to a steady operation state. It becomes possible.

DESCRIPTION OF SYMBOLS 10 Constant current part 20 Control part 30 Boost converter part 200 1st signal generation part 300 2nd signal generation part 400 3rd signal generation part 100 Drive circuit 500 Dimming signal control circuit 510 Control signal generation circuit 520 Dimming signal Generation Circuit DIM1 First Dimming Signal DIM2 Second Dimming Signal LED Load M1, M2 Power MOS-FET
PWM drive signal S1 First signal based on current flowing through load S2 Second signal based on output voltage S3 Third signal based on input voltage VIN Input voltage VOUT Output voltage

Claims (6)

A converter unit for converting an input voltage to output an output voltage for driving a load, and a dimming signal for intermittent operation of the converter unit are input to output a drive signal to the converter unit A power supply circuit including a control unit that performs pressure operation,
The control unit outputs the drive signal to the converter unit even when the dimming signal is not input when the control unit detects that the input voltage has decreased below a predetermined value. . The power supply circuit according to claim 1,
The control unit outputs the drive signal to the converter unit for a certain period when the control unit detects that the input voltage has decreased below the predetermined value. The power supply circuit according to claim 2,
The power supply circuit according to claim 1, wherein the predetermined period is equal to or longer than a time required for the output voltage to return to a voltage capable of driving the load. A converter unit for converting an input voltage to output an output voltage for driving a load, and a dimming signal for intermittent operation of the converter unit are input to output a drive signal to the converter unit A method for controlling a power supply circuit including a control unit that performs pressure operation,
A first step of detecting that the input voltage has dropped below a predetermined value;
A second step of outputting the drive signal to the converter unit even when the dimming signal is not inputted when it is detected in the first step that the input voltage has dropped below the predetermined value;
A method for controlling a power supply circuit, comprising: In the control method of the power supply circuit according to claim 4,
In the second step, when it is detected in the first step that the input voltage has dropped below the predetermined value, the drive signal is output to the converter unit for a certain period. Control method. In the control method of the power supply circuit according to claim 5,
The method of controlling a power supply circuit, wherein the predetermined period is equal to or longer than a time required for the output voltage to return to a voltage sufficient to drive the load.

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