JP2011024345A - Switching regulator and electronic apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching regulator capable of properly responding to a sharp load variation without requiring a coil inductor value determined to be needlessly small by design and to provide an electric apparatus using the switching regulator. <P>SOLUTION: The switching regulator includes a PWM signal generating circuit 10 which generates a PWM signal G1 so that a first feedback voltage Vfb1 corresponding to an output voltage VOUT matches a first reference voltage Vref1, a PFM signal generating circuit 20 which generates a PFM signal G2 so that the first feedback voltage Vfb1 matches a second reference voltage Vref2, a load variation detecting circuit 30 which detects a load variation, and a pre-driver circuit 50 which when the load variation is not detected, arbitrarily selects and outputs either of the PWM signal G1 and the PFM signal G2 as a control signal G0 for controlling an output transistor M1, and when the load variation is detected, forcibly selects and outputs the PFM signal G2 as the control signal G0 for controlling the output transistor M1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a switching regulator that generates a desired output voltage from an input voltage by switching driving an output transistor and supplies the output voltage to a load, and an electronic device using the switching regulator.

  FIG. 5 is a diagram illustrating a first conventional example of a switching regulator. The switching regulator 100 includes an output transistor 101, a coil 102, a diode 103, a capacitor 104, a resistor 105 and a resistor 106, a PWM [Pulse Width Modulation] signal generation circuit 107, and a pre-driver circuit 108. It consists of The PWM signal generation circuit 107 generates the PWM signal G1 so that the feedback voltage Vfb corresponding to the output voltage VOUT matches a predetermined reference voltage. The pre-driver 108 generates a control signal G0 for the output transistor 101 according to the PWM signal G1, and drives the output transistor 101 for switching. As described above, the switching regulator 100 boosts the input voltage VIN to generate a desired output voltage VOUT by driving the output transistor 101 to be switched.

  FIG. 6 is a diagram illustrating a second conventional example of a switching regulator. The switching regulator 200 includes an output transistor 201, a coil 202, a diode 203, a capacitor 204, a resistor 205 and a resistor 206, a PWM signal generation circuit 207a, a PFM [Pulse Frequency Modulation] signal generation circuit 207b, and a pre-driver. The circuit 208 and the switching control unit 209 are provided. The PWM signal generation circuit 207a generates the PWM signal G1 so that the feedback voltage Vfb corresponding to the output voltage VOUT matches the first reference voltage. The PFM signal generation circuit 207b generates the PFM signal G2 so that the feedback voltage Vfb matches the second reference voltage. The pre-driver 208 generates the gate signal G0 of the output transistor 201 according to any one of the PWM signal G1 and the PFM signal G2, and performs switching driving of the output transistor 201. The switching control unit 209 generates the switching signal SW so as to drive only one of the PWM signal generation circuit 207a and the PFM signal generation circuit 207b. Thus, the switching regulator 200 boosts the input voltage VIN to generate a desired output voltage VOUT by driving the output transistor 201 to be switched.

  As an example of the related art related to the above, Patent Document 1 disclosed and proposed by the applicant of the present application can be cited.

JP 2009-55751 A

  In the PWM switching regulator 100 illustrated in FIG. 5, the output voltage VOUT also varies (decreases) due to the variation (increase) in the output current IOUT flowing through the load. This occurs when the response speed of the feedback loop is slow with respect to the changing speed of the output current IOUT. Since the switching regulator 100 requires the coil 102 and the capacitor 104 in the feedback loop, the output voltage VOUT cannot be fed back in a time shorter than the time constant of the LC circuit composed of the coil 102 and the capacitor 104. That is, within a time shorter than the above time constant, it is not possible to generate a PWM signal having a pulse width large enough to suppress fluctuation (decrease) in the output voltage VOUT. Therefore, the conventional switching regulator 100 has a problem that the fluctuation (decrease) in the output voltage VOUT cannot be suppressed to a small value with respect to the sudden fluctuation (increase) in the output current IOUT. In particular, in the current discontinuous mode, the response speed of the feedback loop is much slower than in the current continuous mode, and thus the above-described problem is likely to be manifested.

  If the inductor value of the coil 102 is designed to be small, the response speed of the feedback loop can be increased, so that it is possible to cope with a sudden change in the output current IOUT. However, such a solution causes various adverse effects such as a decrease in conversion efficiency, an increase in the ripple of the output voltage VOUT and the output current IOUT, and noise generation due to an increase in the ripple of the output current IOUT. It was not a solution.

  Further, the PWM switching regulator 100 has a problem that efficiency at a light load is low. As a solution, there is a switching regulator that performs switching drive of the output transistor by the PWM method at a heavy load and performs switching drive of the output transistor by the PFM method at a light load. In particular, in the switching regulator 200 illustrated in FIG. 6, the PWM signal generation circuit 207a and the PFM signal generation circuit 207b are separately formed, so that the consumption of the signal generation circuit itself is reduced as compared with a configuration in which these are integrally formed. It is possible to suppress the current consumption at light load without unnecessarily increasing the current.

  However, if the PWM signal generation circuit 207a and the PFM signal generation circuit 207b are separately formed, the feedback loop becomes stable after the power supply to the PWM signal generation circuit 207a is started when switching from the PFM method to the PWM method. In the meantime, there is a problem that the output voltage VOUT decreases because no pulse is generated in the PWM signal G1.

  In order to solve the above problem, when switching from the PFM method to the PWM method, the PWM method is started after the power supply to the PWM signal generation circuit 207a is started until the feedback loop becomes stable. A configuration in which the switching drive of the output transistor M1 by the PFM method is continued without switching to is conceivable. In order to realize such a configuration, a circuit for determining whether or not the feedback loop of the PWM signal generation circuit 207a has become stable is necessary. Conventionally, as shown in FIG. 7, the PWM signal G1 and the PFM signal G2 are smoothed by the low-pass filters 209a and 209b, respectively, and the respective smoothed signals are compared by the comparator 209c, thereby generating the stability detection signal STBL. It was. However, in such a configuration, two high-order low-pass filters 209a and 209b are required, so an increase in circuit scale cannot be avoided.

  Further, in order to solve the above problem, as shown in FIG. 8, the output target value at the time of PFM driving is set lower than the output target value at the time of PWM driving, and switching from the PFM method to the PWM method is performed. At this time, a configuration in which the feedback loop of the PWM signal generation circuit 207a is stabilized during a predetermined soft start period by gradually increasing the output target value during PWM driving from the output target value during PFM driving.

  However, as shown in FIG. 6, in the configuration in which the feedback voltage Vfb of one system is compared with the reference voltages of the PWM signal generation circuit 207a and the PFM signal generation circuit 207b, the resistances of the external resistors 205 and 206 are attached. By appropriately changing the ratio, the voltage level of the feedback voltage Vfb is adjusted, and consequently, the output target value during PWM driving and the output target value during PFM driving are adjusted. As described above, in the switching regulator 200 illustrated in FIG. 6, the output target value at the time of PWM driving and the output target value at the time of PFM driving are simultaneously changed according to the resistance ratio of the resistors 205 and 206. When the above conventional solution is adopted, there is a problem in that one of the output target value during PWM driving and the output target value during PFM driving is limited.

  For example, when the output target value at the time of PWM driving is lowered, a lower limit is set to the set value so that the output target value at the time of PFM driving is not lowered too much. Conversely, the output target value at the time of PFM driving is set. When raising the value, there is a problem that an upper limit is set for the set value so that the output target value during PWM driving does not rise too much.

  In addition, the conventional solution described above also has a problem that the output target value at the time of PWM driving and the final output target value at the time of PWM driving cannot be set to be the same.

  In view of the above problems, the present invention provides a switching regulator capable of appropriately responding to steep load fluctuations without designing the coil inductor value to be unnecessarily small, and an electronic device using the switching regulator. The purpose is to provide.

  In order to achieve the above object, a switching regulator according to the present invention generates a desired output voltage from an input voltage by switching driving an output transistor, and supplies the output voltage to a load. A first drive signal generating circuit that generates a first drive signal of a pulse width modulation system so that a first feedback voltage corresponding to the first reference voltage matches a predetermined first reference voltage; and the first feedback voltage and a predetermined first reference voltage A second drive signal generation circuit that generates a second drive signal of a pulse frequency modulation system so that the two reference voltages match; a load fluctuation detection circuit that detects a load fluctuation; and when the load fluctuation is not detected As the control signal for the output transistor, any one of the first drive signal and the second drive signal is arbitrarily selected and output while the load fluctuation is detected. As a control signal of the output transistor, and a pre-driver circuit for forcibly selects output the second driving signal; has a configuration comprising a (first configuration).

  In the switching regulator having the first configuration, the pre-driver circuit selects one of the first drive signal and the second drive signal and outputs this as a control signal for the output transistor. And a logic unit that receives the input of the driving method switching signal and controls the selector unit. The logic unit is instructed to select and output the first driving signal by the driving method switching signal. In the meantime, when the load fluctuation is detected, the selector unit is controlled so as to selectively output the second drive signal only for a predetermined help period without depending on the drive method switching signal (second output). Configuration).

  In the switching regulator having the second configuration, the logic unit temporarily resets the first drive signal generation circuit at the start of the help period, and the first reference voltage is applied to the first reference voltage only during a predetermined boost period. A configuration (third configuration) that is set higher than the second reference voltage may be used.

  In the switching regulator having any one of the first to third configurations, the load fluctuation detection circuit includes the output voltage, the first reference voltage, an output current flowing through the load, a switching current flowing through the output transistor, A configuration (fourth configuration) may be adopted in which at least one of a coil current flowing in a coil connected to the output transistor or a voltage across the output transistor is monitored to detect the load variation.

  In the switching regulator having the fourth configuration, the load variation detection circuit compares the first reference voltage with a predetermined first threshold voltage to detect the load variation (fifth configuration). It is good to.

  The switching regulator having any one of the second to fifth configurations has a pulse width and a pulse frequency only while the output voltage or the second feedback voltage corresponding to the output voltage is lower than a predetermined second threshold voltage. Both have a third drive signal generation circuit that generates a fixed third drive signal, and the logic unit does not depend on the drive method switching signal when the third drive signal is generated, A configuration (sixth configuration) may be employed in which the selector unit is controlled to selectively output the third drive signal.

  Further, the switching regulator having any one of the second to sixth configurations provides power to the first drive signal generation circuit only while the selection output of the first drive signal is instructed by the drive method switching signal. The logic unit includes an internal power supply circuit that supplies power, and when the selection output of the first drive signal is instructed by the drive method switching signal, the logic unit is in a predetermined transition period from the start of the internal power supply circuit. A configuration (seventh configuration) may be employed in which the selector unit is controlled to perform the selective output of the first drive signal after performing the selective output of the second drive signal.

  Further, in the switching regulator having the seventh configuration, the logic unit sets the first reference voltage higher than the second reference voltage for a predetermined boost period from the startup of the internal power supply circuit ( An eighth configuration is preferable.

  In the switching regulator having any one of the second to eighth configurations, the pre-driver circuit starts counting pulses of the first drive signal when the load fluctuation is detected or when the internal power supply circuit is activated. The logic unit may include a counter unit, and the logic unit may be configured to determine whether the help period, the boost period, or the transition period has elapsed based on the count value of the counter unit (ninth configuration). .

  An electronic apparatus according to the present invention includes a switching regulator having any one of the first to ninth configurations, a battery that supplies the input voltage to the switching regulator, and the output voltage generated by the switching regulator. And a load to be supplied (a tenth configuration).

  With the switching regulator according to the present invention and an electronic device using the same, it is possible to appropriately respond to steep load fluctuations without designing the inductor value of the coil to be unnecessarily small.

The figure which shows one Embodiment of the switching regulator which concerns on this invention Timing chart for explaining drive system switching operation Timing chart for explaining output decrease suppression operation Timing chart for explaining output lower limit maintaining operation The figure which shows the 1st prior art example of a switching regulator The figure which shows the 2nd prior art example of a switching regulator The figure which shows one prior art example of the stable state determination part Timing chart showing a conventional example of drive system switching operation

  Hereinafter, a detailed description will be given by taking as an example a case where the present invention is applied to a switching regulator mounted on a portable electronic device (such as a mobile phone terminal or a digital still camera) that uses a battery as a power source.

  FIG. 1 is a diagram showing an embodiment of a switching regulator according to the present invention. The switching regulator of this embodiment includes a semiconductor device 1 and a plurality of discrete elements (N-channel MOS [Metal Oxide Semiconductor] field effect transistor M1, a coil L1, a Zener diode D1, capacitors C1 to C3, externally connected to the semiconductor device 1). And a resistor R1 and a resistor R2).

  Although not explicitly shown in FIG. 1, an electronic device according to the present invention receives a battery (such as a lithium ion battery) that supplies an input voltage VIN to a switching regulator and an output voltage VOUT generated by the switching regulator. And a load (such as a microcomputer and a lens driving unit).

  First, external connection of the semiconductor device 1 will be described. The application end of the input voltage VIN is connected to one end of the coil L1, one end of the capacitor C1, and the external terminal P2 (VIN terminal) of the semiconductor device 1. The other end of the capacitor C1 is grounded. The other end of the coil L1 is connected to the drain of the transistor M1 and the anode of the diode D1. The source and back gate of the transistor M1 are connected to the ground terminal and the external terminal P4 (PGND terminal) of the semiconductor device 1, respectively. The gate of the transistor M1 is connected to the external terminal P3 (OUT terminal) of the semiconductor device 1. The cathode of the diode D1 is connected to a load (not shown), one end of the capacitor C2, and the external terminal P1 (PREV terminal) of the semiconductor device 1. The other end of the capacitor C2 is grounded. One end of the resistor R1 is connected to the output end of the output voltage VOUT (one end of the capacitor C2). The other end of the resistor R1 is connected to one end of the resistor R2 and the external terminal P5 (FB terminal) of the semiconductor device 1. The other end of the resistor R2 is grounded. The capacitor C3 is connected between both ends of the resistor R1. An external terminal P6 (PWM / PFM terminal) of the semiconductor device 1 is connected to an output circuit (such as a microcomputer) of a driving method switching signal Sa.

  The drive system switching signal Sa is a pulse signal that is set to high level when instructing the selection output of the PWM signal G1, and is set to low level when instructing the selection output of the PFM signal G2. This operation mode switching signal (such as a standby mode transition instruction signal) can be used.

  Next, the internal configuration of the semiconductor device 1 will be described. The semiconductor device 1 is a so-called switching regulator IC, and includes a PWM signal generation circuit 10, a PFM signal generation circuit 20, a load variation detection circuit 30, an LV signal generation circuit 40, a predriver circuit 50, and an internal power supply circuit 60. And an UVLO [Under Voltage Locked-Out] circuit 70 are integrated.

  The PWM signal generation circuit 10 uses a pulse width modulation type first drive signal G1 (hereinafter referred to as a PWM signal G1) so that the first feedback voltage Vfb1 corresponding to the output voltage VOUT matches the predetermined first reference voltage Vref1. An error amplifier 11, a DC voltage source 12, a resistor 13, a capacitor 14, a comparator 15, a triangular wave generator 16, and a logical product calculator 17. And a maximum duty setting unit 18. The PWM signal generation circuit 10 is driven by receiving the internal power supply voltage VREF.

  The error amplifier 11 has a difference between the first feedback voltage Vfb1 input from the external terminal P5 to the inverting input terminal (−) and the first reference voltage Vref1 input from the DC voltage source 12 to the non-inverting input terminal (+). Is output as an error voltage Verr. That is, as the first feedback voltage Vfb1 is lower than the first reference voltage Vref1, the voltage level of the error voltage Verr becomes higher. As the first feedback voltage Vfb approaches the first reference voltage Vref1, the voltage level of the error voltage Verr becomes higher. Lower. If the first feedback voltage Vfb is higher than the first reference voltage Vref1, the voltage level of the error voltage Verr becomes a zero value (0V).

  The DC voltage source 12 generates the first reference voltage Vref1 and outputs it to the non-inverting input terminal (+) of the error amplifier 11. The DC voltage source 12 has a voltage level switching function of the first reference voltage Vref1, and this function will be described in detail later.

  The resistor 13 and the capacitor 14 are connected in series between the output terminal of the error amplifier 11 and the ground terminal to form a phase compensation circuit.

  The comparator 15 compares the error voltage Verr input from the error amplifier 11 to the non-inverting input terminal (+) and the triangular wave voltage Vslp input from the triangular wave generation unit 16 to the inverting input terminal (−), and the comparison result is obtained. Output as a comparison voltage Vcmp. That is, if the error voltage Verr is higher than the triangular wave voltage Vslp, the comparison voltage Vcmp is at a high level, and if the error voltage Verr is lower than the triangular wave voltage Vslp, the comparison voltage Vcmp is at a low level.

  The triangular wave generation unit 16 generates a triangular wave voltage Vslp having a predetermined frequency and outputs it to the inverting input terminal (−) of the comparator 15. The waveform of the triangular wave voltage Vslp may be a sawtooth waveform as well as a triangular wave shape.

  The AND operator 17 performs an AND operation between the comparison voltage Vcmp input from the comparator 15 to the first input terminal and the pulse voltage Vmax input from the maximum duty setting unit 18 to the second input terminal, and the calculation is performed. The result is output to the pre-driver circuit 50 as a PWM signal G1. That is, the PWM signal G1 is at a high level only when both the comparison voltage Vcmp and the pulse voltage Vmax are at a high level, and if either the comparison voltage Vcmp or the pulse voltage Vmax is at a low level, the PWM signal G1 is at a low level. Become a level. With such a configuration, even when the comparison voltage Vcmp is always maintained at a high level (that is, the duty is 100%), the duty of the PWM signal G1 is the maximum determined by the pulse width of the pulse voltage Vmax. It is limited to a duty (for example, 95%).

  The maximum duty setting unit 18 generates a pulse voltage Vmax for setting the maximum duty of the PWM signal G1 and outputs this to the second input terminal of the AND operator 17.

  The PFM signal generation circuit 20 generates a second drive signal G2 of a pulse frequency modulation method (hereinafter referred to as a PFM signal G2) so that the first feedback voltage Vfb1 matches a predetermined second reference voltage Vref2. The second drive signal generation circuit includes a comparator 21 and a DC voltage source 22. The PFM signal generation circuit 20 is driven by receiving the input voltage VIN or the output voltage VOUT.

  The comparator 21 compares the first feedback voltage Vfb1 input from the external terminal P5 to the inverting input terminal (−) and the second reference voltage Vref2 input from the DC voltage source 22 to the non-inverting input terminal (+). The comparison result is output to the pre-driver circuit 50 as the PFM signal G2. That is, if the first feedback voltage Vfb1 is higher than the second reference voltage Vref2, the PFM signal G2 is at a low level. Conversely, if the first feedback voltage Vfb1 is lower than the second reference voltage Vref2, the PFM signal G2 is high. Become a level.

  The DC voltage source 22 generates the second reference voltage Vref2 and outputs it to the non-inverting input terminal (+) of the comparator 21.

  The load fluctuation detection circuit 30 detects a load fluctuation by comparing the first reference voltage Vref1 and a predetermined first threshold voltage Vth1, and includes a comparator 31, a DC voltage source 32, an edge detection unit 33, It has. The load fluctuation detection circuit 30 is driven by receiving the input voltage VIN or the output voltage VOUT.

  The comparator 31 compares the first feedback voltage Vfb1 input from the external terminal P5 to the inverting input terminal (−) and the first threshold voltage Vth1 input from the DC voltage source 32 to the non-inverting input terminal (+). The comparison result is output to the edge detection unit 33. That is, if the first feedback voltage Vfb1 is higher than the first threshold voltage Vth1, the output signal of the comparator 31 is low level. Conversely, if the first feedback voltage Vfb1 is lower than the first threshold voltage Vth1, the comparator 31 The output signal becomes high level.

  The DC voltage source 32 generates the first reference voltage Vth1 and outputs it to the non-inverting input terminal (+) of the comparator 31.

  When the output signal of the comparator 31 rises to a high level, the edge detector 33 detects the rising edge and raises the PFM help signal Se from a low level to a high level. That is, the PFM help signal Se is raised to a high level when the first feedback voltage Vfb1 falls below the first threshold voltage Vth1. The PFM help signal Se is output to the pre-driver circuit 50.

  The LV signal generation circuit 40 has a third pulse width and pulse frequency that are fixed only while the output voltage VOUT (or the second feedback voltage Vfb2 corresponding thereto) is lower than the predetermined second threshold voltage Vth2. A third drive signal generation circuit that generates a drive signal G3 (hereinafter referred to as LV signal G3), and includes a comparator 41, a DC voltage source 42, and an LV pulse oscillator 43. The LV signal generation circuit 40 is driven by receiving the input voltage VIN.

  The comparator 41 compares the output voltage VOUT input from the external terminal P1 to the inverting input terminal (−) with the second threshold voltage Vth2 input from the DC voltage source 42 to the non-inverting input terminal (+), and The comparison result is output to the LV pulse oscillator 43 and the pre-driver circuit 50 as the output lower limit detection signal Sf. That is, if the output voltage VOUT is higher than the second threshold voltage Vth2, the output lower limit detection signal Sf is at a low level, and if the output voltage VOUT is lower than the second threshold voltage Vth2, the output lower limit detection signal Sf is at a high level. .

  The DC voltage source 42 generates the second reference voltage Vth2 and outputs it to the non-inverting input terminal (+) of the comparator 41.

  The LV pulse oscillator 43 has both the pulse width and the pulse frequency only while the output voltage VOUT is lower than the predetermined second threshold voltage Vth2, that is, while the output lower limit detection signal Sf is raised to the high level. A fixed LV signal G3 is generated and output to the pre-driver circuit 50. The LV signal G3 is used not only for the output lower limit maintaining operation (details will be described later) of the output voltage VOUT, but also for the initial output operation of the output voltage VOUT immediately after the input voltage VIN is input.

  When no load fluctuation is detected, the pre-driver circuit 50 arbitrarily outputs any one of the PWM signal G1 and the PFM drive signal G2 as the gate signal G0 of the output transistor M1, while the load fluctuation is detected. Sometimes, it has a function of forcibly selecting and outputting the PFM signal G2 as the gate signal G0 of the output transistor M1, and as a circuit component for realizing the function, a counter unit 51, a logic unit 52, a selector Part 53. The pre-driver circuit 50 is basically driven by receiving the input voltage VIN or the output voltage VOUT. However, the counter unit 51 included in the pre-driver circuit 50 is driven by receiving the internal power supply voltage VREF.

  The counter unit 51 starts the pulse count of the PWM signal G1 at the time of detecting the load fluctuation or at the completion of the startup of the internal power supply circuit 60. That is, the counter unit 51 starts the pulse count of the PWM signal G1 using the rising edges of the PFM help signal Se and the UVLO signal Sb as triggers. The counter unit 51 generates a PWM start signal Sc and a boost stop signal Sd based on the count value and outputs them to the logic unit 52.

  The logic unit 52 has a function of receiving the input of the driving method switching signal Sa from the external terminal P6 and controlling the selector unit 53.

  Further, the logic unit 52 detects the load fluctuation in the load fluctuation detection circuit 30 while the selection output of the PWM signal G1 is instructed by the driving method switching signal Sa, and the PFM help signal Se changes from the low level to the high level. When it is started, the function of controlling the selector unit 53 so as to selectively output the PFM signal G2 only for a predetermined help period T3 is provided regardless of the drive system switching signal Sa.

  The logic unit 52 has a function of temporarily resetting the PWM signal generation circuit 10 at the start of the above-described help period T3 and setting the first reference voltage Vref1 higher than the second reference voltage Vref2 only during a predetermined boost period T2. ing.

  The logic unit 52 is driven when the output voltage VOUT is detected to be lowered by the LV signal generation circuit 40, the output lower limit detection signal Sf is raised from the low level to the high level, and the LV signal G3 is generated. It has a function of controlling the selector unit 53 so as to selectively output the LV signal G3 regardless of the method switching signal Sa.

  Further, when the selection output of the PWM signal G1 is instructed by the drive method switching signal Sa, the logic unit 52 performs the selection output of the PFM signal G2 only for a predetermined transition period T1 from the time of starting the internal power supply circuit 60, and then A function of controlling the selector unit 53 so as to select and output the PWM signal G1 is provided.

  Further, the logic unit 52 has a function of setting the first reference voltage Vref1 higher than the second reference voltage Vref2 for a predetermined boost period T2 from the completion of startup of the internal power supply circuit 60.

  In addition, the logic unit 52 monitors the PWM start signal Sc and the boost stop signal Sd input from the counter unit 51, and based on the count value of the counter unit 51, the help period T3, the boost period T2, or In addition, a function for determining the progress of the transition period T1 is provided.

  In the above description, only the outline of the various functions of the logic unit 52 has been described. However, these functions will be described in more detail later with reference to the drawings.

  The selector unit 53 receives one of the PWM signal G1, the PFM signal G2, and the LV signal G3 based on the PWM selection signal Sx, the PFM selection signal Sy, and the LV selection signal Sz input from the logic unit 52. This is selected and output as the gate signal G0 of the output transistor M1. More specifically, the selector 53 selectively outputs the PWM signal G1 when the PWM selection signal Sx is at a high level and the remainder is at a low level. The selector unit 53 selectively outputs the PFM signal G2 when the PFM selection signal Sy is at a high level and the remainder is at a low level. The selector unit 53 selectively outputs the LV signal G3 when the LV selection signal Sz is at a high level and the remainder is at a low level.

  The internal power supply circuit 60 generates the internal power supply voltage VREF only while the selection output of the PWM signal G1 is instructed by the drive system switching signal Sa (high level period of the drive system switching signal Sa), and the PWM signal generation circuit 10 To supply power.

  The UVLO circuit 70 monitors the internal power supply voltage VREF, and raises the UVLO signal Sb from the low level to the high level when the voltage level exceeds a predetermined value. That is, if the UVLO signal Sb rises to a high level, it can be seen that the startup of the internal power supply circuit 60 has been completed and the PWM signal generation circuit 10 is in an operable state.

  Next, the basic operation (DC / DC conversion operation) of the switching regulator configured as described above will be described in detail.

  The transistor M1 is an output power transistor that is switched and driven in accordance with a gate signal G0 (switching drive signal) output from the external terminal P3 of the semiconductor device 1.

  When the transistor M1 is turned on, a switch current flows to the coil L1 toward the ground terminal via the transistor M1, and the electrical energy is stored. Note that if the charge has already been accumulated in the capacitor C2 during the ON period of the transistor M1, the current from the capacitor C2 flows through the load. At this time, since the anode potential of the diode D1 is lowered to almost the ground potential via the transistor M1, the diode D1 is in a reverse bias state, and no current flows from the capacitor C2 toward the transistor M1.

  On the other hand, when the transistor M1 is turned off, the electric energy stored therein is released by the counter electromotive voltage generated in the coil L1. At this time, since the diode D1 is in the forward bias state, the current flowing through the diode D1 flows into the load as the output current IOUT, and also flows into the ground terminal through the capacitor C2, thereby charging the capacitor C2. . By repeating the above operation, the load is supplied with the output voltage VOUT that has been boosted and smoothed by the capacitor C2.

  As described above, the switching regulator of the present embodiment drives the coil L1 that is an energy storage element by on / off control of the transistor M1, thereby boosting the input voltage VIN and generating a desired output voltage VOUT. Functions as a booster circuit.

  Next, the driving method switching operation of the switching regulator configured as described above will be described in detail with reference to FIG.

  FIG. 2 is a timing chart for explaining the driving method switching operation. In this figure, in order from the top, the driving method switching signal Sa, UVLO signal Sb, PWM start signal Sc, boost stop signal Sd, first reference voltage Vref1, second reference voltage Vref2, PWM signal G1, PFM signal G2, LV signal G3, output current IOUT, first feedback voltage Vfb1, PFM help signal Se, output voltage VOUT, output lower limit detection signal Sf, PWM selection signal Sx, PFM selection signal Sy, LV selection signal Sz, internal operation of semiconductor device 1 The state and the external instruction state of the semiconductor device 1 are shown.

  Until time t11, the drive system switching signal Sa is kept at the low level, and the selection output of the PFM signal G2 is instructed. The logic unit 52 sets the PFM selection signal Sy to the high level and sets the PWM selection signal Sx and the LV selection signal Sz to the low level based on the driving method switching signal Sa. In response to the fact that the PFM selection signal Sy is at the high level, the selector unit 53 outputs the PFM signal G2 as the gate signal G0 of the output transistor M1.

  Until time t11, the generation operation of the internal power supply voltage VREF by the internal power supply circuit 60 is stopped, and power is not supplied to the PWM signal generation circuit 10, so that a pulse is raised in the PWM signal G1. There is no. Thus, by stopping the operation of the PWM signal generation circuit 10, the power consumption of the semiconductor device 1 can be minimized.

  When the driving method switching signal Sa rises from the low level to the high level at time t11, the internal power supply circuit 60 is activated and the generation of the internal power supply voltage VREF is started.

  When the internal power supply voltage VREF exceeds a predetermined value at time t12, the UVLO signal Sb is raised from the low level to the high level. With this rising edge as a trigger, the counter unit 51 resets the count value and starts counting pulses of the PWM signal G1.

  At time t12, when the startup of the internal power supply circuit 60 is completed, the PWM signal generation circuit 10 starts generating the PWM signal G1, but until the feedback loop becomes stable (error voltage). Until Verr reaches the lowest potential of the triangular wave voltage Vslp from the initial potential (0 V), the PWM signal G1 is not pulsed. Therefore, if the PWM signal G1 is selectively output at the time t11 when the driving method switching signal Sa is raised to the high level or the time t12 when the UVLO signal Sb is raised to the high level, the output transistor M1 is switched. There is a possibility that the output voltage VOUT may be lowered from the target value because it cannot be driven (see the broken line in the figure).

  Therefore, when the selection output of the PWM signal G1 is instructed by the drive method switching signal Sa, the logic unit 52 is from the time when the internal power supply circuit 60 is started up (that is, from the time t12) until the predetermined transition period T1 elapses. Then, the selection output of the PFM signal G2 is continued, and at the time when the PWM start signal Sc input from the counter unit 51 is raised from the low level to the high level after the transition period T1 has elapsed (that is, at time t13). , A function of controlling the selector unit 53 so as to start the selection output of the PWM signal G1 is provided.

  That is, the logic unit 52 sets the PWM selection signal Sx to the high level and sets the PFM selection signal Sy and the LV selection signal Sz to the low level for the first time not at time t11 or time t12 but at time t13. In response to the fact that the PWM selection signal Sx is at the high level, the selector unit 53 outputs the PWM signal G1 as the gate signal G0 of the output transistor M1.

  With such a configuration, until the PWM signal generation circuit 10 can stably output the PWM signal G1, the selection output of the PFM signal G2 is continued, so that the output voltage VOUT is unintentionally reduced. Therefore, the transition from the PFM method to the PWM method can be performed smoothly.

  Further, the logic unit 52 supplies the first reference voltage Vref1 to the second reference voltage Vref2 (that is, feedback input at that time) until the boost period T2 elapses after the start-up of the internal power supply circuit 60 (that is, time t12). The boost stop signal Sd input from the counter unit 51 rises from the low level to the high level after the boost period T2 elapses. It has a function of returning the first reference voltage Vref1 to the normal value at the raised time point (that is, time t14).

  In this way, if the first reference voltage Vref1 is intentionally higher than the second reference voltage Vref2 so that the first feedback voltage Vfb1 is surely lower than the first reference voltage Vref1, the PFM method is used. When shifting from the PWM method to the PWM method, the first reference voltage Vref1 becomes equal to or lower than the first feedback voltage Vfb1, and the error voltage Verr of the error amplifier 11 is maintained at a zero value (0V). Since a situation in which a pulse does not rise in the PWM signal G1 can be avoided in advance, it is possible to more reliably perform the transition from the PFM method to the PWM method.

  In the switching regulator of this embodiment, the normal values of the first reference voltage Vref1 and the second reference voltage Vref2 are both set to the same value (for example, 0.4V). With this setting, it is possible to make the output target value during PFM driving coincide with the output target value during PWM driving.

  The boost value of the first reference voltage Vref1 is determined based on the first feedback at the time of switching the driving method after taking into account variations in the first reference voltage Vref1 and the second reference voltage Vref2 and the output rating of the output voltage VOUT. It is set to a minimum necessary voltage level (eg, 0.44 V) that is considered to be surely higher than the voltage Vfb1. Such a setting makes it possible to stably and reliably execute the transition from the PFM method to the PWM method.

  The logic unit 52 monitors the PWM start signal Sc and the boost stop signal Sd input from the counter unit 51, so that the transition period T1 and the boost period T2 have elapsed based on the count value of the counter unit 51. It has a function to make a decision. For example, in the counter unit 51 that is reset with the rising edge of the UVLO signal Sb as a trigger, when the number of pulses of the PWM signal G1 reaches a predetermined value A (for example, 8 pulses), the PWM activation signal Sc changes from low level to high level. When the number of pulses of the PWM signal G1 reaches a predetermined value B (for example, 128 pulses), the boost stop signal Sd is raised from the low level to the high level. Therefore, the logic unit 52 recognizes that the transition period T1 has elapsed with the rising edge of the PWM activation signal Sc as a trigger, and starts selecting and outputting the PWM signal G1. Also, the logic unit 52 recognizes that the boost period T2 has elapsed with the rising edge of the boost stop signal Sd as a trigger, and stops the boost operation of the first reference voltage Vref1.

  With such a configuration, it is possible to determine the progress of the transition period T1 or the boost period T2 using a very simple circuit.

  Further, with the above configuration, even if the time constant of the phase compensation circuit connected to the output terminal of the error amplifier 11 (that is, the rising speed of the error voltage Verr) can be arbitrarily adjusted, the PWM signal generation circuit Whether or not the 10 feedback loops are stable can be reliably determined on the basis of the number of pulses of the PWM signal G1 without depending on the fluctuation of the time constant.

  Also, with the above configuration, unlike the conventional configuration of FIG. 7, it is possible to determine whether the feedback loop of the PWM signal generation circuit 10 has become stable without requiring a high-order low-pass filter. This avoids an unnecessary increase in scale.

  Further, with the above configuration, unlike the conventional configuration of FIG. 8, the transition from the PFM method to the PWM method is smoothly performed while the output target value at the time of PFM driving and the output target value at the time of PWM driving are made to coincide with each other. It becomes possible.

  Note that after the boost operation of the first reference voltage Vref1 is stopped at time t14, the PWM signal generation circuit 10 causes the PWM signal G1 to match the first feedback voltage Vfb1 and the first reference voltage Vref1 (normal value). Is generated. Therefore, the output target value during PWM driving matches the output target value during PFM driving.

  Thereafter, when the driving method switching signal Sa falls from the high level to the low level at time t15, the logic unit 52 sets the PFM selection signal Sy to the high level, and sets the PWM selection signal Sx and the LV selection signal Sz to the low level. To do. In response to the fact that the PFM selection signal Sy is at the high level, the selector unit 53 outputs the PFM signal G2 as the gate signal G0 of the output transistor M1. As described above, the transition from the PWM method to the PFM method is promptly performed at the time when the drive method switching signal Sa falls from the high level to the low level at time t15.

  At time t15, when the driving method switching signal Sa falls to the low level, the internal power supply circuit 60 stops generating the internal power supply voltage VREF, and power supply to the PWM signal generation circuit 10 is stopped. Blocked. Thereby, the generation of the PWM signal G1 is stopped, and the first reference voltage Vref1 becomes a zero value (0V). As the generation of the internal power supply voltage VREF is stopped, the count value of the counter unit 51 is also cleared, so that the PWM start signal Sc and the boost stop signal Sd are lowered to a low level.

  Next, the output reduction suppressing operation of the switching regulator having the above configuration will be described in detail with reference to FIG.

  FIG. 3 is a timing chart for explaining the output decrease suppressing operation. The signals and voltages shown in this figure and the arrangement order thereof are the same as those in FIG.

  Until time t21, the drive system switching signal Sa is at the high level, and the selection output of the PWM signal G1 is instructed. The logic unit 52 sets the PWM selection signal Sx to a high level and the PFM selection signal Sy and the LV selection signal Sz to a low level based on the driving method switching signal Sa. In response to the fact that the PWM selection signal Sx is at the high level, the selector unit 53 outputs the PWM signal G1 as the gate signal G0 of the output transistor M1. In addition, since the operation state before time t21 corresponds to the operation state indicated by time t14 to time t15 in FIG. 2, redundant description is omitted.

  When the output current IOUT flowing through the load sharply increases at time t21, if the response speed of the feedback loop via the PWM signal generation circuit 10 is slow, the decrease in the output voltage VOUT cannot be suppressed as shown in FIG. Things happen.

  Thereafter, when the output voltage VOUT further decreases and the first feedback voltage Vfb1 falls below the predetermined first threshold voltage Vth1 at time t22, the load fluctuation detection circuit 30 changes the PFM help signal Se from the low level to the high level. To launch. With this rising edge as a trigger, the counter unit 51 resets the count value and starts counting pulses of the PWM signal G1.

  In this way, while the selection output of the PWM signal G1 is instructed by the drive system switching signal Sa, the load fluctuation is detected by the load fluctuation detection circuit 30, and the PFM help signal Se rises from the low level to the high level. In this case, the logic unit 52 selectively outputs the PFM signal G2 from the time when the load fluctuation is detected (that is, time t22) until the predetermined help period T3 elapses without depending on the driving method switching signal Sa. After the help period T3 has elapsed and the PWM start signal Sc input from the counter unit 51 is raised from the high level to the low level (that is, at time t23), A function of controlling the selector unit 53 so as to resume the selective output of the signal G1 is provided.

  That is, at time t22, the logic unit 52 sets the PFM selection signal Sy to the high level and sets the PWM selection signal Sx and the LV selection signal Sz to the low level regardless of the drive method switching signal Sa. In response to the fact that the PFM selection signal Sy is at the high level, the selector unit 53 outputs the PFM signal G2 as the gate signal G0 of the output transistor M1.

  By adopting such a configuration, even when a sudden load fluctuation occurs during the selective output of the PWM signal G1, the switching drive of the output transistor M1 is performed using the PFM signal G2 having a faster feedback loop response speed. As a result, the decrease in the output voltage VOUT can be suppressed and the output voltage VOUT can be maintained at its output target value as compared with the case where the selection output of the PWM signal G1 is continued (see the broken line in the figure). Is possible. Therefore, with the switching regulator of this embodiment, it is possible to appropriately respond to steep load fluctuations without designing the inductor value of the coil L1 to be unnecessarily small.

  Note that when the transition from the PWM method to the PFM method is performed at time t22, the PWM signal generation circuit 10 determines that the initial state (the error voltage Verr is set to the initial potential (0V)) based on an instruction from the logic unit 52. (Returned state) is reset. For this reason, the PWM signal G1 is not pulsed until the feedback loop of the PWM signal generation circuit 10 becomes stable.

  Therefore, the logic unit 52 temporarily resets the PWM signal generation circuit 10 at the start of the above-described help period T3 (that is, at time t22) and sets the first reference voltage Vref1 to the first time until the predetermined boost period T2 elapses. 2 is set higher than the reference voltage Vref2, and then the boost stop signal Sd input from the counter unit 51 rises from the low level to the high level after the boost period T2 elapses (that is, at time t24). 1 has a function of returning the reference voltage Vref1 to a normal value. Note that the normal value and boost value of the first reference voltage Vref1 are the same as those described above, and thus a duplicate description is omitted.

  In this way, if the first reference voltage Vref1 is intentionally higher than the second reference voltage Vref2 so that the first feedback voltage Vfb1 is surely lower than the first reference voltage Vref1, the PFM method is used. When shifting from the PWM method to the PWM method, the first reference voltage Vref1 becomes equal to or lower than the first feedback voltage Vfb1, and the error voltage Verr of the error amplifier 11 is maintained at a zero value (0V). Since a situation in which a pulse does not rise in the PWM signal G1 can be avoided in advance, it is possible to more reliably perform the transition from the PFM method to the PWM method.

  However, when the help period T3 is longer than the feedback response time of the PWM signal generation circuit 10, there is no problem in operation even if the PWM signal generation circuit 10 is not reset.

  In addition, the logic unit 52 monitors the PWM start signal Sc and the boost stop signal Sd input from the counter unit 51, so that the help period T3 and the boost period T2 have elapsed based on the count value of the counter unit 51. It has a function to make a decision. For example, in the counter unit 51 reset by the rising edge of the PFM help signal Se, when the number of pulses of the PWM signal G1 reaches a predetermined value C (for example, 64 pulses), the PWM activation signal Sc changes from low level to high level. Further, when the number of pulses of the PWM signal G1 reaches a predetermined value B (for example, 128 pulses), the boost stop signal Sd is raised from the low level to the high level. Therefore, the logic unit 52 recognizes that the help period T3 has elapsed with the rising edge of the PWM activation signal Sc as a trigger, and starts selecting and outputting the PWM signal G1. Also, the logic unit 52 recognizes that the boost period T2 has elapsed with the rising edge of the boost stop signal Sd as a trigger, and stops the boost operation of the first reference voltage Vref1.

  With such a configuration, it is possible to perform the progress determination of the help period T3 and the boost period T2 using an extremely simple circuit.

  Note that after the boost operation of the first reference voltage Vref1 is stopped at time t24, the PWM signal generation circuit 10 causes the PWM signal G1 to match the first feedback voltage Vfb1 and the first reference voltage Vref1 (normal value). Is generated. Therefore, the output target value during PWM driving matches the output target value during PFM driving.

  Next, the output lower limit maintaining operation of the switching regulator configured as described above will be described in detail with reference to FIG.

  FIG. 4 is a timing chart for explaining the output lower limit maintaining operation. The signals and voltages shown in this figure and the arrangement order thereof are the same as those in FIGS.

  Until the time t31, the drive system switching signal Sa is at a high level, and the selection output of the PWM signal G1 is instructed. The logic unit 52 sets the PWM selection signal Sx to a high level and the PFM selection signal Sy and the LV selection signal Sz to a low level based on the driving method switching signal Sa. In response to the fact that the PWM selection signal Sx is at the high level, the selector unit 53 outputs the PWM signal G1 as the gate signal G0 of the output transistor M1. In addition, since the operation state before time t31 corresponds to the operation state indicated by time t14 to time t15 in FIG. 2, redundant description is omitted.

  When the output current IOUT flowing through the load sharply increases at time t31, if the response speed of the feedback loop through the PWM signal generation circuit 10 is slow, as shown in FIG. 4, the decrease in the output voltage VOUT cannot be suppressed. Things happen.

  Thereafter, the output voltage VOUT further decreases, and at time t32, when the first feedback voltage Vfb1 falls below the predetermined first threshold voltage Vth1, the load fluctuation detection circuit 30 changes the PFM help signal Se from the low level to the high level. To launch. With this rising edge as a trigger, the counter unit 51 resets the count value and starts counting pulses of the PWM signal G1. Thereafter, as described with reference to FIG. 3, the output transistor M1 is switching-driven using the PFM signal G2, and an attempt is made to suppress the decrease in the output voltage VOUT (maintain the output target value).

  However, even if the PFM help operation is started, if the output voltage VOUT further decreases and the output voltage VOUT falls below the second threshold voltage Vth2 at time t33, the LV signal generation circuit 40 outputs the output lower limit detection signal. Sf is raised from the low level to the high level, and generation of the LV signal G3 is started.

  At this time, the logic unit 52 controls the selector unit 53 so as to selectively output the LV signal G3 without depending on the drive method switching signal Sa. That is, at time t33, the logic unit 52 sets the LV selection signal Sz to the high level and the PWM selection signal Sx and the PFM selection signal Sy to the low level regardless of the drive method switching signal Sa. In response to the LV selection signal Sz being at the high level, the selector unit 53 outputs the LV signal G3 as the gate signal G0 of the output transistor M1.

  With such a configuration, when the decrease in the output voltage VOUT cannot be suppressed by the PFM help operation, the feedback control of the output voltage VOUT is interrupted, and the LV signal G3 in which both the pulse width and the pulse frequency are fixed. Since the switching driving of the output transistor M1 is forcibly performed with a constant on-duty, unlike the case where the PFM help operation is continued (see the broken line in the figure), the lower limit value of the output voltage VOUT (ie, The second threshold voltage Vth2) can be maintained. Therefore, in the switching regulator according to the present embodiment, the output lower limit maintaining operation of the output voltage VOUT is performed so as not to cause the power shortage of the semiconductor device 1 itself, so that the power supply to the load is continued in any case. Is possible.

  After the time t33, while the output lower limit maintaining operation is performed by the interrupt output operation of the LV signal G3, the feedback control of the output voltage VOUT is not performed at all, and whether or not the output voltage VOUT is lower than the second threshold voltage Vth2. Accordingly, the selection output of the LV signal G3 and the selection output of the PWM signal G1 are alternately repeated. As a result, as shown in FIG. 4, the output voltage VOUT largely fluctuates in the vicinity of the second reference voltage Vth2. However, in the interrupt output operation of the LV signal G3, the output voltage VOUT does not fall below the second threshold voltage Vth2. Therefore, the ripple component may be overlooked.

  Thereafter, when the output voltage VOUT recovers to a state where it always exceeds the second threshold voltage Vth2, the selection output of the LV signal G3 is completely stopped, and the PWM signal G1 is continuously selected and output. Note that after the boost operation of the first reference voltage Vref1 is stopped at time t35, the PWM signal generation circuit 10 causes the PWM signal G1 to match the first feedback voltage Vfb1 and the first reference voltage Vref1 (normal value). Is generated. Therefore, the output target value during PWM driving matches the output target value during PFM driving.

  In the above embodiment, the case where the present invention is applied to a switching regulator mounted on a portable electronic device (such as a mobile phone terminal or a digital still camera) using a battery as a power source has been described as an example. The application target of the present invention is not limited to this, and can be widely applied to switching regulators mounted on other electronic devices.

  In the above embodiment, the configuration in which the present invention is applied to the step-up switching regulator has been described as an example. However, the application target of the present invention is not limited to this, and the present invention is not limited to the step-down switching regulator. The present invention can also be applied to a type or a step-up / step-down type switching regulator.

  In the above embodiment, the configuration in which the present invention is applied to the asynchronous rectification type switching regulator using the diode D1 as the rectifying element has been described as an example. However, the application target of the present invention is limited to this. However, the present invention can also be applied to a synchronous rectification type switching regulator using a transistor as a rectifying element.

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the spirit of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  For example, in the above-described embodiment, the load fluctuation detection circuit 30 has been described by taking as an example a configuration in which the load fluctuation is detected by comparing the first reference voltage Vref1 and the predetermined first threshold voltage Vth1, The configuration of the invention is not limited to this. The output voltage VOUT, the output current IOUT flowing through the load, the switching current ISW flowing through the output transistor M1, the coil current IL flowing through the coil L1, or the source / drain of the output transistor M1 A configuration may be adopted in which load fluctuation is detected by monitoring at least one of the inter-voltage VM1.

  The present invention is a technique suitable for a DC / DC converter mounted on, for example, a portable electronic device (such as a mobile phone terminal or a digital still camera) that uses a battery as a power source.

1 Semiconductor device (switching regulator IC)
10 PWM signal generation circuit (first drive signal generation circuit)
11 Error amplifier 12 DC voltage source (Vref1)
13 Resistance (for phase compensation)
14 Capacitor (for phase compensation)
DESCRIPTION OF SYMBOLS 15 Comparator 16 Triangle wave generation part 17 AND operator 18 Maximum duty setting part 20 PFM signal generation circuit (2nd drive signal generation circuit)
21 Comparator 22 DC voltage source (Vref2)
30 Load Fluctuation Detection Circuit 31 Comparator 32 DC Voltage Source (Vth1)
33 edge detector 40 LV signal generation circuit (third drive signal generation circuit)
41 Comparator 42 DC voltage source (Vth2)
43 LV pulse oscillator 50 Pre-driver circuit 51 Counter unit 52 Logic unit 53 Selector unit 60 Internal power supply circuit 70 UVLO circuit M1 N-channel MOS field effect transistor (output transistor)
L1 Coil D1 Diode (Zener diode)
C1 to C3 Capacitors R1, R2 Resistor Sa Drive system switching signal (PWM / PFM)
Sb UVLO signal Sc PWM start signal Sd Boost stop signal Se PFM help signal Sf Output lower limit detection signal Sx PWM selection signal Sy PFM selection signal Sz LV selection signal G0 Gate signal (switching drive signal)
G1 PWM signal G2 PFM signal G3 LV signal

Claims (10)

A switching regulator that generates a desired output voltage from an input voltage by switching driving an output transistor and supplies the output voltage to a load.
A first drive signal generation circuit that generates a first drive signal of a pulse width modulation system so that a first feedback voltage corresponding to the output voltage matches a predetermined first reference voltage;
A second drive signal generation circuit for generating a second drive signal of a pulse frequency modulation method so that the first feedback voltage and a predetermined second reference voltage match;
A load fluctuation detection circuit for detecting the load fluctuation;
When the load fluctuation is not detected, any one of the first drive signal and the second drive signal is arbitrarily selected and output as a control signal of the output transistor, while when the load fluctuation is detected, A pre-driver circuit for forcibly selecting and outputting the second drive signal as a control signal for the output transistor;
A switching regulator comprising: The pre-driver circuit is
A selector unit that selects one of the first drive signal and the second drive signal and outputs the selected signal as a control signal for the output transistor;
A logic unit that receives the input of a driving method switching signal and controls the selector unit;
Comprising
When the load variation is detected while the selection output of the first driving signal is instructed by the driving method switching signal, the logic unit does not depend on the driving method switching signal but only for a predetermined help period. The switching regulator according to claim 1, wherein the selector unit is controlled to selectively output the second drive signal.   The logic unit temporarily resets the first drive signal generation circuit at the start of the help period, and sets the first reference voltage higher than the second reference voltage for a predetermined boost period. Item 3. A switching regulator according to Item 2.   The load fluctuation detection circuit includes the output voltage, the first reference voltage, an output current flowing through the load, a switching current flowing through the output transistor, a coil current flowing through a coil connected to the output transistor, or the output transistor The switching regulator according to any one of claims 1 to 3, wherein the load variation is detected by monitoring at least one of the voltages across the two terminals.   5. The switching regulator according to claim 4, wherein the load fluctuation detection circuit detects the load fluctuation by comparing the first reference voltage with a predetermined first threshold voltage. 6. A third drive signal generation circuit that generates a third drive signal in which both the pulse width and the pulse frequency are fixed only while the output voltage or the second feedback voltage corresponding thereto is below a predetermined second threshold voltage. Comprising
The logic unit controls the selector unit to selectively output the third drive signal regardless of the drive method switching signal when the third drive signal is generated. The switching regulator in any one of Claims 2-5. An internal power supply circuit that supplies power to the first drive signal generation circuit only while the selection output of the first drive signal is instructed by the drive method switching signal;
When the logic unit is instructed to select and output the first driving signal by the driving method switching signal, the logic unit performs the selecting and outputting of the second driving signal for a predetermined transition period from the start of the internal power supply circuit. The switching regulator according to claim 2, wherein the selector unit is controlled so as to perform selective output of the first drive signal.   The switching regulator according to claim 7, wherein the logic unit sets the first reference voltage higher than the second reference voltage for a predetermined boost period from when the internal power supply circuit is activated. The pre-driver circuit is
A counter unit that starts pulse counting of the first drive signal at the time of detecting the load fluctuation or starting up the internal power supply circuit;
The said logic part performs progress determination of the said help period, the said boost period, or the said transition period based on the count value of the said counter part. Switching regulator. A switching regulator according to any one of claims 1 to 9,
A battery for supplying the input voltage to the switching regulator;
A load that receives the output voltage generated by the switching regulator;
An electronic device characterized by comprising:

Images