WO2019008873A1

WO2019008873A1 - Power supply device and electronic control device

Info

Publication number: WO2019008873A1
Application number: PCT/JP2018/016526
Authority: WO
Inventors: 鳴劉; 山脇　大造; 純之荒田; 泰志杉山; 隆介佐原
Original assignee: 日立オートモティブシステムズ株式会社
Priority date: 2017-07-07
Filing date: 2018-04-24
Publication date: 2019-01-10
Also published as: JP6779182B2; US11050345B2; JP2019017186A; US20210126527A1

Abstract

The objective of the present invention is to provide a power supply device capable of achieving a reduction in ripple, and an electronic control device provided with the power supply device. To this end, a PWM controller 25 generates a PWM signal Spwm, and a PFM controller 26 generates a PFM signal Spfm having a phase that is independent from that of the PWM signal Spwm. A level fixing period generating circuit 27 sets a level fixing period having a start timing which is a selection timing determined by an edge of the PFM signal Spfm. A mode selecting circuit 28 selects the PWM signal Spwm instead of the PFM signal Spfm as a switching control signal Ssw at a selection timing, and controls a logic level to a fixed logic level during the level fixing period from the selection timing of the switching control signal Ssw.

Description

Power supply unit and electronic control unit

The present invention relates to a power supply device and an electronic control device, and, for example, to a power supply device mounted on a vehicle-mounted ECU (Electronic Control Unit).

Patent Document 1 shows a power supply circuit capable of quickly responding to load fluctuations. The power supply circuit changes the frequency of the PWM signal when a change in load is detected, and restores the frequency after a predetermined time has elapsed. At this time, the power supply circuit substantially changes the frequency after inserting a predetermined signal separately according to the change of the frequency.

JP, 2016-46893, A

In recent years, in the field of car electronics, many electronic control units (referred to as ECUs) have been put to practical use for power train control, body control, safe traveling control, and the like. The ECU is usually equipped with a microcontroller (abbreviated as a microcomputer) responsible for various controls and a power supply device for generating a power supply of the microcomputer. The power supply device is, for example, a switching regulator type DC / DC converter that converts a DC voltage input based on a battery power supply into a different DC voltage and outputs the DC voltage.

In microcomputers for ECUs, current consumption increases as the number of control targets increases, and switching of activation / deactivation (for example, sleep mode ON / OFF) of each control target The rate of change of current consumption is also increasing. Even when the change rate of the consumption current of the microcomputer (the sudden change rate of the load current when viewed from the power supply device) increases in this manner, the power supply device changes the power supply voltage of the microcomputer (i.e., the ripple of the output voltage It is necessary to keep it within the required range. Therefore, the power supply apparatus is required to improve the response speed to a sudden change in load current (referred to as a sudden change in load).

As a method of improving the response speed, there is considered a method of switching between PWM (Pulse Width Modulation) control and PFM (Pulse Frequency Modulation) control according to sudden load change. However, in this case, when the control is switched, an excessive on period or off period occurs in the switching element, which may cause an increase in ripple. This is different from the case of switching the frequency of one PWM signal as in Patent Document 1 when switching two signals (PWM signal and PFM signal) whose phases are controlled independently, when switching control. This is because the pulse width can not be sufficiently controlled.

The present invention has been made in view of the foregoing, and an object thereof is to provide a power supply capable of achieving a reduction in ripple, and an electronic control unit including the power supply.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

The outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

A power supply device according to one embodiment includes first and second controllers, a phase adjustment period setting circuit, a mode selection circuit, and a switching element. A first controller generates a first switching signal using a first control mode, and a second controller uses a second control mode to phase independent of the first switching signal. To generate a second switching signal. The phase adjustment period setting circuit sets a phase adjustment period whose start timing is a selection timing determined at the edge of the second switching signal. The mode selection circuit selects the first switching signal as the switching control signal instead of the second switching signal at the selection timing, and the logic level between the selection timing and the phase adjustment period in the switching control signal is fixed at the logic level Control. The switching element is controlled on / off based on a switching control signal from the mode selection circuit to control an output voltage.

Among the inventions disclosed in the present application, the effects obtained by the representative embodiments can be briefly described to realize the reduction of ripples.

It is the schematic which shows the structural example of the principal part of the electronic control unit by Embodiment 1 of this invention. It is the schematic which shows the structural example of the principal part of the power supply device by Embodiment 1 of this invention. It is a timing chart which shows the operation example at the time of load sudden change in the power supply device of FIG. It is a timing chart explaining the function of the level fixed period in FIG. It is a timing chart explaining the function of the level fixed period in FIG. (A) is a circuit diagram which shows the structural example of the fixed period production | generation circuit in FIG. 2, (b) is a timing chart which shows the operation example of (a). FIG. 3 is a circuit diagram showing a configuration example of a level fixed period generation circuit in FIG. 2; FIG. 3 is a circuit diagram showing a configuration example of a mode selection circuit in FIG. 2; It is the schematic which shows the structural example of the principal part of the power supply device by Embodiment 2 of this invention. It is the schematic which shows the structural example of the principal part of the power supply device by Embodiment 3 of this invention. It is a timing chart which shows the operation example at the time of load sudden change in the power supply device of FIG. It is the schematic which shows the structural example of the principal part of the power supply device examined as a comparative example of this invention. It is a timing chart which shows the operation example at the time of load sudden change in the power supply device of FIG.

In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but unless specifically stated otherwise, they are not mutually unrelated, one is the other Some or all of the variations, details, supplementary explanations, etc. are in a relation. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. Except for the specific number, it is not limited to the specific number, and may be more or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated or considered to be obviously essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In all the drawings for describing the embodiments, the same reference numeral is attached to the same member in principle, and the repetitive description thereof will be omitted.
Embodiment 1
<< Outline of electronic control device >>

FIG. 1 is a schematic view showing a configuration example of a main part of an electronic control unit according to a first embodiment of the present invention. The electronic control unit 1 shown in FIG. 1 is, for example, an on-vehicle ECU. The electronic control device 1 includes a DC / DC converter 10, a power supply device 11, an input interface 12, a microcontroller (microcomputer) MCU, and a driver 13, which are mounted on a wiring board. There is. The DC / DC converter 10 converts a battery voltage Vbat (e.g., 12 V) to a power supply voltage Vin (e.g., 5 V). The power supply device 11 receives an input voltage (power supply voltage) Vin based on the battery power supply Vbat, and generates a predetermined output voltage (power supply voltage) Vo. The output voltage Vo is, for example, 1 V or the like.

The microcomputer MCU operates using the output voltage Vo of the power supply device 11 as a power supply. The microcomputer MCU includes, for example, a plurality of MPU cores 15 [1] to 15 [n], a memory 16, an analog-to-digital converter (ADC) 17, and various peripheral circuits 18. The microcomputer MCU receives various sensor signals Sin from the outside of the apparatus through the input interface 12, generates various control signals Sout corresponding to the signals using program processing and the like, and transmits the control signals Sout to the outside of the apparatus through the driver 13. . Outside the apparatus, various actuators and the like that operate in response to the various control signals Sout are provided. The various sensor signals Sin are, for example, detection results of operating states of various actuators.

In recent years, while the advancement of vehicles has been advanced, reduction of the number of ECUs mounted on the vehicle, and the like are required. For this reason, the control target by one electronic control device 1 tends to increase, and the current consumption also tends to increase. In order to suppress such an increase in current consumption, the microcomputer MCU activates only necessary circuit blocks (for example, some MPU cores) in a necessary period, and sets unnecessary circuit blocks in the sleep mode. It may have a function. In this case, the rapid change rate of the load current (current consumption of the microcomputer MCU) viewed from the power supply device 11 increases. On the other hand, in order to operate the microcomputer MCU normally, it is necessary to keep the fluctuation (i.e., ripple) of the output voltage Vo within the required range. For this reason, the power supply device 11 is required to improve the response speed to sudden load change (and reduce the ripple).
<< Configuration and Operation of Power Supply Device (Comparative Example) >>

FIG. 12 is a schematic view showing a configuration example of main parts of a power supply device examined as a comparative example of the present invention. The power supply device shown in FIG. 12 includes a switching circuit SWU and a switching control circuit SWC ', and supplies the generated output voltage Vo to an external load LD (for example, the microcomputer MCU in FIG. 1). The switching control circuit SWC 'uses the output voltage Vo as a feedback input to generate a switching control signal Ssw for keeping the output voltage Vo constant.

The switching circuit SWU includes a driver 21, a high side switching element SWh and a low side switching element SW1, an inductor L1, and a smoothing output capacitor C1. Switching element SWh is coupled between input voltage Vin and the output node, and switching element SWl is coupled between the output node and ground power supply voltage GND. The driver 21 receives the switching control signal Ssw, and complementarily controls the on / off of the high side switching element SWh and the low side switching element SWl. Thus, the switching elements SWh and SWl control the output voltage Vo.

Specifically, in the high level period of the switching control signal Ssw, the switching element SWh is turned on and the switching element SWl is turned off. In this period, power from the input voltage Vin is accumulated in the inductor L1 and supplied to the load LD. On the other hand, in the low level period of the switching control signal Ssw, the switching element SWh is turned off and the switching element SWl is turned on. In this period, the power stored in the inductor L1 is supplied to the load LD. The output voltage Vo is controlled by the ratio (ie, the duty) of the high level period in one cycle (the sum of the high level period and the low level period) of the switching control signal Ssw. The smoothing output capacitor C1 has a function of suppressing the ripple of the output voltage Vo.

The switching control circuit SWC 'includes a PWM controller 25, a PFM controller 26, a mode selection circuit 28' and a mode switching control circuit MDC '. The PWM controller 25 uses the PWM control mode to generate a PWM signal (switching signal) Spwm whose frequency is constant and the pulse width changes according to the feedback input from the output voltage Vo. Although the PWM controller 25 is not shown, various circuit systems are known, and any circuit system may be used. Typically, a method of determining the duty of the PWM signal by directly generating a triangular wave (or sawtooth wave) and comparing the triangular wave (sawtooth wave) with an error signal based on the output voltage Vo; A system etc. which are generated using inductor current IL which flows into L1 are mentioned.

The PFM controller 26 generates a PFM signal (switching signal) Spfm whose frequency changes according to the feedback input from the output voltage Vo using the PFM control mode. Although the PFM controller 26 is not shown, various circuit systems are known, and any circuit system may be used. Typically, a method of setting two threshold voltages and determining a high level / low level period of the PFM signal Spfm so that the output voltage Vo falls within the range of the two threshold voltages, or one threshold voltage There is a method of setting and outputting a high pulse of a fixed pulse width when the output voltage Vo reaches the threshold voltage.

The mode switching control circuit MDC 'asserts the mode switching signal Smd when the output voltage Vo deviates from the predetermined voltage range, recovers the output voltage Vo, and negates the mode switching signal Smd after a predetermined period has elapsed. Specifically, the mode switching control circuit MDC 'includes a load abrupt change detection circuit 30 and a generation circuit 31' for a fixed period.

The load sudden change detection circuit 30 includes, for example, two comparator circuits that detect whether the output voltage Vo deviates from a predetermined voltage range. One comparator circuit asserts the sudden load change detection signal Sdet in a period in which the output voltage Vo is lower than the threshold voltage, using a threshold voltage (load abrupt threshold voltage) whose voltage level is lower than the output voltage Vo. . That is, the assertion of the sudden load change detection signal Sdet means detection of a sudden increase in load. The other comparator circuit asserts the sudden load change detection signal Sdet in a period in which the output voltage Vo is higher than the threshold voltage, using a threshold voltage (a rapid load reduction threshold voltage) whose voltage level is higher than the output voltage Vo. . That is, the assertion of the sudden load change detection signal Sdet means detection of a sudden drop in load.

The generation circuit 31 'asserts the mode switching signal Smd in response to the assertion of the sudden load change detection signal Sdet, and waits for a fixed period after the sudden load change detection signal Sdet is changed from the assertion to the negation. Negate. The predetermined period is a period required for the output voltage Vo to recover to a target value and to be in a stable state.

The mode selection circuit 28 'selects one of the PWM signal Spwm or the PFM signal Spfm as the switching control signal Ssw according to the mode switching signal Smd, and outputs it. Specifically, the mode selection circuit 28 'selects the PWM signal Spwm in the negate period of the mode switching signal (that is, when the load LD is steady), and in the assertion period of the mode switching signal Smd (that is, when the load LD suddenly changes). The PFM signal Spfm is selected.

Here, in the PWM control mode, since the switching frequency is fixed, it is necessary to set the switching frequency high in order to improve the response speed at the time of sudden load change. However, in this case, it is not easy to set the switching frequency high in practice because the switching loss of the power supply device is increased (i.e., the power consumption is increased). On the other hand, in the PFM control mode, the frequency fluctuates depending on the load current Io, so that it is possible to speed up the response speed when the load suddenly changes while suppressing the switching loss to some extent. However, in a vehicle-mounted power supply device, it is not easy to apply only the PFM control mode because the EMI (Electro Magnetic Interference) standard is strict. Therefore, as shown in FIG. 12, a mode switching method is useful in which the PWM control mode is used when the load is steady and the PFM control mode is used when the load suddenly changes.
<< Operation of power supply device (comparative example) >>

FIG. 13 is a timing chart showing an operation example of the power supply apparatus of FIG. 12 at the time of sudden load change. In period T1 in which load current Io is steady, mode switching signal Smd from mode switching control circuit MDC 'is at the negate level (here, low level), and mode selection circuit 28' uses PWM signal Spwm as switching control signal Ssw. It selects and outputs to the switching circuit SWU. The switching elements SWh and SWl of the switching circuit SWU are on / off controlled by a switching control signal Ssw (that is, the PWM signal Spwm), and generate an output voltage Vo from an input voltage Vin.

Thereafter, in a period T2 in which the load current Io sharply increases, the output voltage Vo decreases as the load sharply increases, and the load sudden change detection circuit 30 detects the sudden load change when the output voltage Vo decreases below the load sharp threshold voltage. The signal Sdet is changed to an asserted level (here, high level). In response to this, the generation circuit 31 'changes the mode switching signal Smd to an asserted level (here, high level) for a predetermined period. In response to the assertion of the mode switching signal Smd, the mode selection circuit 28 'selects the PFM signal Spfm as the switching control signal Ssw and outputs it to the switching circuit SWU.

The switching elements SWh and SWl of the switching circuit SWU are on / off controlled by the switching control signal Ssw (ie, the PFM signal Spfm) to stabilize the output voltage Vo. As a result, the decrease of the output voltage Vo is recovered. The sudden change in load detection circuit 30 changes the rapid change in load detection signal Sdet to a negate level (here, a low level) when the output voltage Vo exceeds the rapid load increase threshold. The constant period generation circuit 31 'extends the assert period of the sudden load change detection signal Sdet by the constant period Ts until the output voltage Vo recovers to the voltage level (that is, the target value) at steady load and becomes stable.

The mode switching signal Smd is changed to the negate level after a predetermined period Ts by the generation circuit 31 '. As a result, in the period T3, the mode selection circuit 28 ′ selects the PWM signal Spwm as the switching control signal Ssw and outputs it to the switching circuit SWU. The switching elements SWh and SWl of the switching circuit SWU are controlled by the PWM signal Spwm to generate an output voltage Vo from the input voltage Vin.
<< Problems of power supply (comparative example) >>

However, in the power supply device of FIG. 12, as shown in FIG. 13, when switching from the period T2 (PFM control mode) to the period T3 (PWM control mode), large ripple may occur in the output voltage Vo. Specifically, a worst condition may occur in which the timing of the switching, the falling edge of the PFM signal Spfm, and the rising edge of the PWM signal Spwm accidentally coincide. Under the worst condition, a maximum high pulse which is the sum of the high pulse width of the PFM signal Spfm and the high pulse width of the PWM signal Spwm occurs, and a large ripple occurs in the output voltage Vo.

For example, in the method of switching the frequency of one PWM signal as in Patent Document 1, such a worst condition does not occur, but two in which the phases are independently controlled as in FIGS. 12 and 13 In such a scheme that switches the signal (PWM signal Spwm and the PFM signal Spfm) of the above, the worst condition may occur depending on the phase relationship. The worst condition may occur not only in the case of FIG. 13 but also when the switching timing, the rising edge of the PFM signal Spfm, and the falling edge of the PWM signal Spwm accidentally coincide. In this case, the maximum low pulse will occur. Moreover, although the case of a load surge is taken as an example here, the same problem may occur in the case of a load drop.
<< Configuration of Power Supply Device (Embodiment 1) >>

FIG. 2 is a schematic diagram showing an example of configuration of a main part of the power supply device according to Embodiment 1 of the present invention. The power supply device shown in FIG. 2 includes a switching circuit SWU and a switching control circuit SWC1, and supplies the generated output voltage Vo to an external load LD (for example, the microcomputer MCU in FIG. 1). The configuration of switching circuit SWU is similar to that of FIG.

The switching control circuit SWC1 includes a PWM controller 25, a PFM controller 26, a mode selection circuit 28, a mode switching control circuit MDC, and a fixed level period generation circuit 27. The PWM controller 25, the PFM controller 26, and the sudden load change detection circuit 30 have the same configuration as in FIG. 12, and the mode selection circuit 28 and the mode switching control circuit MDC have a slightly different configuration from that in FIG. . The level fixed period generation circuit 27 is newly provided with respect to FIG.

As in the case of FIG. 12, the mode switching control circuit MDC asserts the mode switching signal Smd when the output voltage Vo deviates from the predetermined voltage range, recovers the output voltage Vo, and passes the predetermined period. The switching signal Smd is negated. However, unlike the case of FIG. 12, the mode switching control circuit MDC negates the mode switching signal Smd at the selection timing after a predetermined period has elapsed. The selection timing is determined at the edge of the PFM signal Spfm.

Specifically, the mode switching control circuit MDC includes a load sudden change detection circuit 30 and a generation circuit 31 for a fixed period. The sudden load change detection circuit 30 has the same configuration as that of FIG. Unlike the case of FIG. 12, the generation circuit 31 determines the timing (selection timing) when the mode switching signal Smd is negated to the edge of the PFM signal Spfm, unlike the case of FIG.

The level fixed period generation circuit (phase adjustment period setting circuit) 27 sets a level fixed period (phase adjustment period) whose start timing is the above-described selection timing. Specifically, the level fixed period generation circuit 27 generates the level fixed signal Slf which becomes one of the high level and the low level in the level fixed period and becomes the other of the high level and the low level in the period excluding the level fixed period.

As in the case of FIG. 12, the mode selection circuit 28 selects the PFM signal Spfm in the assert period of the mode switching signal Smd as the switching control signal Ssw, and selects the PWM signal Spwm in the negate period of the mode switching signal Smd. At this time, the mode selection circuit 28 selects the PWM signal Spwm instead of the PFM signal Spfm at the above-described selection timing based on the mode switching signal Smd. Then, unlike in the case of FIG. 12, mode selection circuit 28 forcibly sets the logic level between the selection timing in the switching control signal Ssw (that is, corresponding to the PWM signal Spwm) to the level fixed period based on the level fixed signal Slf. Control to a fixed logic level.
<< Operation of Power Supply Device (Embodiment 1) >>

FIG. 3 is a timing chart showing an operation example of the power supply device of FIG. 2 at the time of a sudden load change. In FIG. 3, the operation in the period T1 in which the load current Io is in steady state is the same as that in the case of FIG. In a period T2 in which the load current Io increases rapidly, the output voltage Vo decreases as the load increases rapidly, and the load sudden change detection circuit 30 detects the rapid load change detection signal Sdet when the output voltage Vo decreases below the load abrupt threshold voltage. Is changed to the assert level (here, high level). In response to this, the generation circuit 31 changes the mode switching signal Smd to an asserted level (here, high level) for a predetermined period. In response to the assertion of the mode switching signal Smd, the mode selection circuit 28 selects the PFM signal Spfm as the switching control signal Ssw and outputs it to the switching circuit SWU.

The switching elements SWh and SWl of the switching circuit SWU are on / off controlled by the switching control signal Ssw (ie, the PFM signal Spfm) to stabilize the output voltage Vo. As a result, the decrease of the output voltage Vo is recovered. The sudden change in load detection circuit 30 changes the rapid change in load detection signal Sdet to a negate level (here, a low level) when the output voltage Vo exceeds the rapid load increase threshold. The constant period generation circuit 31 extends the assert period of the sudden load change detection signal Sdet by the constant period Ts until the output voltage Vo recovers to the voltage level (that is, the target value) at the steady load time and becomes stable. After a predetermined period Ts, the generation circuit 31 changes the mode switching signal Smd to the negate level (here, low level) with the edge (falling edge in this example) of the PFM signal Spfm as the selection timing TMsl.

The mode selection circuit 28 selects the PWM signal Spwm as the switching control signal Ssw in response to the mode switching signal Smd, and outputs the selected signal to the switching circuit SWU. On the other hand, the level fixed period generation circuit 27 receives the negate of the mode switching signal Smd and sets the level fixed signal (in this example, a low pulse signal) having a pulse width of the level fixed period (phase adjustment period) Tfx with the selection timing TMsl as the start timing. ) Generate Slf. The mode selection circuit 28 forcibly controls the logic level of the selected switching control signal Ssw (that is, the PWM signal Spwm) to a fixed level (low level in this example) during this level fixed period Tfx. After the fixed level period Tfx, the switching control signal Ssw becomes equal to the PWM signal Spwm, and the steady operation in the PWM control mode is performed as in the case of FIG.

The minimum value of the fixed period Ts by the fixed period generation circuit 31 is determined by the time when the output voltage Vo recovers from the rapid increase threshold to the voltage level (target value) at the steady load condition on the assumption that the sudden change in load is largest. . The minimum value of the fixed period Ts is calculated, for example, by simulation or the like. The maximum value of the fixed period Ts is determined by the frequency of the sudden load change, and is determined by the minimum interval at which the sudden load change can occur, since it needs to be ended before the next sudden load change occurs. The minimum interval at which this sudden change in load may occur can be determined based on the specifications of the microcomputer. For example, when the microcomputer operates at 1 MHz (1 μs cycle), the maximum value of the fixed period Ts is 1 μs.
<< Details of fixed level period >>

FIG. 4 and FIG. 5 are timing charts explaining the function of the level fixed period in FIG. As described in FIG. 13, FIG. 4 shows the worst condition in which the selection timing TMsl, the falling edge of the PFM signal Spfm, and the rising edge of the PWM signal Spwm coincide, and a maximum high pulse occurs. In this case, the worst condition is relaxed by forcibly controlling the switching control signal Ssw to the low level during the level fixed period Tfx by the level fixed signal Slf. As a result, it is possible to suppress the increase of the inductor current IL accompanying the high pulse and to reduce the ripple of the output voltage Vo.

From the viewpoint of relaxing the worst condition, if the length of level fixed period Tfx is shorter than the pulse width Thf of a logic level (here, high level) different from the fixed logic level in PFM signal Spfm just before selection timing TMsl. Good. Alternatively, the length of the level fixed period Tfx may be shorter than the pulse width Thw of the logic level (high level) different from the fixed logic level in the PWM signal Spwm immediately after the selection timing TMsl.

However, desirably, the length of the level fixed period Tfx may be about 1/2 (for example, in the range of 1/3 to 2/3) of the high pulse width Thw of the PWM signal Spwm. This is because, as shown in case [2], if the length of the level fixing period Tfx is excessively short, the increase in the inductor current IL can not be sufficiently suppressed, and the ripple reduction effect is weakened. Also, as shown in case [3], when the length of level fixed period Tfx is excessively long, inductor current IL decreases excessively, and the output voltage Vo has a reverse polarity to that in the case [2]. It is because a big ripple may arise. Therefore, if the length of the level fixed period Tfx is set to about 1/2 of the high pulse width Thw, as shown in case [1], the increase of the inductor current IL can be appropriately suppressed, and the ripple reduction effect is enhanced. Becomes possible.

Unlike the case of FIG. 4, FIG. 5 shows the worst condition in which the selection timing TMsl, the rising edge of the PFM signal Spfm, and the falling edge of the PWM signal Spwm coincide, and a maximum low pulse occurs. In this case, the worst condition is alleviated by forcibly controlling the switching control signal Ssw to the high level during the level fixed period Tfx by the level fixed signal Slf. As a result, it is possible to suppress the reduction of the inductor current IL accompanying the low pulse, and to reduce the ripple of the output voltage Vo. Also in this case, as in the case of FIG. 4, the length of the level fixed period Tfx may be about 1/2 of the low pulse width Tlw of the PWM signal Spwm.

As described above, when the selection timing TMsl is predetermined at the falling edge of the PFM signal Spfm by the generation circuit 31 for a certain period, the fixed logic level accompanying the level fixed period Tfx becomes the low level as shown in FIG. On the other hand, when the selection timing TMsl is predetermined at the rising edge of the PFM signal Spfm by the generation circuit 31 for a fixed period, the fixed logic level accompanying the level fixed period Tfx becomes the high level as shown in FIG.
<< Details of Main Circuits>

6 (a) is a circuit diagram showing a configuration example of the constant period generation circuit in FIG. 2, and FIG. 6 (b) is a timing chart showing an operation example of FIG. 6 (a). The fixed period generation circuit 31 of FIG. 6A includes a falling edge detection circuit 311, a delay circuit 312,

SR latch circuits

313 and 315, and a D flip flop circuit 314. The falling edge detection circuit 311 outputs a high pulse signal Sx having a pulse width determined by an internal delay circuit when a falling edge of the sudden load change detection signal Sdet occurs.

The delay circuit 312 is formed of, for example, inverter circuits in a plurality of stages, and delays the high pulse signal Sx from the falling edge detection circuit 311 by a predetermined time Ts. The fixed time Ts is predetermined by simulation or the like as described in FIG. The SR latch circuit 313 drives the output signal Sy to the set level (high level) in response to the high pulse signal from the delay circuit 312.

The D flip-flop circuit 314 latches the output signal Sy of the SR latch circuit 313 at the falling edge of the PFM signal Spfm. As a result, the D flip flop circuit 314 outputs the high level output signal Sz at the first falling edge of the PFM signal Spfm after the output signal Sy becomes high level (in other words, after a predetermined period Ts has passed). Output.

The SR latch circuit 315 drives the mode switching signal Smd to the set level (high level) in response to the assertion of the sudden load change detection signal Sdet, and switches the mode in response to the high level output signal Sz from the D flip flop circuit 314. The signal Smd is driven to the reset level (low level). The SR latch circuit 313 drives the output signal Sy to the reset level (low level) in response to the reset level (low level) of the mode switching signal Smd. Thereafter, the D flip flop circuit 314 returns the output signal Sz to the low level in response to the falling edge of the PFM signal Spfm.

Of course, the generation circuit 31 is not limited to such a circuit, and can be realized by various circuits. Further, as shown in FIG. 3, the sudden load change detection circuit 30 of FIG. 2 negates the rapid load change detection signal Sdet when the output voltage Vo recovers to the load rapid increase threshold, but has recovered to the target value. In this case, the sudden load change detection signal Sdet may be negated. In this case, the generation circuit 31 generates a waiting time for stabilizing the output voltage Vo recovered to the target value for a predetermined period.

FIG. 7 is a circuit diagram showing a configuration example of the level fixed period generation circuit in FIG. The level fixed period generation circuit 27 shown in FIG. 7 includes a delay circuit 271 and a logic gate 272. The delay circuit 271 is formed of, for example, inverter circuits in a plurality of stages, and delays the mode switching signal Smd by the level fixed period Tfx. Logic gate 272 outputs the result of an OR operation of mode switching signal Smd and the inverted output signal of delay circuit 271 as level fixed signal Slf.

Here, the delay time of the delay circuit 271 (that is, the level fixed period Tfx) can be fixed in advance. That is, for example, as shown in FIG. 1, when the input voltage Vin of the power supply device 11 is not the battery voltage Vbat but the output voltage of the DC / DC converter 10, the value of the input voltage Vin is substantially constant. The power supply device 11 generates a constant output voltage Vo from a constant input voltage Vin. Therefore, the duty in the steady state can be predicted in advance with high accuracy. For example, the high pulse width Thw of the PWM signal Spwm shown in FIG. 4 can also be predicted with high accuracy.

FIG. 8 is a circuit diagram showing a configuration example of the mode selection circuit in FIG. The mode selection circuit 28 shown in FIG. 8 includes a selection circuit 281 and a logic gate 282. The selection circuit 281 selects the PWM signal Spwm when the mode switching signal Smd is at the negate level (low level), and selects the PFM signal Spfm when the mode switching signal Smd is at the assert level (high level). The logic gate 282 outputs an AND operation result of the output of the selection circuit 281 and the level fixed signal Slf as the switching control signal Ssw.

In FIGS. 6A, 7 and 8, although the case where the selection timing TMsl is determined to be the falling edge of the PFM signal Spfm is taken as an example, the same applies to the case where it is determined to be the rising edge. In this case, for example, D flip-flop circuit 314 in FIG. 6A is changed to a rising edge trigger configuration, the polarity of level fixing signal Slf in FIG. 7 is inverted, and logic gate 282 in FIG. Just do it.
<< Main effects of Embodiment 1 >>

As described above, by using the power supply device and the electronic control device according to the first embodiment, it is possible to alleviate the worst condition by switching two signals whose phases are controlled independently, and to realize the reduction of the ripple. As a result, for example, in the on-vehicle electronic control device, the control object can be expanded. Here, although the case of a sudden increase in load is taken as an example, the same applies to the case of a sudden decrease in load.
Second Embodiment
問題 Prerequisite problems》

In the first embodiment described above, as described with reference to FIG. 7, the level fixed period Tfx is set to a fixed value. However, for example, in FIG. 1, when the battery voltage Vbat is directly input to the power supply 11, when the use environment of the power supply 11 changes significantly, or when characteristic variations of each circuit occur, The high pulse width Thw of the PWM signal Spwm in FIG. 4 may not be predicted with high accuracy. If the ratio between the high pulse width Thw and the level fixed period Tfx can not be maintained properly, as shown in FIG. 4, the ripple reduction effect is weakened.
<< Configuration and Operation of Power Supply Device (Second Embodiment) >>

FIG. 9 is a schematic diagram showing an example of a configuration of a main part of a power supply device according to Embodiment 2 of the present invention. The power supply device shown in FIG. 9 is different from the power supply device shown in FIG. 2 in the configuration of the switching control circuit SWC2. The switching control circuit SWC2 is slightly different in configuration of the level fixed period generating circuit 35 from the switching control circuit SWC1 of FIG. 2, and additionally includes a duty detection circuit 36.

The duty detection circuit 36 detects the duty of the PFM signal Spfm or the PWM signal Spwm in the fixed period Ts of the mode switching control circuit MDC shown in FIG. 3, reflects the duty, and outputs the fixed level period (phase adjustment period) Tfx. Variable control of the length. At this time, desirably, the duty detection circuit 36 recognizes the length of a period of a logic level (high level in FIG. 3) different from the level fixed period Tfx in the PWM signal Spwm based on the detection result of the duty. Then, the duty detection circuit 36 sets the level fixed period Tfx so that the recognized length and the length of the level fixed period Tfx maintain a predetermined ratio (for example, 2: 1 as in the case [1] of FIG. 4). Control. In this case, for example, if the high pulse period of the PFM signal Spfm (and the high pulse period of the PWM signal Spwm) in the fixed period Ts in FIG. 3 becomes long, the low level level fixed period Tfx also becomes long.

In the example of FIG. 9, the duty detection circuit 36 recognizes a fixed period Ts based on the mode switching signal Smd and the sudden load change detection signal Sdet, and detects the duty of the PFM signal Spfm in the fixed period Ts. Since the duty of the PFM signal Spfm is stable during the fixed period Ts, the duty detection circuit 36 generates the PFM signal according to, for example, a predetermined duty of the predetermined PFM cycle or an average value of the duty of each PFM cycle. Detect the duty of Spfm. Then, the duty detection circuit 36 recognizes the length of the high level period of the PWM signal Spwm by reflecting the detected duty on the length of one cycle of the PWM signal Spwm determined in advance.

The fixed level period generation circuit 35 has, for example, a configuration in which the delay circuit 271 of FIG. 7 is changed to a variable delay circuit. The delay time of the variable delay circuit is variably controlled by the duty detection circuit 36. Here, as a circuit method of the duty detection circuit 36 of FIG. 9, a method of detecting the duty of the PFM signal Spfm and converting it to the length of the high level period in the PWM signal Spwm is used. A method of directly detecting the duty of the signal Spwm may be used. However, the duty of the PWM signal Spwm in the fixed period Ts may be unstable from the viewpoint of the response speed to the sudden change in load, so in this example, the method of detecting the duty of the PFM signal Spfm is used .
<< Main effects of Embodiment 2 >>

As described above, by using the power supply device and the electronic control device according to the second embodiment, in addition to the same effect as obtained in the first embodiment can be obtained, the ripple may be further reduced. That is, even when there are various causes of variation, the length of the level fixed period Tfx can be appropriately maintained accordingly, and the ripple reduction effect can be enhanced.
Third Embodiment
問題 Prerequisite problems》

In the first and second embodiments, depending on the response speed in the PWM control mode, the duty of the PWM signal Spwm may not converge to an appropriate value immediately after switching from the PFM signal Spfm to the PWM signal Spwm. That is, there is a possibility that deviation may occur between the PFM signal Spfm immediately before switching and the duty of the PWM signal Spwm immediately after switching. In this case, ripple may occur due to the improper duty of the PWM signal Spwm.
<< Configuration of Power Supply Device (Third Embodiment) >>

FIG. 10 is a schematic diagram showing an example of configuration of a main part of the power supply device according to Embodiment 3 of the present invention. The power supply device shown in FIG. 10 is different from the power supply device shown in FIG. 2 in the configuration of the switching control circuit SWC3. The switching control circuit SWC3 is different from the switching control circuit SWC1 of FIG. 2 in the configuration of the PWM controller 40, and further includes a duty detection circuit 41 having a configuration slightly different from that of FIG.

The PWM controller 40 stops the generation operation of the PWM signal Spwm in the level fixed period (phase adjustment period) Tfx, and restarts the generation operation of the PWM signal Spwm at the timing when the level fixed period Tfx ends. Specifically, for example, it is assumed that the circuit system of the PWM controller 40 generates the PWM signal Spwm based on the comparison result of the triangular wave signal generated by the triangular wave generation circuit and the error signal. In this case, the triangular wave generation circuit stops the generation operation of the triangular wave signal in the level fixed period Tfx, and resumes the generation operation at the timing when the level fixed period Tfx ends.

Also, the circuit system of the PWM controller 40 periodically sets the SR latch circuit with the clock signal from the clock generation circuit, and generates the PWM signal Spwm by resetting the SR latch circuit at a timing based on the error signal. It is assumed that the method is In this case, the clock generation circuit stops the clock signal generation operation in the level fixed period Tfx, and resumes the generation operation at the timing when the level fixed period Tfx ends. The duty detection circuit 41 detects the duty of the PFM signal Spfm in a fixed period of the mode switching control circuit MDC, and reflects the duty in the first cycle of the PWM signal Spwm from the PWM controller 40 which has resumed the generation operation. .
<< Operation of Power Supply Device (Third Embodiment) >>

FIG. 11 is a timing chart showing an operation example of the power supply apparatus of FIG. 10 at the time of a sudden load change. In FIG. 11, unlike in the case of FIG. 3, the duty detection circuit 41 detects the duty of the PFM signal Spfm in a fixed period Ts in the period T2. Also, in the fixed level period Tfx after the selection timing TMsl, the PWM signal Spwm itself is fixed at the low level along with the stop of the generation operation of the PWM signal Spwm, and accordingly the switching control signal Ssw is also fixed at the 'L' level. Ru.

Thereafter, when the level fixed period Tfx elapses, the generation operation of the PWM signal Spwm is resumed. The duty of the first cycle of the restarted PWM signal Spwm is set to the same value as the duty of the PFM signal Spfm detected by the duty detection circuit 41. As a result, compared to the case of FIG. 3, it is possible to reduce the ripple of the output voltage Vo at the initial stage of the period T3.
<< Main effects of Embodiment 3 >>

As described above, by using the power supply device and the electronic control device according to the third embodiment, in addition to the same effect as that of the first embodiment can be obtained, the ripple may be further reduced. That is, the duty of the PFM signal Spfm in the fixed period Ts has an appropriate value according to the load current Io, and this appropriate value can be reflected in the duty of the PWM signal Spwm immediately after switching. As a result, even if the response speed in the PWM control mode can not be sufficiently obtained, it is possible to reduce the ripple of the output voltage Vo.

As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. For example, the above-described embodiments are described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the described configurations. Also, part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, with respect to a part of the configuration of each embodiment, it is possible to add, delete, and replace other configurations.

For example, the power supply apparatus of each embodiment is widely applicable as an apparatus for supplying power to a load having a large sudden change in load as well as an on-vehicle ECU.

DESCRIPTION OF SYMBOLS 1 electronic control device 11 power supply device 25 PWM controller 26 PFM controller 27 fixed level period generation circuit 28 mode selection circuit 36, 41 duty detection circuit MCU microcontroller MDC mode switching control circuit SWC switching control circuit SWU switching circuit SWh, SWl switching Element Slf level fixed signal Smd mode switching signal Spfm PFM signal Spwm PWM signal Ssw switching control signal Tfx fixed level period Ts fixed period Vo output voltage TMsl selection timing

Claims

A first controller generating a first switching signal using a first control mode;
A second controller generating a second switching signal having a phase independent of the first switching signal using a second control mode;
A phase adjustment period setting circuit that sets a phase adjustment period whose start timing is a selection timing determined at an edge of the second switching signal;
The first switching signal is selected as the switching control signal instead of the second switching signal at the selection timing, and the logic level between the selection timing in the switching control signal and the phase adjustment period is fixed at the logic level Mode selection circuit to control
A switching element which is controlled on / off based on the switching control signal from the mode selection circuit to control the output voltage;
Power supply device.
In the power supply device according to claim 1,
The first control mode is a fixed frequency PWM (Pulse Width Modulation) control mode,
The second control mode is a variable frequency PFM (Pulse Frequency Modulation) control mode.
Power supply.
In the power supply device according to claim 1,
The phase adjustment period setting circuit generates a level fixed signal which becomes one of high level and low level in the phase adjustment period and becomes the other of high level and low level in the period except the phase adjustment period.
Power supply.
In the power supply device according to claim 1,
The fixed logic level is a low level when the selection timing is predetermined to the falling edge of the second switching signal, and is predetermined to the rising edge of the second switching signal. High level,
Power supply.
In the power supply device according to claim 4,
The phase adjustment period is shorter than a pulse width of a logic level different from the fixed logic level in the second switching signal immediately before the selection timing, or in the first switching signal immediately after the selection timing. Shorter than the pulse width of the logic level different from the fixed logic level,
Power supply.
In the power supply device according to claim 4,
Furthermore, a mode switching control is performed to assert a mode switching signal when the output voltage deviates from a predetermined voltage range, recover the output voltage, and negate the mode switching signal at the selection timing after a predetermined period has elapsed. Have a circuit,
The mode selection circuit selects the second switching signal in an assert period of the mode switching signal, and selects the first switching signal in a negate period of the mode switching signal.
Power supply.
In the power supply device according to claim 6,
Furthermore, a duty detection that detects the duty of the first switching signal or the second switching signal during the predetermined period of the mode switching control circuit, and variably controls the length of the phase adjustment period by reflecting the duty. With circuit,
Power supply.
In the power supply device according to claim 7,
The duty detection circuit recognizes the length of a period of a logic level different from the fixed logic level in the first switching signal based on the detection result of the duty, and recognizes the recognized length and the length of the phase adjustment period. Control the phase adjustment period so as to maintain the predetermined ratio.
Power supply.
In the power supply device according to claim 6,
The first controller stops the generation operation of the first switching signal in the phase adjustment period, and resumes the generation operation of the first switching signal at a timing when the phase adjustment period ends.
Power supply.
In the power supply device according to claim 9,
The first control mode is a fixed frequency PWM (Pulse Width Modulation) control mode,
The second control mode is a variable frequency PFM (Pulse Frequency Modulation) control mode,
The power supply device further detects the duty of the second switching signal in the fixed period of the mode switching control circuit, and resumes the duty from the first controller from the first controller. Has a duty detection circuit that reflects the first cycle of the switching signal,
Power supply.
A power supply device that generates a predetermined output voltage based on a battery power supply;
A microcontroller operating with the output voltage of the power supply as a power supply;
An electronic control device having
The power supply device
A first controller generating a first switching signal using a first control mode;
A second controller generating a second switching signal having a phase independent of the first switching signal using a second control mode;
A phase adjustment period setting circuit that sets a phase adjustment period whose start timing is a selection timing determined at an edge of the second switching signal;
The first switching signal is selected as the switching control signal instead of the second switching signal at the selection timing, and the logic level between the selection timing in the switching control signal and the phase adjustment period is fixed at the logic level Mode selection circuit to control
A switching element which is controlled on / off based on the switching control signal from the mode selection circuit to control the output voltage;
An electronic control unit having
In the electronic control unit according to claim 11,
The first control mode is a fixed frequency PWM (Pulse Width Modulation) control mode,
The second control mode is a variable frequency PFM (Pulse Frequency Modulation) control mode.
Electronic control unit.
In the electronic control unit according to claim 11,
The fixed logic level is a low level when the selection timing is predetermined to the falling edge of the second switching signal, and is predetermined to the rising edge of the second switching signal. High level,
Electronic control unit.
In the electronic control unit according to claim 13,
The power supply apparatus further asserts a mode switching signal when the output voltage deviates from a predetermined voltage range, the output voltage recovers, and the mode switching signal is selected at the selection timing after a predetermined period has elapsed. Have a mode switching control circuit to negate
The mode selection circuit selects the second switching signal in an assert period of the mode switching signal, and selects the first switching signal in a negate period of the mode switching signal.
Electronic control unit.
In the electronic control unit according to claim 14,
The power supply device further detects the duty of the first switching signal or the second switching signal in the fixed period of the mode switching control circuit, reflects the duty, and determines the length of the phase adjustment period. Having a duty detection circuit that performs variable control,
Electronic control unit.