JP2002209377A - Dc-dc converter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform zero voltage switching to be conducted surely by controlling the on-timing of a semiconductor switching element. SOLUTION: The inductance Lr of a resonant reactor L1 and the capacitor Cr of a resonant capacitor C1 in a converter circuit 1 are known, and the cycle Tn and the characteristic impedance Zn of a resonant voltage are determined when the respective values Lr, Cr are determined, so that the respective values Tn and Zn are stored in the memory of a control circuit 3 in advance. The control circuit 3 uses the respective values Tn, Zn in the memory, and detects input voltage Vin and an output voltage Iot to calculate a time To in accordance with the following expression, and switches a transistor Q1 from off to on when the time To has passed since the off-time of the transistor Q1. To=Tn.(1+Vin/(Zn.Iot))/2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter circuit for reducing switching loss.

[0002]

2. Description of the Related Art Conventionally, as a DC-DC converter circuit, a switch mode converter using ON / OFF of a semiconductor switching element has been known. Since the switching loss increases as the switching frequency increases, this switch mode converter has a resonance circuit consisting of a resonance reactor and a resonance capacitor, and uses a voltage resonance to perform switching at zero voltage or a current resonance. The switching loss is reduced by adopting a method of performing switching at zero current by utilizing such a method.

FIG. 29 shows a zero-voltage switching type DC.
6 is a timing chart illustrating an operation of the DC converter circuit. Generally, zero-voltage switching DC
The -DC converter circuit is configured so that a reverse voltage is not applied to the semiconductor switching element when the resonance voltage Vr <0 by a diode. Therefore, the off time of the semiconductor switching element is set to T100, and the resonance voltage Vr
Assuming that the time of ≧ 0 is T110, the off time of the semiconductor switching element is set to a constant value of T100> T110. And the output voltage is the switching frequency,
That is, the control is performed by changing the on / off cycle T200.

[0004]

The resonance frequency in a DC-DC converter circuit utilizing such resonance is as follows.
It is determined by the inductance and capacitance of the resonance circuit. If a change in parameters such as inductance and capacitance due to a change in the operating environment or deterioration over time, or a change in the input voltage or output current resulting therefrom, the resonance voltage Vr = 0. , That is, the time T110 when the resonance voltage Vr ≧ 0 changes.

Here, when the ON time T100 of the semiconductor switching element is a constant value as in the above-mentioned prior art,
If the timing at which the resonance voltage Vr becomes 0 is delayed, the switching element is turned on when the voltage applied to the semiconductor switching element is not zero, and the switching loss increases accordingly.

An object of the present invention is to provide a DC-DC converter circuit that solves the above-mentioned problem and controls the ON timing of a semiconductor switching element so that zero-voltage switching can be reliably performed. I do.

[0007]

SUMMARY OF THE INVENTION The present invention provides a switching circuit for turning on and off an input voltage, a resonance circuit including a resonance reactor connected to the switching means and a resonance capacitor resonating with the resonance reactor.
A switching type DC-DC converter circuit comprising a driving unit for turning on and off the switching unit, comprising: a detection unit for detecting an electric signal of the circuit; and a driving control unit for controlling an operation of the driving unit. The drive control means controls the on-timing of the switching means based on the detected electric signal so as to switch the switching means from off to on when no resonance voltage is applied to the switching means.

According to this configuration, when the switching means is turned on and off by the driving means, the DC input voltage is chopped, and the resonance voltage is applied to the switching means by the resonance of the resonance circuit including the resonance reactor and the resonance capacitor. You. At this time, an electric signal of the circuit is detected, and the on timing of the switching means is controlled based on the detected electric signal, and the switching means is switched from off to on when no voltage is applied to the switching means. Thereby, zero voltage switching is reliably performed, and an increase in switching loss is prevented.

The circuit is a step-down converter circuit for stepping down and outputting an input voltage, wherein the detecting means detects an input voltage and an output current as the electric signal, and the driving control means detects the input voltage and the output current. A time during which a resonance voltage is applied to the switching means is calculated based on the input voltage and the output current, and the switching means is turned on from off when the calculated time elapses from the time when the switching means is turned off. Switching may be performed.

According to this configuration, the time during which the resonance voltage is applied to the switching means is calculated based on the detected input voltage and output current, and when the calculated time elapses from the time when the switching means is turned off, the switching means Is switched from off to on. by this,
Even when the time during which the resonance voltage is applied to the switching means changes due to a change in the input voltage or the output current,
Zero voltage switching is reliably performed, and an increase in switching loss is prevented.

Further, the drive control means includes storage means in which the inductance of the resonance reactor, the capacitance of the resonance capacitor, and the cycle of the resonance voltage generated in the resonance capacitor are stored in advance, based on the following equation. The above time may be calculated. To = Tn · (1 + Vin / (Zn · Iot)) / 2 Zn = √ (Lr / Cr) where To: time during which the resonance voltage is applied Tn: period of the resonance voltage generated in the resonance capacitor Zn: Characteristic impedance of resonance circuit Iot: output current Vin: input voltage Lr: inductance of resonance reactor Cr: capacitance of resonance capacitor.

According to this configuration, the resonance of the switching means is performed by the above equation using the previously stored inductance of the resonance reactor, the capacitance of the resonance capacitor, and the period of the resonance voltage generated in the resonance capacitor. The time during which the voltage is applied is calculated. Thus, the calculation of the time is performed accurately and easily.

The circuit is a boost converter circuit which boosts an input voltage and outputs the boosted voltage. The detecting means detects an output voltage and an input current as the electric signal. A time during which the resonance voltage is applied to the switching means is calculated based on the output voltage and the input current, and the switching means is turned on from off when the calculated time elapses from the time when the switching means is turned off. Switching may be performed.

According to this configuration, the time during which the resonance voltage is applied to the switching means is calculated based on the detected output voltage and input current, and when the calculated time elapses from the time when the switching means is turned off, the switching means Is switched from off to on. by this,
Even when the time during which the resonance voltage is applied to the switching means changes due to a change in the output voltage or the input current,
Zero voltage switching is reliably performed, and an increase in switching loss is prevented.

Further, the drive control means includes storage means in which the inductance of the resonance reactor, the capacitance of the resonance capacitor, and the cycle of the resonance voltage generated in the resonance capacitor are stored in advance, based on the following equation. The above time may be calculated. To = Tn · (1 + Vot / (Zn · Iin)) / 2 Zn = √ (Lr / Cr) where To: time during which the resonance voltage is applied Tn: period of the resonance voltage generated in the resonance capacitor Zn: Characteristic impedance of resonance circuit Iin: input current Vot: output voltage Lr: inductance of resonance reactor Cr: capacitance of resonance capacitor.

According to this configuration, the resonance of the switching means is performed by the above equation using the previously stored inductance of the resonance reactor, the capacitance of the resonance capacitor, and the period of the resonance voltage generated in the resonance capacitor. The time during which the voltage is applied is calculated. Thus, the calculation of the time is performed accurately and easily.

The detecting means detects a resonance voltage generated in the resonance capacitor as the electric signal, and the drive control means uses the detected resonance voltage to supply a resonance voltage to the switching means. May be determined when the application is stopped, and when the determined time is reached, the switching means is switched from off to on.

According to this configuration, the resonance voltage generated in the resonance capacitor is detected, the time point at which the resonance voltage is no longer applied to the switching means is determined using the detected resonance voltage, and when the determined time point is reached, The switching means is switched from off to on.

As a result, the parameters of the reactors and capacitors constituting the resonance circuit change due to changes in the operating environment and deterioration over time, so that the peak value and waveform of the resonance voltage change, so that the resonance voltage is applied to the switching means. Even when the time changes, the resonance voltage is detected and the time point is obtained, so that zero-voltage switching is reliably performed, and an increase in switching loss is prevented.

Further, the drive control means may switch the switching means from off to on after a predetermined time from the time when the resonance voltage decreases to a predetermined value or less.

According to this configuration, the switching means is switched from off to on after a predetermined time from the point in time when the resonance voltage decreases to a predetermined value or less. Here, for example, when the peak value of the resonance voltage increases and the time during which the resonance voltage is applied to the switching means becomes longer than the standard state, the time when the resonance voltage becomes equal to or lower than the predetermined value is also later than the standard state. . Therefore, even in such a case, the resonance voltage is not applied to the switching means after a predetermined time from the time when the resonance voltage becomes equal to or lower than the predetermined value. in this way,
Even when the resonance voltage changes due to a change in the operating environment or the like, zero voltage switching is reliably performed, and an increase in switching loss is prevented.

In this case, assuming that the predetermined value is a fixed value set in advance, a circuit can be realized with a simple configuration.

On the other hand, if the predetermined value is a voltage value of the resonance voltage after a predetermined time from the time when the switching means is turned off, or is set according to a peak value of the resonance voltage, Since the predetermined value is not a fixed value but a value reflecting a change in the resonance voltage, zero voltage switching is more reliably performed in response to a change in the operating environment or the like.

[0024]

(First Embodiment) FIG. 1 is a circuit block diagram showing a first embodiment of a DC-DC converter circuit according to the present invention. This circuit is a converter circuit unit 1
And a drive circuit 2 and a control circuit 3.

Converter circuit section 1 has a DC output voltage V lower than DC input voltage Vin applied between input terminals 4 and 5.
ot is generated and applied to the load 8 connected between the output terminals 6 and 7 to constitute a well-known full-waveform zero-voltage switching type step-down converter.

That is, the converter circuit section 1 includes a transistor (switching means) Q1 for chopping the input voltage Vin, a parasitic diode D1 of the transistor Q1, and a series connection to the transistor Q1 in the forward direction, and a reverse connection to the input side. A diode D2 for blocking current, a resonance capacitor C1 connected in parallel to a series circuit of the transistor Q1 and the diode D2, and a diode D2;
2, a reactor L1 for resonance, a reactor L2 for smoothing and a capacitor C2, and a return diode D3 for releasing the energy stored in the reactor L2 when the transistor Q1 is turned off. I have.

A current detecting circuit 9 interposed between the output terminal 6 and a connection point between the reactor L2 and the capacitor C2.
Is composed of, for example, a Hall element or a low resistance, and detects the output current Iot, and sends a detection value proportional to the output current Iot to the control circuit 3.

The drive circuit 2 turns on and off the transistor Q1 according to a control signal from the control circuit 3.

The control circuit 3 comprises a CPU, a memory, an A / D converter, etc., and sends a control signal composed of a pulse signal to the drive circuit 2 to control the on / off of the transistor Q1. Have.

The function of detecting the input voltage Vin, the output voltage Vot, and the output current Iot; After turning off the transistor Q1, the polarity of the voltage generated in the resonance capacitor C1 is inverted, and the application to the transistor Q1 is performed by the diode D2. A function of performing zero voltage switching for switching the transistor Q1 from off to on while being blocked, that is, while Vr <0. The timing of switching the transistor Q1 from off to on will be described later; a function of controlling the switching frequency of the transistor Q1 so that the detected output voltage Vot matches a preset value.

Next, the timing at which the control circuit 3 switches the transistor Q1 from off to on will be described with reference to FIGS. FIGS. 2A, 2B and 2C are waveform diagrams of the resonance voltage Vr of the resonance capacitor C1.

A voltage Vr having a waveform as shown in FIG. 2A is applied as a resonance voltage Vr generated in the resonance capacitor C1, and this voltage Vr is represented by the following equation (1). Vr = Vin + Vp · sin ωt (1) where ω is the resonance angular frequency of the resonance circuit including the resonance reactor L1 and the resonance capacitor C1, and Vp is the amplitude of the AC component of the resonance voltage Vr. This resonance angular frequency ω
Is represented by the following equation (2). 1 / ω = √ (Lr · Cr) (2) where the inductance of the resonance reactor L1 is Lr,
Let Cr be the capacitance of the resonance capacitor C1.

In FIG. 2A, To is the time when Vr ≧ 0, T1 is the time from Vr = 0 to Vr = Vin,
Tn is the period of the resonance voltage Vr. Here, from the figure, since Vp · sin (ωT1) = Vin (3), T1 = sin ⁻¹ (Vin / Vp) / ω (4) is obtained. Vp = Iot · Zn (5) Here, Zn is a characteristic impedance and is represented by the following equation (6). Zn = √ (Lr / Cr) (6) Therefore, the above equation (4) can be expressed as: T1 = sin ⁻¹ [Vin / (Iot · Zn)] / ω (7)

As can be seen from FIG. 2A, To = Tn / 2 + 2 · T1 (8) holds.

Here, when Vin = 0, as shown in FIG. 2B, T1 = 0 and To = Tn / 2. Also,
When Vin = Vp, as shown in FIG. 2C, To = T
n.

Therefore, according to the above equation (8), when Vin = 0, T1 = 0, and when Vin = Vp, T1 = Tn / 4. That is, when Vin changes from 0 to Vp, T1
Changes from 0 to Tn / 4. When this change in T1 is approximated by a linear change, that is, a linear function of Vin, T1 = Vin / (Iot · Zn) · Tn / 4 (9) is obtained from the above equation (7). By substituting this equation (9) into the above equation (8), Is obtained.

In the converter circuit section 1, the inductance Lr of the resonance reactor L1 and the capacitance Cr of the resonance capacitor C1 are known, and the respective values Lr,
Once Cr is determined, the period Tn and the characteristic impedance Z
n is determined. Therefore, the cycle Tn is stored in the memory of the control circuit 3.
Each value of the characteristic impedance Zn is stored in advance.

Using the values Tn and Zn stored in the memory, the detected input voltage Vin and the output current Iot, the control circuit 3 calculates the time To according to the above equation (10). When the time To elapses from the time when the transistor Q1 is turned off, the transistor Q1 is switched from off to on.

The calculation of the time To may be performed every predetermined time (for example, several msec).

As described above, according to the first embodiment, the input voltage Vin and the output current Iot are detected, and the above equation (10) is obtained.
, The transistor Q1 is switched from off to on when the time To elapses from the time when the transistor Q1 is turned off. Therefore, the input voltage Vin and the output current Iot change due to a change in the operating environment or the like. By doing so, even when the timing when Vr = 0 changes, zero-voltage switching can be reliably performed.

(Second Embodiment) FIG. 3 shows a DC according to the present invention.
FIG. 4 is a waveform diagram of the resonance voltage Vr and a timing chart showing ON / OFF of the transistor Q1. The same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 3, the voltage detection circuit 10 connected in parallel to the resonance capacitor C1 has, for example, a low resistance and has a resonance voltage Vr generated in the resonance capacitor C1.
And sends a detection value proportional to the resonance voltage Vr to the comparison circuit 11.

The comparison circuit 11 compares the resonance voltage Vr detected by the voltage detection circuit 10 with the threshold V11 (V11> 0) generated by the voltage threshold generation circuit 12, and the resonance voltage Vr decreases. When Vr ≦ V11, a detection signal to that effect is sent to the delay circuit 13.

The control circuit 15 compares the output voltage Vot with the set value generated by the set value generating circuit 14, and sends an OFF signal to the drive circuit 2 at a switching frequency such that the output voltage Vot is maintained at a constant value. Sends Soff. Further, the control circuit 15 transmits the clock synchronization signal to the delay circuit 13.
To send to.

The delay circuit 13 counts the elapsed time from the output of the detection signal by the comparison circuit 11 based on the clock synchronizing signal sent from the control circuit 15. It sends an ON signal Son.

The predetermined time T2 is set in advance to a time from when the resonance voltage Vr falls below the predetermined value V11 to when Vr <0.

The drive circuit 2 turns off the transistor Q1 when the off signal Soff is input from the control circuit 15, and switches the transistor Q1 from off to on when the on signal Son is input from the delay circuit 13.

With this configuration, as shown in FIG. 4, the transistor Q1 is turned on when a predetermined time T2 elapses from the point in time when the resonance voltage Vr decreases and Vr ≦ V11.

FIG. 5 is a circuit block diagram showing a more specific circuit configuration example of the second embodiment, and FIG.
5 is a timing chart showing the signals of FIG. FIG.
Here, the illustration of the converter circuit unit 1 is omitted, and the same components as those in FIG. 3 are denoted by the same reference numerals.

In FIG. 5, voltage frequency conversion (V / F)
The circuit 16 sets a switching frequency based on the voltage difference V1 between the output voltage Vot and the set value, and sends a timing signal determined by the switching frequency to the synthesizing circuit 17 (FIG. 6). The synthesizing circuit 17 sends an off signal Soff to the drive circuit 2 based on the timing signal (FIG. 6).

When the transistor Q1 is turned off by the off signal Soff, the resonance voltage Vr is taken into the comparison circuit 11 (FIG. 6). On the other hand, the threshold value V11 generated by the voltage threshold value generation circuit 12 is taken into the comparison circuit 11 (FIG. 6).
of).

Then, the comparison circuit 11 compares the changing resonance voltage Vr with the threshold value V11 and outputs an ON (high level) signal while Vr ≧ V11 (FIG. 6). The delay circuit 18 outputs the output signal from the comparison circuit 11 for a predetermined time T2.
The output is delayed with a delay (FIG. 6).

The output signal from delay circuit 18 is further delayed by delay circuit 19 for a predetermined time T21 (FIG. 6) and inverted by inverter gate circuit 20 (FIG. 6).

The AND gate circuit 21 combines the logical product of these signals to generate a pulse signal (FIG. 6) and sends it to the combining circuit 17.

When the pulse signal is input from the AND gate circuit 21, the synthesizing circuit 17 sends the ON signal S to the drive circuit 2.
On is transmitted (of FIG. 6).

As shown in FIG. 6, when the resonance voltage Vr falls from the peak value and Vr ≦ V11, Vr = 0
Assuming that the time until becomes T20, T2> T20 is set. In the present embodiment, for example, T2 = Tn / 4
, Which ensures zero voltage switching.

As described above, according to the second embodiment, the resonance voltage Vr generated in the resonance capacitor C1 is Vr ≦ V1.
A predetermined time T2 from the point in time at which it becomes 1 to a time when Vr <0 is surely set in advance, a resonance voltage Vr (instantaneous value) is detected, and a predetermined time from the point in time when the resonance voltage Vr becomes Vr ≦ V11 Since the transistor Q1 is switched from off to on after the passage of T2, the resonance voltage Lr and Cr of the resonance reactor L1 and the resonance capacitor C1 change due to changes in the operating environment and deterioration over time, so that the resonance voltage changes. Even if the timing of Vr = 0 changes,
Zero voltage switching can be performed reliably. Therefore, an increase in switching loss can be prevented.

(Third Embodiment) FIG. 7 shows a DC according to the present invention.
FIG. 8 is a circuit block diagram showing a third embodiment of the DC converter circuit, and FIG. 8 is a waveform diagram of the resonance voltage Vr and a timing chart showing ON / OFF of the transistor Q1. 1 and 3 are denoted by the same reference numerals.

In FIG. 7, the control circuit 31 compares the output voltage Vot with the set value generated by the set value generating circuit 14, and operates at a switching frequency such that the output voltage Vot is maintained at a constant value. 2 for transmitting an off signal Soff. Further, the control circuit 31 includes the transistor Q1
From the OFF time point, a clock synchronization signal for clocking is sent to the delay circuits 32 and 33.

The delay circuit 32 takes in the resonance voltage Vr detected by the voltage detection circuit 10 and counts the elapsed time from the time when the transistor Q1 is turned off based on the clock synchronization signal sent from the control circuit 31, and The resonance voltage Vr at the time when the time T31 has elapsed is sent to the holding circuit 34.

The holding circuit 34 holds the resonance voltage Vr sent from the delay circuit 32 as the threshold value V31 and sends it to the comparison circuit 35. The comparison circuit 35 captures the resonance voltage Vr detected by the voltage detection circuit 10,
The resonance voltage Vr is compared with a threshold value V31 sent from the holding circuit 34. When the resonance voltage Vr decreases and Vr ≦ V31, a detection signal to that effect is sent to the delay circuit 33.

The delay circuit 33 counts the elapsed time from the time when the detection signal is sent out by the comparison circuit 35 based on the clock synchronization signal sent from the control circuit 31, and when a predetermined time T32 (> T31) elapses. The on signal Son is sent to the drive circuit 2. Also, the delay circuit 33
Resets the threshold value V31 held in the holding circuit 34 after the output of the ON signal Son.

With this configuration, as shown in FIG. 8, the resonance voltage Vr at the time when a predetermined time T31 has elapsed from the time when the transistor Q1 is turned off is set to the threshold value V31, and the resonance voltage Vr
A predetermined time T from the point when r decreases and Vr ≦ V31
When 32 (> T31) has elapsed, the transistor Q1 is switched from off to on.

FIG. 9 is a circuit block diagram showing a more specific example of the circuit configuration of the third embodiment, and FIG. 10 is a timing chart showing signals of the components ′,.
In FIG. 9, the illustration of the converter circuit unit 1 is omitted, and the same components as those in FIG. 7 are denoted by the same reference numerals.

In FIG. 9, the switches 36 and 37 are, for example, transistors, and the switch 36 is normally on and the switch 37 is normally off.

The voltage frequency conversion (V / F) circuit 16 sets the switching frequency based on the voltage difference V1 between the output voltage Vot and the set value, and sends a timing signal determined by the switching frequency to the synthesizing circuit 38. (Figure 1
0). The synthesizing circuit 38 sends the off signal Soff to the drive circuit 2 based on the timing signal ('in FIG. 10). Further, the synthesizing circuit 38 outputs the off signal S
A clock synchronizing signal for timing is transmitted to the delay circuit 39 from the time when off is transmitted.

When the transistor Q1 is turned off by the off signal Soff, the resonance voltage Vr is taken into the comparison circuit 35 (FIG. 10). The delay circuit 39 includes a transistor Q
The elapsed time is counted from the time point of turning off the first time, and the predetermined time T3
When 1 has elapsed, the switch 36 is turned off, and the comparison circuit 3
5 is the resonance voltage Vr when the switch 36 is turned off.
Is held as the threshold value V31 (FIG. 10).
Then, the comparison circuit 35 compares the changing resonance voltage Vr with the threshold value V31, and outputs an ON (high level) signal while Vr ≧ V31 (FIG. 10).

The delay circuit 41 delays the output signal from the comparison circuit 35 by a predetermined time T32 and outputs it (FIG. 10). Note that T32> T31 is set.

The output signal from delay circuit 41 is further delayed by delay circuit 42 for a predetermined time T33 (FIG. 10) and inverted by inverter gate circuit 43 (FIG. 10).

The AND gate circuit 44 generates a pulse signal by synthesizing the logical product of these signals (FIG. 10).
The signal is sent to the combining circuit 38 and the delay circuit 45.

When the pulse signal is input from the AND gate circuit 44, the synthesizing circuit 38 sends the ON signal S to the drive circuit 2.
On is transmitted ('in FIG. 10). The delay circuit 45 delays the pulse signal input from the AND gate circuit 44 by a predetermined time T34 and outputs it to the switch 37 (FIG. 10). The threshold value V31 that has been set is reset.

Therefore, as shown in FIG.
The signal on is output in synchronization with the falling point of, but this point is a predetermined time T32 after the falling point of (at the time when Vr ≦ V31). Here, T32
Is that T32> T31 and the ON signal Son is Vr <0
Since the value is set so as to be output during the period, zero voltage switching is reliably performed.

Further, the threshold value V31 held in the comparison circuit 35 is reset for each cycle of the resonance voltage Vr. Therefore, in FIG. 10, for example, when the resonance voltage Vr on the right side is higher than the resonance voltage Vr on the left side, the resonance voltage Vr at the time when the switch 36 is turned off is set.
, V31 <V32, and the threshold level of the resonance voltage Vr on the right side increases from the resonance voltage Vr on the left side.

Here, in the waveform of the resonance voltage Vr on the left side, the time T31 from the time when the transistor Q1 is turned on to the instantaneous value V31 is substantially the same as the time T35 from the instantaneous value V31 to Vr = 0. Value. Also,
In the waveform of the resonance voltage Vr on the right side, the transistor Q1
T31 from the time when the switch is turned on to the instantaneous value V32
And a time T36 from the instantaneous value V32 to Vr = 0.
Is almost the same value.

Accordingly, the instantaneous value of the resonance voltage Vr at the time when the predetermined time T31 has elapsed from the time when the transistor Q1 is turned on is used as the threshold value. It can be said that the resonance voltage Vr ≒ 0 when a predetermined time T31 elapses from the time.

As described above, according to the third embodiment, the instantaneous value of the resonance voltage Vr at the time when the predetermined time T31 has elapsed from the time when the transistor Q1 is turned on is used as the threshold value,
For a predetermined time T32 (> T3) from the time when
Since the transistor Q1 is switched from off to on after 1), zero voltage switching can be reliably performed, and an increase in switching loss can be prevented.

In particular, when the magnitude or the waveform of the resonance voltage Vr changes, the instantaneous value at the time when the predetermined time T31 has elapsed changes, so that the threshold value changes in accordance with the change in the resonance voltage Vr. Since the time required from the threshold value to the point at which Vr = 0 is hardly changed, even if the timing at which the resonance voltage Vr = 0 changes due to a change in the operating environment, aging, etc., it is necessary to reliably perform zero voltage switching. Can be.

(Fourth Embodiment) FIG.
FIG. 12 is a circuit block diagram showing a fourth embodiment of the C-DC converter circuit. FIG. 12 is a waveform diagram of the resonance voltage Vr and a timing chart showing ON / OFF of the transistor Q1.
The same components as those in FIG. 3 are denoted by the same reference numerals.

In FIG. 11, the control circuit 51 compares the output voltage Vot with the set value generated by the set value generation circuit 14, and determines the drive circuit at a switching frequency such that the output voltage Vot is maintained at a constant value. 2 for transmitting an off signal Soff. The control circuit 51 includes a transistor Q
A clock synchronizing signal for clocking is sent to the delay circuit 52 from the off point of 1.

The holding circuit 53 holds the peak value of the resonance voltage Vr detected by the voltage detection circuit 10.
The voltage dividing circuit 54 sends the predetermined ratio (<1) of the peak value held by the holding circuit 53 to the comparing circuit 55 as a threshold value.

The comparison circuit 55 compares the resonance voltage Vr detected by the voltage detection circuit 10 with the threshold value sent from the voltage dividing circuit 54. The signal is sent to the delay circuit 52.

The delay circuit 52 counts the elapsed time from the point in time when the detection signal is sent out by the comparison circuit 55 based on the clock synchronization signal sent from the control circuit 51, and turns on the ON signal Son when a predetermined time T41 has elapsed. This is sent to the drive circuit 2.

With this configuration, as shown in FIG. 12, the peak value Vrp of the resonance voltage Vr (thick solid line in FIG. 12)
The thin solid line is maintained, and a predetermined ratio of this peak value Vrp (<
1) is a threshold Vth (thin solid line in the figure), and the resonance voltage V
A predetermined time T from the time when r decreases to Vr ≦ Vth
When 41 elapses, the transistor Q1 is turned on.

The holding circuit 53 is formed of, for example, a capacitor. Since the peak value Vrp is gradually reduced as shown in FIG. 12, it is not necessary to reset the peak value held by the holding circuit 53 every cycle. .

FIG. 13 is a circuit block diagram showing a more specific example of the circuit configuration of the fourth embodiment, and FIG. 14 is a timing chart showing signals of various parts of FIG. In FIG. 13, the illustration of the converter circuit unit 1 is omitted, and the same components as those in FIGS. 5 and 11 are denoted by the same reference numerals.

The voltage frequency conversion (V / F) circuit 16 sets the switching frequency based on the voltage difference V1 between the output voltage Vot and the set value, and sends a timing signal determined by the switching frequency to the synthesizing circuit 56. (Figure 1
4). The synthesizing circuit 56 sends an off signal Soff to the drive circuit 2 based on the timing signal (FIG. 14).

When the transistor Q1 is turned off by the off signal Soff, the resonance voltage Vr is taken into the comparison circuit 55 (FIG. 14), and a circuit in which the capacitor C41 is connected in parallel to the series circuit of the resistors R41 and R42. Is input to The connection point of the resistors R41 and R42 is connected to the comparison circuit 55, so that the capacitor C41 is charged by the resonance voltage Vr and the resistor R of the charged voltage is charged.
The divided voltage values of R41 and R42 are input to the comparison circuit 55 as threshold values (FIG. 14).

Here, Vrp, V shown in FIG.
relationship th, resistors R41, R42 of the resistance R _41, R
When ₄₂ is expressed as _{Vth = Vrp · R 42 / (} R 41 + R 42). The capacitor C41 forms a holding circuit 53, and the resistors R41 and R42 form a voltage dividing circuit 54.

The comparison circuit 55 compares the changing resonance voltage Vr with the threshold value Vth, and outputs an ON (high level) signal while Vr ≧ Vth (FIG. 14).

The delay circuit 57 delays the output signal from the comparison circuit 55 by a predetermined time T41 and outputs it (FIG. 14). The output signal from the delay circuit 57 is
8 and a predetermined time T42 (see FIG. 1).
4), and inverted by the inverter gate circuit 59 (FIG. 14).

The AND gate circuit 60 generates a pulse signal by synthesizing the logical product of these signals (FIG. 14).
Output to the synthesis circuit 56.

When a pulse signal is input from the AND gate circuit 60, the synthesizing circuit 56 sends an ON signal S to the driving circuit 2.
on is output, thereby turning on the transistor Q1 (of FIG. 14).

Therefore, as shown in FIG.
On is output in synchronization with the falling point of, but at this point, the falling point of (that is, Vr ≦ Vth
) After a predetermined time T41. here,
Since T41 is set so that the ON signal Son is output while Vr <0, zero voltage switching is reliably performed.

As described above, according to the fourth embodiment, the predetermined ratio Vth of the peak value Vrp of the resonance voltage Vr is set as the threshold,
A predetermined time T4 from when the resonance voltage Vr falls below the threshold value
Since the transistor Q1 is switched from off to on after the lapse of 1, zero voltage switching can be reliably performed, and an increase in switching loss can be prevented.

When the magnitude or waveform of the resonance voltage Vr changes due to a change in the operating environment or deterioration over time, the threshold value Vth changes in accordance with the change. Therefore, Vr = 0 due to a change in the operating environment or the like. , The zero voltage switching can be reliably performed.

In each of the above-described embodiments, the converter circuit unit 1 is described using the step-down converter of the full-waveform zero-voltage switching system. However, the present invention is not limited to this. The present invention can be applied to a general zero-voltage switching type converter including a boost converter.

Therefore, specific examples of the step-up converter of the full waveform zero voltage switching type will be described below as fifth to eighth embodiments.

(Fifth Embodiment) FIG. 15 shows the structure of a D according to the present invention.
It is a circuit block diagram showing a fifth embodiment of a C-DC converter circuit. This circuit includes a converter circuit unit 101
And a drive circuit 102 and a control circuit 103.

The converter circuit section 101 has an input terminal 10
A DC output voltage Vot higher than a DC input voltage Vin applied between the output terminals 4 and 105 is generated and applied to a load 108 connected between the output terminals 106 and 107. And a shape converter.

That is, the converter circuit unit 101
Is connected in parallel to a series circuit consisting of a transistor (switching means) Q11 for chopping the input voltage Vin, a parasitic diode D11 of the transistor Q11, a diode D12 for blocking reverse current to the input side, and a transistor Q11 and a diode D12. The resonance capacitor C11, the resonance reactor L11, the reactor L12 for storing energy when the transistor Q11 is on, the capacitor C12 for smoothing the output voltage Vot, and the output side to the input side. And a diode D13 for preventing a backflow of current.

A current detection circuit 109 interposed between the input terminal 104 and the reactor L12 is formed of, for example, a Hall element or a low resistance and detects the input current Iin, and detects a detection value proportional to the input current Iin. It is sent to the control circuit 103.

The drive circuit 102 turns on and off the transistor Q11 according to a control signal from the control circuit 103.

The control circuit 103 includes a CPU, a memory, an A /
It comprises a D converter or the like and sends a control signal composed of a pulse signal to the drive circuit 102 to control the on / off of the transistor Q11, and has the following functions.

A function of detecting the input voltage Vin, the input current Iin, and the output voltage Vot; after turning off the transistor Q11, the polarity of the voltage generated in the resonance capacitor C11 is inverted, and the diode D
A function of performing zero voltage switching for switching the transistor Q11 from off to on while the application to the transistor Q11 is blocked by the transistor 12, that is, while Vr <0. The timing of switching the transistor Q11 from off to on will be described later; a function of controlling the switching frequency of the transistor Q11 so that the detected output voltage Vot matches a preset value.

Next, the switching timing of the transistor Q11 from off to on by the control circuit 103 will be described with reference to FIGS. FIGS. 16A, 16B and 16C are waveform diagrams of the resonance voltage Vr generated in the resonance capacitor C11.

As the resonance voltage Vr generated in the resonance capacitor C11, a voltage Vr having a waveform as shown in FIG.
Is applied, and this voltage Vr is expressed as follows: Vr = Vot + Vp · sinωt (11) Here, ω is the resonance angular frequency of the resonance circuit including the resonance reactor L11 and the resonance capacitor C11, and Vp is the amplitude of the AC component of the resonance voltage Vr.

The resonance angular frequency ω is expressed as 1 / ω = √ (Lr · Cr) (12) Here, the inductance of the resonance reactor L11 is Lr, and the capacitance of the resonance capacitor C11 is Cr.

In FIG. 16A, To is a time of Vr ≧ 0, T51 is a time from Vr = 0 to Vr = Vot, and Tn is a period of the resonance voltage Vr. Here, from the figure, since Vp · sin (ωT51) = Vot (13), T51 = sin ⁻¹ (Vot / Vp) / ω (14) is obtained. Vp = Iin.Zn (15) Here, Iin is an input current. Zn is a characteristic impedance, and is represented by Zn = √ (Lr / Cr) (16) Therefore, the above equation (14) can be expressed as: T51 = sin ⁻¹ (Vot / (Iin · Zn)) / ω (17)

As can be seen from FIG. 16A, To = Tn / 2 + 2 · T51 (18) holds.

Here, when Vot = 0, as shown in FIG. 16B, T51 = 0 and To = Tn / 2. Further, when Vot = Vp, as shown in FIG.
o = Tn.

Therefore, according to the above equation (18), when Vot = 0, T51 = 0, and when Vot = Vp, T51 = Tn /
It becomes 4. That is, when Vot changes from 0 to Vp,
T51 changes from 0 to Tn / 4. When this change in T51 is approximated by a linear change, that is, by a linear function of Vot, the following equation (17) is obtained from the above equation (17): T51 = Vot / (Iin · Zn) · Tn / 4 (19) When this equation (19) is substituted into the above equation (18), To = TnＴ (1 + Vot / (Iin ・ Zn)) / 2 (20) is obtained.

In converter circuit section 101, inductance Lr of resonance reactor L11 and capacitance Cr of resonance capacitor C11 are known, and when values Lr and Cr are determined, period Tn and characteristic impedance Zn are determined. Therefore, each value of the cycle Tn and the characteristic impedance Zn is stored in the memory of the control circuit 103 in advance.

The control circuit 103 uses the values Tn and Zn stored in the memory, the detected output voltage Vot and the input current Iin according to the above equation (20).
The time To is calculated, and when the time To elapses from the time when the transistor Q11 is turned off, the transistor Q11 is switched from off to on.

The calculation of the time To may be performed every predetermined time (for example, several msec).

As described above, according to the fifth embodiment, the output voltage Vot and the input current Iin are detected, the time To is calculated according to the above equation (20), and the time To elapses from the time when the transistor Q11 is turned off. Since the transistor Q11 is switched from off to on in (1), when the circuit configuration of the converter circuit unit 101 is determined, the inductance Lr and the capacitance Cr of the resonance circuit are determined to be constant values. V
ot and input current Iin change, so that Vr = 0
, The zero voltage switching can be reliably performed.

(Sixth Embodiment) FIG.
FIG. 18 is a circuit block diagram showing a sixth embodiment of the C-DC converter circuit. FIG. 18 is a waveform diagram of the resonance voltage Vr and a timing chart showing ON / OFF of the transistor Q11. The same components as those in FIG. 15 are denoted by the same reference numerals.

In FIG. 17, comparison circuit 111 detects a voltage at a connection point between resonance capacitor C11 and resonance reactor L11, that is, a resonance voltage Vr.
The resonance voltage Vr is compared with a threshold value V51 (> 0) generated by the voltage threshold generation circuit 112, and when the resonance voltage Vr decreases and becomes Vr ≦ V51, a detection signal to that effect is sent to the delay circuit 113. Is what you do.

The control circuit 114 compares the output voltage Vot with the set value generated by the set value generating circuit 115, and sends an off signal to the drive circuit 102 at a switching frequency such that the output voltage Vot is maintained at a constant value. Sends Soff. Further, the control circuit 114 sends the clock synchronization signal to the delay circuit 113.

The delay circuit 113 is based on the clock synchronizing signal sent from the control circuit 114,
The ON time Son is sent to the drive circuit 102 when the predetermined time T51 has elapsed.

The drive circuit 102 turns off the transistor Q11 when the off signal Soff is input from the control circuit 114, and switches the transistor Q11 from off to on when the on signal Son is input from the delay circuit 113.

As shown in FIG. 18, the predetermined time T51 is set in advance to a value larger than the time T50 from the time when the resonance voltage Vr falls below the predetermined value V51 to Vr = 0, that is, T51> T50. The predetermined time T5
When 1 has elapsed, Vr <0 is definitely established.
With such a configuration, the resonance voltage Vr decreases and Vr ≦
When a predetermined time T51 elapses from the point in time when V51 has been reached,
Transistor Q11 is turned off.

FIG. 19 is a circuit block diagram showing a more specific example of the circuit configuration of the sixth embodiment, and FIG. 20 is a timing chart showing signals of various parts of FIG. In FIG. 19, the illustration of the converter circuit unit 101 is omitted, and the same components as those in FIG. 17 are denoted by the same reference numerals.

In FIG. 19, voltage frequency conversion (V /
F) The circuit 116 calculates a voltage difference V between the output voltage Vot and the set value.
2, and a timing signal determined by the switching frequency is sent to the synthesizing circuit 117 (FIG. 20). The synthesis circuit 117
An off signal Soff is sent to the drive circuit 102 based on the timing signal (FIG. 20).

The transistor Q11 is turned on by the off signal Soff.
Is turned off, the resonance voltage Vr is taken into the comparison circuit 111 (FIG. 20). On the other hand, the voltage threshold generation circuit 11
The threshold value V51 generated in 2 is taken into the comparison circuit 111 (FIG. 20).

Then, the comparing circuit 111 compares the changing resonance voltage Vr with the threshold value V51, and when Vr ≧ V51,
An on (high level) signal is output (FIG. 20). The delay circuit 118 delays the output signal from the comparison circuit 111 by a predetermined time T51 and outputs it (FIG. 20).

The output signal from delay circuit 118 is further delayed by delay circuit 119 for a predetermined time T52 (of FIG. 20), and the output signal of inverter gate circuit 12
It is inverted by 0 (of FIG. 20).

The AND gate circuit 121 generates a pulse signal (FIG. 20) by synthesizing the logical product of these signals, and sends it to the synthesizing circuit 117.

The combining circuit 117 includes the AND gate circuit 12
When a pulse signal is input from No. 1, an ON signal Son is sent to the drive circuit 102 (FIG. 20).

As shown in FIG. 20, when the resonance voltage Vr drops from the peak value and Vr ≦ V51, Vr =
Assuming that the time until it becomes 0 is T50, T51> T50
In the present embodiment, for example, T51 = T
n / 4, which ensures zero-voltage switching.

As described above, according to the sixth embodiment, the resonance voltage Vr generated in the resonance capacitor C11 is Vr ≦ V
A predetermined time T51 from the time when the voltage reaches 51 to a time when Vr <0 is definitely set in advance, the resonance voltage Vr (instantaneous value) is detected, and a predetermined time from the time when the resonance voltage Vr satisfies Vr ≦ V51 is obtained. Since the transistor Q11 is switched from off to on after the passage of T51, each value Lr, Cr of the resonance reactor L11 and the resonance capacitor C11 changes due to a change in the operating environment and aging, so that the resonance voltage is changed. Even when the timing at which Vr = 0 changes, zero voltage switching can be reliably performed. Therefore, an increase in switching loss can be prevented.

(Seventh Embodiment) FIG. 21 shows a structure of a D according to the present invention.
FIG. 22 is a circuit block diagram showing a seventh embodiment of the C-DC converter circuit, and FIG. 22 is a waveform diagram of the resonance voltage Vr and a timing chart showing ON / OFF of the transistor Q11. The same components as those in FIG. 17 are denoted by the same reference numerals.

In FIG. 21, the control circuit 131 compares the output voltage Vot with the set value generated by the set value generating circuit 115, and operates at a switching frequency such that the output voltage Vot is maintained at a constant value. Off signal Soff at 102
Is sent. In addition, the control circuit 131 sends a clock synchronization signal for clocking to the delay circuits 132 and 133 from the time when the transistor Q11 is turned off.

The delay circuit 132 includes a resonance capacitor C1.
In addition to taking in the voltage at the connection point between 1 and the resonance reactor L11, that is, the resonance voltage Vr, the elapsed time from the time when the transistor Q11 is turned off is counted based on the clock synchronization signal sent from the control circuit 131, and the predetermined time T71 The resonance voltage Vr at the time when
34.

The holding circuit 134 holds the resonance voltage Vr sent from the delay circuit 132 as the threshold value V71 and sends it to the comparison circuit 135. Comparison circuit 135
Captures the resonance voltage Vr, compares the resonance voltage Vr with a threshold value V71 sent from the holding circuit 134, and sends a detection signal to that effect to the delay circuit 133 when the resonance voltage Vr decreases and becomes Vr ≦ V71. Is what you do.

The delay circuit 133 counts the elapsed time from the point at which the comparison circuit 135 sends out the detection signal based on the clock synchronization signal sent from the control circuit 131,
The ON signal Son is sent to the drive circuit 102 when a predetermined time T72 (> T71) has elapsed. Further, the delay circuit 133 outputs the holding circuit 1 after outputting the ON signal Son.
The threshold V71 held at 34 is reset.

With this configuration, as shown in FIG. 22, the resonance voltage Vr at the time when a predetermined time T71 has elapsed from the time when the transistor Q11 is turned off is set to the threshold value V71, and the resonance voltage Vr is reduced to Vr ≦ V71. After a lapse of a predetermined time T72 from the point in time, the transistor Q11 is switched from off to on.

The predetermined time T72 is set in advance to a time that satisfies T72> T71 and Vr = 0.

FIG. 23 is a circuit block diagram showing a more specific example of the circuit configuration of the seventh embodiment, and FIG. 24 is a timing chart showing signals of the components 〜 of FIG. In FIG. 23, the illustration of the converter circuit unit 101 is omitted, and the same components as those in FIGS. 19 and 21 are denoted by the same reference numerals.

In FIG. 23, switches 136 and 137
Is composed of, for example, a transistor.
Reference numeral 6 denotes a normal ON state, and the switch 137 is normally OFF.

The voltage frequency conversion (V / F) circuit 116
The switching frequency is set based on the voltage difference V2 between the output voltage Vot and the set value, and a timing signal determined by the switching frequency is sent to the combining circuit 138 (FIG. 24).

The synthesizing circuit 138 sends an off signal Soff to the drive circuit 102 based on the timing signal ('in FIG. 24). In addition, the synthesis circuit 138
A clock synchronization signal for timing is transmitted to the delay circuit 139 from the time when the off signal Soff is transmitted.

The transistor Q11 is turned on by the off signal Soff.
Is turned off, the resonance voltage Vr is taken into the comparison circuit 135 (FIG. 24). The delay circuit 139 counts the elapsed time from the time when the transistor Q11 is turned off, and when a predetermined time T71 elapses, turns off the switch 136,
The comparison circuit 135 holds the instantaneous value of the resonance voltage Vr at the time when the switch 136 is turned off as the threshold value V71 (FIG. 24). Then, the comparison circuit 135 compares the changing resonance voltage Vr with the threshold value V71, and outputs an ON (high level) signal only when Vr ≧ V71 (FIG. 24).

The delay circuit 140 outputs the output signal from the comparison circuit 135 with a delay of a predetermined time T72 (FIG. 2).
4). As described above, T72> T71 is set.

The output signal from delay circuit 140 is further delayed by delay circuit 141 for a predetermined time T73 (see FIG. 24), and
2 (FIG. 24).

The AND gate circuit 143 combines the logical product of these signals to generate a pulse signal (FIG. 24) and sends it to the combining circuit 138 and the delay circuit 144.

The synthesizing circuit 138 includes the AND gate circuit 14
When a pulse signal is input from No. 3, an ON signal Son is sent to the drive circuit 102 ('in FIG. 24). Delay circuit 14
4 delays the pulse signal input from the AND gate circuit 143 by a predetermined time T74 and outputs it to the switch 137 (FIG. 24).
7 is turned on, and the threshold value V71 held in the comparison circuit 135 is reset.

Therefore, as shown in FIG.
On is output in synchronization with the falling time point of, but this time point is a predetermined time T72 after the falling time point (at the time when Vr ≦ V71). Here, T72
Is that T72> T71 and the ON signal Son is Vr <0
Since the value is set so as to be output during the period, zero voltage switching is reliably performed.

The threshold value held in the comparison circuit 135 is reset every cycle of the resonance voltage Vr. Therefore, in FIG. 24, for example, when the resonance voltage Vr on the right side is higher than the resonance voltage Vr on the left side,
The instantaneous values V71 and V72 of the resonance voltage Vr at the time when the switch 136 is turned off satisfy V71 <V72, and the level of the threshold value in the resonance voltage Vr on the right side increases from the resonance voltage Vr on the left side.

Here, in the waveform of the resonance voltage Vr on the left side, the time T71 from the time when the transistor Q11 is turned off to the instantaneous value V71 is substantially the same as the time T75 from the instantaneous value V71 to Vr = 0. Value. Further, in the waveform of the resonance voltage Vr on the right side, the time T from the time when the transistor Q11 is turned off to the instantaneous value V72 is obtained.
71 and the time T from the instantaneous value V72 to Vr = 0.
Again, 76 is almost the same value.

Therefore, by setting the instantaneous value of the resonance voltage Vr at the time when the predetermined time T71 has elapsed from the time when the transistor Q11 is turned off to the threshold value, the time when the resonance voltage Vr falls below the threshold value regardless of the threshold level From the predetermined time T71
It can be said that the resonance voltage Vr ≒ 0 is reached at the point in time when elapses.

As described above, according to the seventh embodiment, the instantaneous value of the resonance voltage Vr at the time when the predetermined time T71 has elapsed from the time when the transistor Q11 is turned off is used as the threshold value,
A predetermined time T72 (> T7) from the time when r becomes equal to or less than the threshold value
Since the transistor Q11 is switched from off to on after 1), zero voltage switching can be reliably performed, and an increase in switching loss can be prevented.

In particular, when the magnitude or the waveform of the resonance voltage Vr changes, the instantaneous value at the time when the predetermined time T71 elapses changes. Therefore, the threshold value changes according to the change in the resonance voltage Vr. Since the time required from the threshold value to the point at which Vr = 0 is hardly changed, even if the timing at which the resonance voltage Vr = 0 changes due to a change in the operating environment, aging, etc., it is necessary to reliably perform zero voltage switching. Can be.

(Eighth Embodiment) FIG.
26 is a circuit block diagram showing an eighth embodiment of the C-DC converter circuit. FIG. 26 is a waveform diagram of the resonance voltage Vr and a timing chart showing ON / OFF of the transistor Q11. The same components as those in FIG. 17 are denoted by the same reference numerals.

In FIG. 25, the control circuit 151 compares the output voltage Vot with the set value generated by the set value generation circuit 115 and operates at a switching frequency such that the output voltage Vot is maintained at a constant value. Off signal Soff at 102
Is sent. Further, the control circuit 151 sends a clock synchronization signal for clocking to the delay circuit 152 from the time when the transistor Q11 is turned off.

The holding circuit 153 includes a resonance capacitor C1.
The voltage dividing circuit 154 holds the peak value of the resonance voltage Vr by taking in the voltage at the connection point of the resonance reactor L1 and the resonance reactor L11, that is, the resonance voltage Vr. The ratio (<1) is sent to the comparison circuit 155 as a threshold value.

The comparison circuit 155 takes in the resonance voltage Vr, compares the resonance voltage Vr with a threshold value sent from the voltage dividing circuit 154, and, when the resonance voltage Vr decreases and falls below the threshold value, a detection signal indicating that. To the delay circuit 152.

The delay circuit 152 counts the elapsed time from the point at which the detection signal is sent out by the comparison circuit 155 based on the clock synchronization signal sent from the control circuit 151.
The ON signal Son is sent to the drive circuit 102 when the predetermined time T81 has elapsed.

With this configuration, as shown in FIG. 26, the peak value Vrp of the resonance voltage Vr (thick solid line in FIG. 26)
The thin solid line is maintained, and a predetermined ratio of this peak value Vrp (<
1) is a threshold Vth (thin solid line in the figure), and the resonance voltage V
A predetermined time T from the time when r decreases to Vr ≦ Vth
When 81 elapses, the transistor Q11 is turned off.

The holding circuit 153 is composed of, for example, a capacitor, and the peak value Vrp is gradually reduced as shown in FIG. 26. Therefore, it is not necessary to reset the peak value held by the holding circuit 153 every cycle. .

FIG. 27 is a circuit block diagram showing a more specific example of the circuit configuration of the eighth embodiment, and FIG. 28 is a timing chart showing signals of various parts of FIG. In FIG. 27, the illustration of the converter circuit unit 101 is omitted, and the same components as those in FIGS. 19 and 25 are denoted by the same reference numerals.

The voltage frequency conversion (V / F) circuit 116
The switching frequency is set based on the voltage difference V2 between the output voltage Vot and the set value, and a timing signal determined by the switching frequency is sent to the synthesizing circuit 156 (FIG. 28). The synthesizing circuit 156 sends an off signal Soff to the drive circuit 102 based on the timing signal (FIG. 28).

The transistor Q11 is turned on by the off signal Soff.
Is turned off, the resonance voltage Vr is taken into the comparison circuit 155 (FIG. 28), and the resistors R81 and R8 are turned on.
2 and a holding circuit 153 including a capacitor C81 are connected in parallel to each other. The connection point of the resistors R81 and R82 is connected to the comparison circuit 155, and the capacitor C81 is connected by the resonance voltage Vr.
Is charged, and the resistors R81, R
The divided voltage value by 82 is input to the comparison circuit 155 as a threshold value (of FIG. 28).

Here, Vrp, V shown in FIG.
relationship th, the resistance value of the resistor R81, R82 R _81, R
_{Assuming 82} , Vth = Vr · R ₈₂ / (R ₈₁ + R ₈₂ ).

The comparison circuit 155 calculates the changing resonance voltage Vr.
And the threshold value Vth, and outputs an ON (high level) signal while Vr ≧ Vth (FIG. 28).

Delay circuit 157 delays the output signal from comparison circuit 155 by a predetermined time T81 and outputs it (FIG. 2).
8).

The output signal from delay circuit 157 is delayed by delay circuit 158 for a predetermined time T82 (FIG. 28) and inverted by inverter gate circuit 159 (FIG. 28).

The AND gate circuit 160 generates a pulse signal (FIG. 28) by synthesizing the logical product of these signals, and outputs the pulse signal to the synthesizing circuit 156.

The synthesizing circuit 156 includes the AND gate circuit 16
When a pulse signal is input from 0, an ON signal Son is output to the drive circuit 102, and thereby the transistor Q11
Is turned on (of FIG. 28).

Therefore, as shown in FIG.
off is output in synchronization with the falling point of
This time is a predetermined time T81 after the falling time (when Vr ≦ Vth). Here, T81
Is set so that the ON signal Son is output while Vr <0, zero voltage switching is reliably performed.

As described above, according to the eighth embodiment, the predetermined ratio Vth of the peak value Vrp of the resonance voltage Vr is set as the threshold value,
Since the transistor Q11 is switched from off to on after a lapse of the predetermined time T81 from the point in time when the resonance voltage Vr has become equal to or lower than the threshold value Vth, zero voltage switching can be performed reliably, and an increase in switching loss can be prevented. Can be prevented.

When the magnitude or waveform of the resonance voltage Vr changes due to a change in the operating environment or deterioration over time, the threshold value Vth changes in accordance with the change. Therefore, Vr = 0 due to a change in the operating environment or the like. , The zero voltage switching can be reliably performed.

In the fifth to eighth embodiments, the converter circuit unit 101 is described using the boost converter of the full-waveform zero-voltage switching method. Needless to say, this can also be applied.

[0173]

As described above, according to the present invention,
By detecting the electric signal of the circuit and controlling the on timing of the switching means based on the detected electric signal, the switching means is switched from off to on when no voltage is applied to the switching means. Therefore, zero-voltage switching can be reliably performed, and an increase in switching loss can be prevented.

In the step-down converter circuit, a time during which the resonance voltage is applied to the switching means is calculated based on the input voltage and the output current, and the switching is performed when the calculated time elapses from the time when the switching means is turned on. By switching from off to on,
Even when the time during which the resonance voltage is applied to the switching means changes due to a change in the input voltage or the output current,
Zero voltage switching can be performed reliably, and an increase in switching loss can be prevented.

The drive control means includes storage means in which the inductance of the resonance reactor, the capacitance of the resonance capacitor, and the cycle of the resonance voltage generated in the resonance capacitor are stored in advance, based on the following equation. By calculating the time, the time during which the resonance voltage is applied to the switching means can be calculated accurately and easily. To = Tn · (1 + Vin / (Zn · Iot)) / 2 Zn = √ (Lr / Cr) where To: time during which the resonance voltage is applied Tn: period of the resonance voltage generated in the resonance capacitor Zn: Characteristic impedance of resonance circuit Iot: output current Vin: input voltage Lr: inductance of resonance reactor Cr: capacitance of resonance capacitor.

Also, in the boost converter circuit, a time during which the resonance voltage is applied to the switching means is calculated based on the output voltage and the input current, and the switching is performed when the calculated time elapses from the time when the switching means is turned off. By switching from off to on,
Even when the time during which the resonance voltage is applied to the switching means changes due to a change in the output voltage or the input current,
Zero voltage switching can be performed reliably, and an increase in switching loss can be prevented.

The drive control means includes storage means in which the inductance of the resonance reactor, the capacitance of the resonance capacitor, and the cycle of the resonance voltage generated in the resonance capacitor are stored in advance. By calculating the time, it is possible to accurately and easily calculate the time during which the resonance voltage is applied to the switching means. To = Tn · (1 + Vot / (Zn · Iin)) / 2 Zn = √ (Lr / Cr) where To: time during which the resonance voltage is applied Tn: period of the resonance voltage generated in the resonance capacitor Zn: Characteristic impedance of resonance circuit Iin: input current Vot: output voltage Lr: inductance of resonance reactor Cr: capacitance of resonance capacitor.

The detecting means detects a resonance voltage generated in the resonance capacitor as the electric signal. The drive control means uses the detected resonance voltage to supply a resonance voltage to the switching means. At the time when the voltage is no longer applied, and when the obtained time is reached, if the switching means is switched from off to on, the parameters of the reactors and capacitors constituting the resonance circuit change due to changes in the operating environment and deterioration over time. Therefore, even when the peak value or waveform of the resonance voltage changes, and therefore the time during which the resonance voltage is applied to the switching means changes, zero voltage switching can be reliably performed, thereby preventing an increase in switching loss. Can be.

The drive control means may switch the switching means from off to on after a predetermined time from the time when the resonance voltage decreases to a predetermined value or less. Is changed, zero voltage switching can be reliably performed, and an increase in switching loss can be prevented.

In this case, if the predetermined value is a predetermined constant value, a circuit can be realized with a simple configuration. On the other hand, if the predetermined value is a voltage value of the resonance voltage after a predetermined time from the time when the switching unit is turned off, or if the predetermined value is set according to a peak value of the resonance voltage, the predetermined value is Since it is not a constant value but a value reflecting the change in resonance voltage,
Zero voltage switching can be performed more reliably in response to changes in the operating environment and the like.

[Brief description of the drawings]

FIG. 1 shows a first example of a DC-DC converter circuit according to the present invention.
It is a circuit block diagram showing an embodiment.

FIGS. 2A, 2B, and 2C are waveform diagrams of a resonance voltage generated in a resonance capacitor.

FIG. 3 shows a second example of the DC-DC converter circuit according to the present invention.
It is a circuit block diagram showing an embodiment.

FIG. 4 is a waveform chart of a resonance voltage and a timing chart showing ON / OFF of a transistor.

FIG. 5 is a circuit block diagram illustrating a more specific circuit configuration example of the second embodiment.

FIG. 6 is a timing chart showing signals of respective parts of FIG. 5;

FIG. 7 shows a third example of the DC-DC converter circuit according to the present invention.
It is a circuit block diagram showing an embodiment.

FIG. 8 is a waveform chart of a resonance voltage and a timing chart showing ON / OFF of a transistor.

FIG. 9 is a circuit block diagram showing a more specific circuit configuration example of the third embodiment.

FIG. 10 is a timing chart showing signals of each part to ′ of FIG. 9;

FIG. 11 is a circuit block diagram showing a fourth embodiment of the DC-DC converter circuit according to the present invention.

FIG. 12 is a waveform chart of a resonance voltage and a timing chart showing ON / OFF of a transistor.

FIG. 13 is a circuit block diagram showing a more specific circuit configuration example of the fourth embodiment.

FIG. 14 is a timing chart showing signals of the respective parts of FIG. 13;

FIG. 15 is a circuit block diagram showing a fifth embodiment of the DC-DC converter circuit according to the present invention.

FIGS. 16 (a), (b) and (c) are waveform diagrams of a resonance voltage generated in a resonance capacitor.

FIG. 17 is a circuit block diagram showing a sixth embodiment of the DC-DC converter circuit according to the present invention.

FIG. 18 is a waveform chart of a resonance voltage and a timing chart showing ON / OFF of a transistor.

FIG. 19 is a circuit block diagram illustrating a more specific circuit configuration example of the sixth embodiment.

FIG. 20 is a timing chart showing signals of the respective parts of FIG. 19;

FIG. 21 is a circuit block diagram showing a seventh embodiment of the DC-DC converter circuit according to the present invention.

FIG. 22 is a waveform chart of a resonance voltage and a timing chart showing ON / OFF of a transistor.

FIG. 23 is a circuit block diagram illustrating a more specific circuit configuration example of the seventh embodiment.

FIG. 24 is a timing chart showing signals of respective parts to ′ of FIG. 23;

FIG. 25 is a circuit block diagram showing an eighth embodiment of the DC-DC converter circuit according to the present invention.

FIG. 26 is a waveform chart of a resonance voltage and a timing chart showing ON / OFF of a transistor.

FIG. 27 is a circuit block diagram showing a more specific circuit configuration example of the eighth embodiment.

FIG. 28 is a timing chart showing signals of respective sections 1 to 3 of FIG. 27;

FIG. 29 is a timing chart illustrating an operation of a zero-voltage switching type DC-DC converter circuit.

[Explanation of symbols]

1,101 converter circuit section 2,102 drive circuit (drive means) 3,103 control circuit (detection means, drive control means, storage means) Q1, Q11 transistors (switching means) L1, L11 resonance reactor C1, C11 resonance Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor ▲ Taka ▼ Mitsuaki Saka 1-7-10 Kikuzumi, Minami-ku, Nagoya-shi, Aichi Auto Network Engineering Laboratory Co., Ltd. (72) Inventor Chen Noboru, Minami-ku, Nagoya-shi, Aichi 1-7-10 Kikuzumi, within the Auto Network Engineering Laboratory Co., Ltd. (72) Inventor Isao Isshiki 1-7-10, Kikuzumi, Minami-ku, Nagoya City, Aichi Prefecture Inside the Auto Network Technology Laboratory Co., Ltd. (72) Inventor Toshiro Shimada Aichi 1-7-10 Kikuzumi, Minami-ku, Nagoya-shi F-term in Auto Network Engineering Laboratory Co., Ltd. (Reference) 5H730 AA02 AA14 BB13 BB14 BB57 BB61 DD02 DD32 DD41 FD01 FD26 FD31 FF09 FG03 FG07

Claims (10)

[Claims] 1. A switching means for turning on and off an input voltage, a resonance circuit including a resonance reactor connected to the switching means and a resonance capacitor resonating with the resonance reactor, and a driving means for turning on and off the switching means. Switching type D with
A C-DC converter circuit, comprising: detection means for detecting an electric signal of the circuit; and drive control means for controlling the operation of the drive means. The drive control means has a resonance voltage applied to the switching means. A DC-DC converter circuit for controlling the ON timing of the switching means based on the detected electric signal so as to switch the switching means from OFF to ON when there is no signal. 2. The DC-DC converter circuit according to claim 1, wherein said circuit is a step-down converter circuit for stepping down an input voltage and outputting said stepped-down voltage, and said detecting means detects an input voltage and an output current as said electric signal. To detect,
The drive control means calculates a time during which a resonance voltage is applied to the switching means based on the detected input voltage and the detected output current, and calculates the time when the calculated time elapses from the time when the switching means is turned off. A DC-DC converter circuit for switching a switching unit from off to on. 3. The DC-DC converter circuit according to claim 2, wherein the drive control means determines in advance that the inductance of the resonance reactor, the capacitance of the resonance capacitor, and the cycle of the resonance voltage generated in the resonance capacitor are predetermined. DC having storage means for storing the data and calculating the time based on the following equation:
A DC converter circuit. To = Tn · (1 + Vin / (Zn · Iot)) / 2 Zn = √ (Lr / Cr) where To: time during which the resonance voltage is applied Tn: period of the resonance voltage generated in the resonance capacitor Zn: Characteristic impedance of resonance circuit Iot: output current Vin: input voltage Lr: inductance of resonance reactor Cr: capacitance of resonance capacitor. 4. The DC-DC converter circuit according to claim 1, wherein said circuit is a boost converter circuit which boosts an input voltage and outputs the boosted input voltage, and wherein said detecting means detects an output voltage and an input current as said electric signal. To detect,
The drive control means calculates a time during which a resonance voltage is applied to the switching means based on the detected output voltage and the input current, and when the calculated time elapses from an off time of the switching means, A DC-DC converter circuit for switching a switching unit from off to on. 5. The DC-DC converter circuit according to claim 4, wherein the drive control means determines in advance that the inductance of the resonance reactor, the capacitance of the resonance capacitor, and the period of the resonance voltage generated in the resonance capacitor are predetermined. DC having storage means for storing the data and calculating the time based on the following equation:
A DC converter circuit. To = Tn · (1 + Vot / (Zn · Iin)) / 2 Zn = √ (Lr / Cr) where To: time during which the resonance voltage is applied Tn: period of the resonance voltage generated in the resonance capacitor Zn: Characteristic impedance of resonance circuit Iin: input current Vot: output voltage Lr: inductance of resonance reactor Cr: capacitance of resonance capacitor. 6. The DC-DC converter circuit according to claim 1, wherein the detection means detects a resonance voltage generated in the resonance capacitor as the electric signal, and the drive control means detects the resonance voltage. A DC-DC converter circuit, wherein a point in time at which no resonance voltage is applied to the switching means is determined using the resonance voltage, and the switching means is switched from off to on at the determined time. 7. The DC-DC converter circuit according to claim 6, wherein the drive control means switches the switching means from off to on after a predetermined time from when the resonance voltage decreases to a predetermined value or less. And a DC-DC converter circuit. 8. The DC-DC converter circuit according to claim 7, wherein the predetermined value is a predetermined constant value. 9. The DC-DC converter circuit according to claim 7, wherein said predetermined value is a voltage value of said resonance voltage after a predetermined time from a time point when said switching means is turned off. circuit. 10. The DC-DC converter circuit according to claim 7, wherein the predetermined value is set according to a peak value of the resonance voltage.
DC converter circuit.