KR102335422B1 - Power circuit - Google Patents

Abstract

The present invention discloses a power supply circuit for digitally controlling power conversion and compensating for a change in input voltage, wherein the power circuit includes a control unit, wherein the control unit turns off the switching element after the switching element is turned off The on-time of the switching element is controlled by detecting the base point of the resonance period of the voltage, and when the switching element is turned on, the level change of the input voltage is measured using the difference between the clamping level of the sensing voltage of the power conversion circuit and the input voltage. It detects and generates an input compensation signal.

Description

power circuit {POWER CIRCUIT}

The present invention relates to a power supply circuit, and more particularly, to a power supply circuit that digitally controls power conversion and compensates for changes in input voltage.

A power circuit is provided in various devices such as an audio device, a display device, a notebook computer, and a white home appliance, and the power circuit may be implemented in a flyback converting method to convert DC power or AC power.

The power supply circuit of the flyback conversion method may include a power conversion circuit including a transformer and a switching element for driving the primary side of the transformer. The switching element performs a switching operation of driving the primary side of the transformer using a driving pulse, and the transformer is configured to convert power from the primary side to the secondary side in response to the switching operation of the switching element.

Power conversion in the power circuit is accompanied by power loss. Therefore, the power circuit should be designed to minimize power loss occurring in power conversion.

Power loss in power circuits can occur for a variety of reasons.

First, when the switching element operates to have a fixed on-time regardless of load variation, excessive power may be supplied in response to a small load. Accordingly, power loss may occur unnecessarily. In order to solve this problem, the on-time of the switching element should be controlled in response to a change in the load.

In addition, a switching loss occurs in the switching element during power conversion. The above-described switching loss is generated by a difference in voltage applied to the switching element in the turned-on state and the turned-off state.

As described above, power loss may occur in the power circuit from various viewpoints, and there is a need to design the power circuit to minimize the power loss.

In addition, the power circuit can be used in a variety of voltage environments. That is, various commercial voltages such as 110V or 220V may be used depending on delay or country. The power circuit needs to have a compensation function applied to the input voltage change so that it can operate normally even with the input phone change.

It is an object of the present invention to control the driving of a switching element in response to feedback of an output voltage by using a digital signal processing block with a driving signal for a switching operation for power conversion, and an audio device, a display device, a notebook computer, and a white home appliance It is to provide a power circuit that can be applied to various devices such as

Another object of the present invention is to provide a power supply circuit capable of reducing power loss due to factors such as load variation and switching loss of a switching element.

Another object of the present invention is to provide a power supply circuit capable of performing a compensating operation in response to a change in an input telephone.

Another object of the present invention is to provide a power supply circuit in which a layout margin of a package can be secured by using an analog-to-digital converter having a reduced number of bits and advantageous in terms of chip size.

Another object of the present invention is to provide a power supply circuit capable of providing a driving signal GD having a stable on-time (ton) by accurately sensing a feedback signal.

The power circuit for performing power conversion in the power conversion circuit by driving the switching element of the present invention detects the base point of the resonance period of the turn-off voltage of the switching element after the switching element is turned off to turn on the switching element controlling a timing, and when the switching element is turned on, a level change of the input voltage is sensed using a difference between a clamping level of a sensing voltage of the power conversion circuit and an input voltage to generate an input compensation signal, and the input compensation signal It characterized in that it includes; a control unit for performing the input compensation using.

In addition, the power supply circuit for performing power conversion in the power conversion circuit by driving the switching element of the present invention controls the generation of a driving signal provided for driving the switching element, and the driving signals included in the driving signal The switching element is switched by the , and after the switching element is turned off, a base point of a resonance period of a turn-off voltage of the switching element is detected to control an on time of the switching element, and to respond to a feedback signal corresponding to a load a digital signal processing block receiving a digital code to control an on-time of the driving pulse; and an analog-to-digital converter that senses the feedback signal and provides the digital code, wherein the digital signal processing block recognizes the range of the digital code provided from the analog-to-digital converter as two or more divided sections, and each section The driving pulse is controlled by applying a change in on time corresponding to 1 bit of the digital code.

In addition, the power supply circuit for performing power conversion in the power conversion circuit by driving the switching element of the present invention, controls the generation of a driving signal provided for driving the switching element, the driving signals included in the driving signal The switching element is switched by the , and after the switching element is turned off, a base point of a resonance period of a turn-off voltage of the switching element is detected to control an on time of the switching element, and to respond to a feedback signal corresponding to a load a digital signal processing block receiving a digital code to control an on-time of the driving pulse; and the feedback signal senses the feedback signal by sampling a feedback voltage provided in response to the load after a blank time set from a turn-off time of the switching element to a predetermined time elapses, and the feedback signal corresponding to the feedback signal It is characterized in that it includes an analog-to-digital converter that provides a digital code.

According to the present invention, it is possible to provide a power supply circuit applicable to various devices such as an audio device, a display device, a notebook computer, and a white home appliance.

In addition, according to the present invention, there is an effect of reducing power loss due to various factors such as load variation and switching loss of the switching element.

In addition, according to the present invention, it is possible to provide a power supply circuit capable of stably performing power conversion because compensation can be performed even when an input voltage is changed.

In addition, according to the present invention, the maximum on-time can be ensured by using the analog-to-digital converter having the reduced number of bits, and as a result, a layout margin necessary for mounting the analog-to-digital converter on the package can be secured, and the package can reduce the chip size. It can be advantageously implemented in the aspect.

In addition, according to the present invention, the analog-to-digital converter can sample the feedback voltage in a stable state and accurately sense the feedback signal using the blank time. Therefore, the present invention can provide a driving signal GD having a stable on-time (ton).

1 is a block diagram showing an embodiment of a power supply circuit of the present invention;
Figure 2 is a detailed block diagram of the control unit of Figure 1;
3 is a circuit diagram illustrating an operation corresponding to turn-on of a switching element;
Fig. 4 is a waveform diagram corresponding to the operation of the switching element of Fig. 3;
5 is a circuit diagram for explaining an operation corresponding to turn-off of a switching element;
Fig. 6 is a waveform diagram corresponding to the operation of the switching element of Fig. 5;
7 is a waveform diagram for explaining an ON time change according to a resonance period;
8 is a detailed circuit diagram of the input compensation circuit of FIG.
Fig. 9 is a waveform diagram for explaining the operation of Fig. 8;
10 is a graph for explaining a method for improving the number of bits of an analog-to-digital converter.
11 is a waveform diagram illustrating a method of controlling sensing of a feedback signal by applying a blank time;
12 is a waveform diagram illustrating another method of controlling sensing of a feedback signal by applying a blank time;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The terms used in the present specification and claims are not limited to a conventional or dictionary meaning, and should be interpreted in a meaning and concept consistent with the technical matters of the present invention.

The embodiments described in this specification and the configurations shown in the drawings are preferred embodiments of the present invention, and do not represent all of the technical spirit of the present invention, so various equivalents and modifications that can replace them at the time of the present application there may be

Referring to FIG. 1 , the power circuit includes a power supply unit 10 , a start-up circuit 12 , a power conversion circuit 14 , a switching element Q, an output circuit 16 , a feedback circuit 18 , and a control unit 20 . ) and a zero current sensing circuit 22 . In FIG. 1 , RL is a load, D is a diode for blocking the flow of counter electromotive current, C is a capacitor for charging the operating voltage applied to the control unit 20 , and R is a resistance.

The power circuit of the present invention implemented as shown in FIG. 1 may be implemented to be applied to various devices such as an audio device, a display device, a notebook computer, and a white home appliance. For example, when applied to an audio device, the controller 20 may be configured as one package. And, when applied to a display device, the control unit 20 and the start-up circuit 12 may be included in one package. And, when applied to a notebook computer and white goods, the control unit 20, the start-up circuit 12, and the switching element Q may be included in one package.

A configuration and operation of each component configured in the embodiment of FIG. 1 will be described.

The power supply unit 10 may provide AC power or DC power, and for the purpose of the present invention, the power supply unit 10 is defined as providing an _{input voltage VIN and an input current i VIN.}

The start-up circuit 12 provides an operating voltage Vcc for the operation of the control unit 20 by using the input voltage VIN of the power supply unit 10 in response to a section in which the power conversion circuit 14 does not provide the operating voltage Vcc. it is to do

The power conversion circuit 14 converts the input voltage VIN and may include a transformer for this purpose. The input voltage VIN may be an AC voltage or a DC voltage, but for the description of the embodiment, it is exemplified as an AC voltage.

The transformer includes a plurality of coils for inducing a current corresponding to the voltage change, a number of coils may be divided into a primary side _(P N) and the outlet _(S N) and secondary coil (N _A). The LM shown in the electric power conversion circuit 14 is a representation of the inductance component of the primary winding (N _P) equivalently, hereinafter referred to as the inductor (LM). An inductor voltage V _LM and an inductor current i _M may be applied to the inductor LM. In order to distinguish it from _{the input-side current i VIN} corresponding to the input voltage VIN of the power conversion circuit 14, the _{inductor current i M} of the inductor LM is described as the _{primary-side (NP} ) current of the transformer, that is, the power conversion circuit 14 may be. transformer performs power conversion in accordance with the turns ratio of the primary winding (N _P) and the secondary side (N _S). Then, the secondary coil (N _A) of the transformer is sensed according to a change in the current primary _(P N) to the turns ratio.

The switching element Q _{has a drain connected to the primary side N P} of the transformer and may be formed of a high voltage NMOS transistor using a field effect transistor (FET). The source of the switching element Q is connected to the ground through the resistor R, and the driving signal GD is provided to the gate of the switching element Q.

A switching element (Q) and the switching operation by a drive signal (GD), it can be driving the primary winding (N _P) of the transformer in conjunction with the turn-on and turn-off of the switching device (Q). The driving signal GD may be provided as a pulse waveform in which a high level and a low level are periodically repeated. The switching element Q is turned on by the high-level driving signal GD, and in this case, the voltage Vds between the drain and the source of the switching element Q may be defined as the turn-on voltage. The turn-on voltage may be defined as “0 V” in the embodiment, and the switching element Q is turned off by the low-level driving signal GD, and at this time, the voltage Vds between the drain and the source of the switching element Q may be defined as a turn-off voltage The turn-off voltage may be defined as a value obtained by adding an _{input voltage VIN and a voltage transferred to the primary side N P} by a turn ratio of the voltage of the _{secondary side N S .}

The turn-off voltage of the switching element Q resonates after the point in time when the _{primary side (NP) current of the transformer of the power conversion circuit 14 becomes 0 (Zero).} At this time, the resonance occurs due to the difference between the input voltage VIN and the voltage Vds between the drain and the source applied to the switching element Q, and corresponds to the LC resonance caused by the parasitic capacitor between the inductor LM and the drain-source of the switching element. The resonator is an input voltage VIN and the secondary side (N _S) voltage is a first value obtained by adding the voltage delivered to the primary winding (N _P) by the turns ratio (VIN + (Np / Ns) Vo) and the input voltage VIN and the secondary side of a a second value (VIN- (Np / Ns) Vo ) of the convergence caused by the car and having a resonant period the input voltage VIN of the voltage (N _S), minus the voltage that is delivered to the primary winding (N _P) by the turns ratio do.

In addition, the sensing signal CS may be output from a node between the source of the switching element Q and the resistor R, and it may be understood that the sensing signal CS has a value corresponding to a voltage applied to the resistor R. .

On the other hand, the power conversion and a secondary side (N _S), the output circuit 16 to the transformer of the circuit 14 is configured, the output circuit 16 forwards the voltage of the secondary side of the transformer (N _S) to the load (RL) do. To this end, the output circuit 16 includes a diode Do and a capacitor Co, and the current passing through the diode Do _{may be defined as a diode current i D} , and the load by charging and discharging the capacitor Co The current provided by (RL) may be defined as the output current (io). The diode current i _D corresponds to the secondary-side current of the power conversion circuit 14 , that is, the transformer.

The feedback circuit 18 generates a feedback signal FB corresponding to the state of the load RL and transmits the feedback signal FB to the control unit 20 . The feedback circuit 18 may generate the feedback signal FB by detecting the output voltage Vo or the output current io provided to the load. The feedback circuit 18 may be variously configured according to the intention of the manufacturer, and may be typically configured using a photo coupler.

On the other hand, a zero current detection circuit 22 is configured to sense the sensed voltage V _A that is output from the secondary coil (N _A) of the transformer of the power conversion circuit 14.

Sensing the voltage V _A is the primary side of the point that is the transformer kept at the high level, while the secondary side (N _S) current of a transformer flows and the secondary side of the transformer (N _S) current of the diode current i _D is to be zero (Zero) ( When _{the current of N P} ) becomes zero, the level starts to drop, and theoretically, the level may drop along the resonance of the turn-off voltage of the switching element Q. Sensing the voltage V _A has to detect the zero current point, the current of the secondary side (N _S) to the diode current i _D is zero (Zero) is the time that is the primary side (N _P) of the transformer is a transformer that is zero (Zero) It can be used as a zero current sensing signal for

A zero current detection circuit 22 is configured to provide a sense signal V _BD delayed by a predetermined time from the zero-current point in time for sensing the voltage V _A will start to fall from the high level to the control unit 20. The zero current sensing circuit 22 may include elements having capacitance and resistance for delay.

The resonance period of the turn-off voltage of the switching element Q may be known in advance by a test. Therefore, the zero current sensing circuit 22 may be configured to have a preset delay time for the turn-off voltage of the switching element Q to coincide with the base point of the resonance period when the _{sensing signal V BD reaches the low level.} have.

Meanwhile, the controller 20 may include a digital signal processing block 210 , a gate driver 220 , an oscillator 230 , an analog-to-digital converter (ADC: 240 ), and an input compensation circuit 250 as shown in FIG. 2 . . The gate driver 220 generates and outputs a driving signal GD corresponding to the pulse signal PWM provided from the digital signal processing block 210 . The analog-to-digital converter 240 receives the feedback signal FB and provides a digital code corresponding to the feedback signal to the digital signal processing block 210 . The oscillator 230 may provide pulse signals of different frequencies required for the operation of the digital signal processing block 210 and the analog-to-digital converter 240 . And, the input compensation circuit 230 receives the output of the power conversion circuit. _A level change of the input voltage VIN is sensed using a difference between the clamping level of the sensed sensing voltage V A and the input voltage VIN to generate an input compensation signal. Here, the input compensation circuit 230 may utilize a sensing signal V _BD of the zero current detection circuit 22 to determine a clamping level of the sensing voltage V _A. That is, the input compensation circuit 230 may be configured to detect a level change of the input voltage VIN using a difference between the clamping level _{of the detection signal V BD and the input voltage VIN.}

The digital signal processing block 210 controls generation and output of the driving signal GD of the gate driver 220 in response to the sensing signal CS, the sensing signal V _{BD, and the feedback signal FB.}

The control unit 20 is operated by the operating voltage VCC provided from the start-up circuit 12 at the initial stage when the input voltage VIN is applied, that is, before the power conversion circuit 14 is driven, and the power conversion circuit 14 is driven. after it is operated by using a sensing voltage V _a supplied from the secondary coil (N _a) as an operating voltage VCC.

The operation of controlling the driving signal GD in response to the sensing signal CS, the sensing signal V _BD, and the feedback signal FB is performed by the digital signal processing block 210 . However, for convenience of description, the present invention describes that the control operation of the digital signal processing block 210 is performed by the controller 20 .

When the load RL is kept constant, the controller 20 may perform an operation of controlling the generation and output of the driving signal GD so that the output current io may be kept constant in response to the sensing signal CS.

And, the control unit 20 is the switching element (Q) corresponding to the base point of the resonance period of the turn-off voltage of the switching element (Q) after the zero current point of the _{primary side (NP) current of the power conversion circuit 14} The ON time is determined, and the ON time of the switching element Q is changed in units of a resonance period in response to a change in the load RL, and is gradually changed within one resonance period, and the driving signal GD to which the ON time is applied is switched. element (Q)).

The control unit 20 of the switching element (Q) to correspond to the base point of the resonance period of the turn-off voltage of the switching element (Q) resonant after the zero current point of the _{primary side (NP) current of the power conversion circuit 14 The sensing signal V BD} of the zero current sensing circuit 22 is used to determine the on time point.

In addition, the controller 20 uses the feedback signal FB to change the on-time so that the on-time of the switching element Q can be increased or decreased according to a change in the load RL.

An operation of the power circuit configured as in FIGS. 1 and 2 will be described. First, with reference to FIGS. 3 and 4 , the operation of the power circuit in a state in which the switching element Q is turned on will be described, and with reference to FIGS. 5 and 6 , the power supply in a state in which the switching element Q is turned off The operation of the circuit will be described.

3 and 4 , when the driving signal GD is provided at a high level, the switching element Q is turned on. The switching element Q may equivalently have a diode function to block the flow of the counter electromotive force, and the voltage Vds between the drain and the source, that is, the turn-on voltage, may be formed to be low.

After the switching element Q is turned on, the input current i _VIN gradually increases. The input current i _VIN flows through the inductor LM and the switching element Q of the power conversion circuit 14, and after the switching element Q is turned on, the inductor voltage V _LM is maintained at the input voltage VIN level, and the inductor The current i _M follows the increase of the input current i _{VIN .}

In this case, the output circuit 16 may discharge the energy accumulated in the capacitor Co to the load RL in response to the driving signal GD being turned off in the previous cycle. Therefore, the output voltage Vo decreases.

Further, the secondary side from the primary side of the power conversion circuit _{(14) (N P) (} N S) to the energy transfer is not performed. Therefore, the diode current i _D does not flow, and the sensing voltage V _A and the sensing signal V _BD are not formed.

Thereafter, when the driving signal GD is provided at a low level, the switching element Q is turned off. The operation of the power circuit will be described with reference to FIGS. 5 and 6 .

When the switching element Q is turned off, it _{does not provide a path for the flow of the input current i VIN} and the drain-source voltage Vds, that is, the turn-off voltage is formed to be high. In one example, the turn-off voltage can be defined as the "winding ratio of the input voltage (VIN) +1 winding (N _P) and the secondary side _{(N S) (N P /} N S) * Output voltage Vo". That is, the input current i _VIN does not flow, and the inductor voltage V _LM may be low. In one example, the inductor voltage V _LM can be defined as the "primary-side turn ratio (N _P / N _S) of (N _P) and the outlet _(S N) * Output voltage Vo". In addition, the turn-off voltage may have a transient characteristic when the switching element Q is turned on.

When the switching device (Q) is turned off by the energy stored in the inductor (LM), generated in the closed loop for the inductor current i _M includes a primary side (N _P) of the inductor (LM) and the power conversion circuit 14 do. The flow of the diode current i _{D in the secondary side N S} of the current conversion circuit 14 is initiated by induced in the primary side (N _{P ) current flow.} The amount of diode current i _{D follows} the amount by which the inductor current i _M is reduced.

At this time, the output circuit 16 transfers _{the energy by the diode current i D} to the load RL while charging the capacitor Co. Therefore, the output voltage Vo increases.

The flow of the diode current i _D of the power conversion circuit 14 may be sensed in the _{auxiliary coil N A .} A secondary coil (N _A) is a sensing voltage V _A for outputting a high level, a zero current detection circuit 22 is also detected in a high level corresponding to the sensing voltage V _A signal V _BD corresponding to the flow of diode current i _D Output at high level. In one example, a high level sensing voltage V _A and the high level of the sense signal V _BD is to be defined as the "winding ratio of the secondary winding (N _A) and the secondary side _{(N S) (N A /} N S) * Output voltage Vo" can Then, the detection signal V _BD of the low level sensing voltage V _A and the low level of the theoretically defined as the "winding ratio (N _A / N _P) * input voltage VIN of the secondary winding (N _A) and the primary winding (N _P)." can be and can have a negative value. However, in practice, the sensing voltage V _A and the low-level sensing signal V _BD may be theoretically set to maintain a substantially “0” level with respect to a case having a negative value.

When the turn-off state of the switching device (Q) maintained as described above, the diode current i _D of the secondary winding _(S N) of the power conversion circuit 14 is a 0 (Zero). At this time, the _{inductor current i M that is the primary side (NP} ) current of the power conversion circuit 14 also becomes 0 (Zero).

In the turn-off state, the voltage Vds between the drain and the source of the switching element Q, that is, the turn-off voltage is formed to be high. When the switching element Q is turned on in this state, a large difference in the voltage Vds between the drain and the source, that is, the difference between the turn-off voltage and the turn-on voltage, may cause a lot of switching loss in the switching element Q, and as a result, a lot of power loss can occur

In order to reduce the above-described power loss, in the present invention, the on-time of the switching element Q can be adjusted by the digital control of the digital signal processing block 210 . The switching element Q may be controlled to be turned on at a point in time when the difference between the turn-off voltage and the turn-on voltage is the lowest.

As described above, the zero current sensing circuit 22 is the primary side ( _NP ) current of the power conversion circuit 14, the inductor current i _M after the zero current point of time when 0 (Zero) the turn of the switching element (Q) _A delay operation corresponding to the sensing voltage V _{A is performed so that the sensing signal V BD} reaches a low level when the off voltage coincides with the base point of the resonance period. The voltage of the base point of the resonance cycle may be defined as the "winding ratio of the input voltage VIN-1 side _(P N) and the secondary side _{(N S) (N P /} N S) * Output voltage Vo".

That is, the switching element Q may be turned on at the base point of the resonance period with the lowest difference between the turn-off voltage and the turn-on voltage. As a result, the switching loss of the switching element Q may be minimized, and power loss by the switching element Q may be reduced.

4 and 6, the inductor current i _{M, which is the primary side (NP} ) current of the power conversion circuit 14, becomes 0 (Zero), that is, the zero current time point is described as T1, and the zero current sensing circuit 22 ) at which the sensing signal V _BD outputted from the low level reaches the low level is referred to as T2. In contrast to these, when the sensing voltage V _A reaches the low level, the time when the sensing signal V _BD reaches the low level is delayed, and the time when the sensing signal V _BD reaches the low level is the time of the switching element Q. It can be understood that the turn-off voltage coincides with the base point of the resonance period.

As described above, the control unit 20 uses the sensing signal V _BD output from the zero current sensing circuit 22 to resonate the switching element Q after the zero current time point T1 of the output side of the power conversion circuit 14 . The on-time of the switching element Q may be determined to correspond to the base point of the resonance period of the turn-off voltage of , and the driving signal GD to which the on-time is applied may be provided to the switching element Q.

In addition, the control unit 20 performs counting, and sets a time point coincident with a predetermined value such that the count value is set to correspond to the base point of a desired resonance period among the resonance periods of the turn-off voltage of the switching element Q. It is determined as the ON time of Q, and the ON time of the switching element Q is changed in units of a resonance period in response to a change in the load RL, and the driving signal GD is changed gradually within one resonance period of the switching element (Q) can be provided.

In more detail, the operation of the control unit 20 will be described with reference to FIG. 7 .

The control unit 20 performs counting and can know how many times resonance has been achieved by using the counting. The control unit 20 may count using the resonance period pulse generated at the base point of the resonance period, and determines whether the count value matches a predetermined value.

The controller 20 generates a resonance cycle pulse BD synchronized with a timing corresponding to the base of each resonance cycle with reference to a time point T2 when the _{detection signal V BD reaches the low level.} When the count value and the predetermined value match, the control unit 20 determines the on time point by determining that the turn-off voltage of the switching element Q corresponds to the base point of the desired resonance period among the resonance periods.

The control unit 20 may receive the feedback signal FB corresponding to the load state of the output side of the power conversion circuit 14 and detect a change in the load by using the feedback signal FB.

When a change in load is sensed using the feedback signal FB, the controller 20 may change the on-time so that the on-time of the switching element Q can be increased or decreased in response to an increase or a decrease in the load.

The controller 20 may change the on time in units of the resonance period in response to a change in the load, for example, such that the on time of the switching element Q is gradually decreased between the third and fourth resonance periods as shown in FIG. 7 . can be configured.

The controller 20 may set an enable section including one or more resonance periods in response to a change in load, and the embodiment of FIG. 7 exemplifies the enable section between the third resonance period and the fourth resonance period.

The control unit 20 may sequentially generate a plurality of transition control signals BDS1 to BDSn that are sequentially shifted during the enable section in response to the resonance cycle pulse BD of the third cycle, and the control unit 20 controls each of the transition control signals BDS1 to BDSn In response to BDSn, the driving signal GD having a sequentially on-time change from the base of the third resonance period to the base of the fourth resonance period may be provided.

As described above, when the driving signal GD of which the on-time is changed is provided to the switching element Q, the switching element Q may provide a driving signal of which the on-time is changed in response to a change in load. As a result, when the load is reduced, the power conversion circuit 14 may be driven by the driving signal GD having a reduced on-time.

As described above, the controller 20 may change the on-time so that the on-time of the driving signal GD is increased or decreased. If the controller 20 is implemented as an analog circuit, it may not be easy to design to reduce the on time. However, the controller 20 implemented in the present invention uses a digital signal processing block. Therefore, the controller 20 implemented in the present invention can easily implement increasing or decreasing the on-time of the driving signal GD by using a digital operation.

As described above, the control unit 20 of the present invention controls the on-time of the switching element Q by detecting the base point of the resonance period of the turn-off voltage of the switching element Q after the switching element Q is turned off as described above. can

On the other hand, Figure 8 and as shown in Figure 9, the control unit 20 the clamping level and the inputs of the sensing voltage V _A of the electric power conversion circuit 14 by the switching device input compensation circuit 250, when (Q) is turned on according to the present invention A level change of the input voltage VIN may be sensed using the difference in voltage VIN, an input compensation signal INPUT_COMP may be generated using the detected result, and input compensation may be performed using the input compensation signal INPUT_COMP.

8, the input compensation circuit 250 senses the voltage V _A is using the detection signal V _BD delayed by a predetermined time from the zero-current point in time to start to fall from a high level to determine a clamping level of the sensing voltage V _A It can be implemented as configured.

The input voltage VIN may be assumed to change to a high level (first level) or a low level (second level), and the high level may be illustrated as 220V, and the low level may be illustrated as 110V.

In addition, although not specifically shown, the digital signal processing block 210 of the control unit 20 performs input compensation including adjustment of an overcurrent detection signal sensing the current flowing through the switching element Q using the above-described input compensation signal INPUT_COMP. can be done

The input compensation circuit 250 of FIG. 8 may include an input detection circuit 300 and an input compensation logic unit 320 .

_{Here, the input detection circuit 300 calculates the difference between the clamping level of the detection signal V BD} corresponding to the sensed power conversion of the power conversion circuit 14 and the input voltage VIN and a reference voltage that varies depending on the level of the input voltage VIN. It can be configured to output the compensation sensing signal INCOMP by applying it.

Then, the input compensation logic unit 320 receives and counts the compensation sensing signal INCOMP in units of the cycle of the driving signal GD, and when it is counted that the compensation sensing signal INCOMP maintains the same state by a predetermined number or more, the level of the input voltage VIN is It may be configured to provide an input compensation signal INPUT_COMP that determines that it has changed.

Among them, the input detection circuit 300 may include a clamping circuit 400 , a current mirror circuit 420 , and an output unit 440 .

First, the clamping circuit 400 may be configured to generate _{a first current I BD} corresponding to a difference between the clamping level _{of the sensing signal V BD and the input voltage VIN.} More specifically, the clamping circuit 400 includes an NMOS transistor Qc to which a constant current source is applied to a gate and NON bipolar transistors Qd and Qs having a common base coupled to a source of the NMOS transistor Qc. The clamping circuit 400 generates _{a first current I BD1} corresponding to the level of the _{clamped sensing signal V BD} while the switching element Q is turned on.

And, provided through the current mirror circuit 420 includes PMOS transistors (M1, M2), the PMOS transistor (M2), a second current I _BD2 a base that has a coupling mirrored structure, copying the first current I _BD1 of can do.

The output unit 440 includes _{a resistor R1 through which the second current I BD2} flows to form an input voltage INCOMP_IN and series-connected resistors R2 and R3 through which the constant current source flows. Here, the switch SW is connected in parallel to the resistor R3 , and the switch SW is configured to perform a switching operation according to the switching control signal INCOMP_CTRL provided from the input logic unit 320 .

When the current input voltage VIN is at the low level, the switch SW is turned off by the switching control signal INCOMP_CTRL provided at the low level, and when the current input voltage VIN is at the high level, the switch SW is provided at the high level. It is turned on by the switching control signal INCOMP_CTRL.

In addition, the output unit 440 includes an error amplifier 442 , an input voltage INCOMP_IN to which a resistor R1 is applied is applied to a positive terminal of the error amplifier 442 and a resistor R2 or a series-connected resistor is applied to a negative terminal of the error amplifier 442 . A reference voltage INCOMP_REF applied to (R2, R3) is applied. The error amplifier 442 provides a high level compensation sensing signal INCOMP to the input compensation logic unit 320 when the voltage difference between the positive terminal and the negative terminal is different than a predetermined level.

The output unit 440 configured as described above uses the first reference voltage to detect the high level (first level) input voltage VIN, and compensates for _{the second current I BD2 of the current mirror circuit 420 .} Outputs the sensing signal INCOMP. In this case, the first reference voltage corresponds to the reference voltage INCOMP_REF(H) applied to the series-connected resistors R2 and R3. The output unit 440 uses the second reference voltage to detect the low level (second level) input voltage VIN, and the compensation sensing signal INCOMP corresponding to _{the second current I BD2 of the current mirror circuit 420 .} to output In this case, the second reference voltage corresponds to the reference voltage INCOMP_REF(L) applied to the resistor R2 as the switch SW is turned on.

Therefore, when the input voltage VIN of the high level is input, the level difference between the clamping level of the _{detection signal V BD} and the input voltage VIN is large, so that the amount of _{the first current I BD1 increases, and accordingly, the first current I BD1 provided from the current mirror circuit 420 .} 2 The amount of current I _{BD2 also increases.}

In this case, the high level first reference voltage INCOMP_REF(H) is applied to the negative terminal of the error amplifier 442 .

For example, the error amplifier 442 outputs a high level signal when a voltage sufficiently higher than the first reference voltage INCOMP_REF(H) is applied to the positive terminal.

The detection signal V _BD has a level that is periodically clamped in synchronization with the period of the pulse signal PWM provided to the gate driver 220 in the digital signal processing block 210 . Therefore, when a voltage sufficiently higher than the first reference voltage INCOMP_REF(H) is applied to the positive terminal, the error amplifier 442 may output the compensation sensing signal ICOMP in the form of a periodic pulse.

On the contrary, when the input voltage VIN of the low level is input, the level difference between the clamping level of the _{detection signal V BD} and the input voltage VIN is small, so that the amount of _{the first current I BD1 decreases, and accordingly, the amount of the first current I BD1 is reduced.} The amount of the second current I _{BD2 also decreases.}

At this time, the low level second reference voltage INCOMP_REF(L) is applied to the negative terminal of the error amplifier 442 .

For example, the error amplifier 442 outputs a low-level signal if the input voltage INCOMP_IN applied to the positive terminal is not sufficiently greater than the second reference voltage INCOMP_REF(L).

The input compensation logic unit 320 counts the level change of the compensation sensing signal in synchronization with the cycle of the driving signal GD, that is, the cycle of the pulse signal PWM provided to the gate driver 220 in the digital signal processing block 210 .

The input compensation logic unit 320 determines that the high level input voltage VIN is input when the level of the compensation sensing signal INCOMP maintains a high level while the pulse signal PWM is continuously provided three or more times, and a corresponding input The compensation signal INPUT_COMP is provided to the digital signal processing block 210 .

In addition, the input compensation logic unit 320 determines that the low level input voltage VIN is input when the level of the compensation sensing signal INCOMP maintains a low level while the pulse signal PWM is continuously provided three or more times, and corresponds to the input voltage VIN. provides an input compensation signal INPUT_COMP to the digital signal processing block 210 .

Therefore, the digital signal processing block 210 may perform input compensation such as adjustment of the overcurrent detection signal using the input compensation signal INPUT_COMP.

The number of counts of the input compensation logic unit 320 may be variously modified by a manufacturer.

According to the present invention, a change in the input voltage VIN can be detected by the operation of the above-described input compensation circuit 230, and a compensation operation for the input voltage VIN can be performed in response thereto. Therefore, the power supply circuit can operate stably even in various voltage environments.

On the other hand, the present invention can be configured to secure a sufficient maximum on-time (ton) by using the analog-to-digital converter 240 having a small number of bits by being implemented as shown in FIG. 10 .

The analog-to-digital converter 240 converts the feedback signal FB into a digital code and provides it to the digital signal processing block 210, and the digital signal processing block 210 generates a driving pulse having an on time (ton) corresponding to the digital code. It is possible to control the generation of the driving signal GD to include it.

When the analog-to-digital converter 240 is designed with a small number of bits, a layout margin of a circuit required to be mounted on a package may be secured. Therefore, when the analog digital converter 240 having a small number of bits is mounted, the package may have an advantageous advantage in terms of chip size.

When the analog-to-digital converter 240 implements the same maximum on-time (ton) with a small number of bits, a layout margin of a circuit necessary for mounting in a package can be secured as described above.

In general, when the digital signal processing block 210 is designed to uniformly change the on time (ton) of the driving pulse by 46.5 ns per digital code of the analog-to-digital converter 240, the maximum on time (ton) of 30 μs is implemented To do this, a 10-bit analog-to-digital converter 240 is required.

The digital signal processing block 210 of the embodiment may be exemplified as being designed to implement a maximum on-time (ton) of 30 μs using a 9-bit analog-to-digital converter 240 .

To this end, the digital signal processing block 210 may be configured to recognize as two or more divided sections in response to the digital code of the analog-to-digital converter 240 provided in response to the feedback signal FB. A change in on time (ton) may be applied differently. According to the above configuration, the digital signal processing block 210 may control to generate a driving pulse having a different on time (ton) for each section in response to a digital code change.

10 is a case in which the digital signal processing block 210 is divided into three sections corresponding to the digital code of the analog-to-digital converter 240 and configured to apply a change in the on time (ton) of the driving pulse differently for each section. It is one graph.

In the case of FIG. 10 , the digital signal processing block 210 includes a period (x1 period) in which the on time (ton) of the driving pulse increases by one time of a preset time in response to an increase in the digital code by one bit (x1 period), the digital code is In response to increasing by 1 bit, the on time (ton) of the driving pulse increases by twice the preset time (x2 interval), and in response to the digital code increasing by 1 bit, the on time (ton) of the driving pulse (ton) ) is divided into a section (x4 section) increasing by 4 times the preset time, and it can be controlled to generate a driving pulse having an on time corresponding to a digital code provided in response to a change in the feedback signal FB signal.

When the digital signal processing block 210 is designed to change uniformly by 46.5 ns per digital code using the 9-bit analog-to-digital converter 240 , the maximum on time (ton) of the driving pulse may be implemented at the level of 23 μs.

As shown in FIG. 10 , when the digital signal processing block 210 changes the on time ton differently for each section in response to a change in the digital code, the on time ton is changed by 46.5 ns per digital code in the x1 section. In the x2 section, the on time (ton) may be changed by 93 ns per digital code, and in the x4 section, the on time (ton) may be changed by 186 ns per digital code.

Even using the 9-bit analog-to-digital converter 240, the digital signal processing block 210 can guarantee a maximum on-time (ton) of 30 μs or more.

As described above, the digital signal processing block 210 of the embodiment can operate using an analog-to-digital converter having a reduced number of bits, and as a result, a layout margin required for mounting the analog-to-digital converter in a package can be secured, The package can be advantageously implemented in terms of chip size.

According to an embodiment of the present invention, the order in which the x1 section, the x2 section, and the x3 section are arranged may be changed according to the intention of the manufacturer, and the x1 section may be applied to a section requiring fine control.

Meanwhile, when a relatively high first voltage and a relatively low second voltage are applied as the input voltage VIN, the range for controlling the on time is reduced. As a result, the number of digital codes of the analog-to-digital converter 240 required in response to the first voltage may be smaller than the number of digital codes of the analog-to-digital converter 240 required in response to the second voltage.

That is, when the input voltage VIN is high, a small on-time is used, and accordingly, the level of the feedback signal FB is lowered. Therefore, when the input voltage VIN is the first voltage, the analog-to-digital converter 240 may express the on time with relatively few bits.

Accordingly, there is a margin in the design of the analog-to-digital converter 240 . Therefore, if the analog-to-digital converter 240 is designed in response to a high input voltage, a layout margin necessary for mounting the analog-to-digital converter 240 on a package can be secured, and the package can be advantageously implemented in terms of chip size. have.

On the other hand, according to the present invention, as shown in FIG. 11 , the analog-to-digital converter 240 may be configured to accurately sense the feedback signal FB.

The feedback signal FB is sensed by the analog-to-digital converter 240 , converted into a digital code, and then transferred to the digital signal processing block 210 . The analog-to-digital converter 240 receives the feedback voltage V _FB to sense the feedback signal FB.

The analog-to-digital converter 240 needs to accurately sense the feedback signal FB using the _{stabilized feedback voltage V FB .}

Noise may be generated in the voltage VDS between the drain and the source of the switching element Q at the turn-on and turn-off times of the switching element Q. When the driving signal GD is activated, that is, when the switching element Q is turned on, resonance due to the capacitance component of the inductor and the switching element Q of the power conversion circuit 14 occurs. And, when the driving signal GD is deactivated, that is, when the switching element Q is turned off, resonance due to the parasitic inductor of the power conversion circuit 14 and the capacitance component of the switching element Q occurs. _{The feedback voltage V FB} may be affected by noise due to resonances at the turn-on and turn-off timings of the switching element Q. In this case, the feedback voltage V _FB becomes unstable due to noise.

In a state where the feedback voltage V _FB is affected by noise and is unstable, if the analog-to-digital converter 240 senses the feedback signal FB, it is difficult to accurately sense the feedback signal FB.

An embodiment of the present invention sets and uses _{a blank time (t BLK} ) for accurate sensing of the feedback signal FB as shown in FIG. 11 . A blank time (t _BLK ) may be defined as a time from a turn-off time of the switching element Q to a predetermined time out of the influence of noise. The blank time t _BLK is preferably set to a time sufficient to not be affected by noise.

The analog-to-digital converter 240 is configured to sense the feedback signal FB using the stabilized feedback voltage V _{FB after the blank time t BLK has elapsed.}

The analog-to-digital converter 240 may use the sampling clock V _SMPL to _{recognize that the blank time t BLK has elapsed.}

The sampling clock V _SMPL may have a constant period corresponding to the turn-off period of the switching element Q, and may be generated in the digital signal processing block 210 or the analog-to-digital converter 240 using the pulse of the oscillator 230 . can The sampling clock V _SMPL is preferably generated to occur after the switching element Q is turned off and the blank time t _{BLK has elapsed.}

The analog-to-digital converter 240 may sample the feedback voltage V _{FB using the sampling clock V SMPL generated after the blank time (t BLK} ) has elapsed, and when the sampling clock V _SMPL is received, the feedback voltage V V _The feedback signal FB may be sensed by sampling the FB, and a digital code corresponding to the sensed feedback signal FB may be generated. The analog-to-digital converter 240 _{requires a certain time to sense the feedback signal FB} by sampling the feedback voltage V FB , and the time (tconv) required to sense the feedback signal FB corresponds to “DATA Load to Digital” described in FIG. 11 . do.

When the digital code of the analog-to-digital converter 240 corresponding to the sensed feedback signal FB is received, the digital signal processing block 210 may control the on-time of the switching element Q of the next cycle. In FIG. 11 , V _DRV represents a change in the driving signal GD provided to the switching element Q .

If the period of the driving signal GD is long or the period of the sampling clock V _{SMPL is short, as shown in FIG. 12 , several sampling clocks V SMPL} are included in one period of the driving signal GD, that is, the turn-off period of one switching element Q. can

In this case, the analog-to-digital converter 240 is sampled when the feedback voltage V _FB in response to each sampling clock V _SMPL, and the feedback voltage V _FB complete sampling of previously sampled feedback voltage V _FB is the refreshing (Reflash). Then, the analog-to-digital converter 240 outputs a digital code by using the feedback signal FB corresponding to the last sampling clock V _{SMPL on which sampling of the feedback voltage V FB is completed.}

Also, according to the present invention, when multiple sampling is performed as shown in FIG. 12 , the feedback signal FB may be sensed using the feedback voltage V _{FB sampled by the sampling clock V SMPL in a predetermined order.}

11 and 12, the analog-to-digital converter 240 _{samples the feedback voltage V FB} in a stable state and accurately senses the feedback signal FB using the sampled feedback voltage V _FB. . As a result, the present invention can provide a driving signal GD having a stable on-time (ton).

Claims (16)

In the power supply circuit for performing power conversion in the power conversion circuit by driving a switching element,
After the switching element is turned off, a base point of a resonance period of a turn-off voltage of the switching element is detected to control an on time of the switching element, and when the switching element is turned on, the clamping level of the sensing voltage of the power conversion circuit and A power supply circuit comprising a; a control unit for generating an input compensation signal by detecting a level change of the input voltage using a difference in the input voltage, and performing input compensation using the input compensation signal. According to claim 1,
The control unit determines the clamping level of the sensing voltage by using a sensing signal delayed by a predetermined time from a zero current point at which the sensing voltage starts to drop from a high level. According to claim 1,
The control unit is a power circuit for controlling the on-time by gradually changing the on-time within a pore resonance period according to a change in the load. According to claim 1,
The control unit is a power circuit to generate the input compensation signal corresponding to any one of a first level and a second level of the input voltage. According to claim 1,
Detects a zero current time point when the current of the primary side of the power conversion circuit reaches zero, and sends a delayed detection signal from the zero current time point to a time point corresponding to the base point of the resonance period to the control unit A power supply circuit further comprising a zero current sensing circuit providing According to claim 1, wherein the control unit,
a gate driver outputting a driving signal for driving the switching element;
an input compensation circuit generating the input compensation signal by detecting a level change of the input voltage using a difference between the clamping level of the sensing voltage sensed by the current of the primary side of the power conversion circuit and the input voltage; and
A digital signal processing block for controlling the on time of the switching element by detecting a base point of a resonance period of a turn-off voltage of the switching element after the switching element is turned off, and performing input compensation using the input compensation signal A power circuit containing ; 7. The method of claim 6,
The digital signal processing block is configured to perform the input compensation including adjustment of an overcurrent detection signal according to a change in the input voltage by using the input compensation signal. 7. The method of claim 6, wherein the input compensation circuit comprises:
Outputting a compensation sensing signal by applying a reference voltage that varies according to the level of the input voltage to the difference between the clamping level of the sensing signal delayed by a predetermined time from the zero current time point when the sensing voltage starts to drop from the high level and the input voltage input detection circuit; and
The compensation sensing signal is received and counted in units of the driving signal cycle, and when it is counted that the compensation sensing signal maintains the same state for a predetermined number or more, the input compensation signal is provided for determining that the level of the input voltage has changed A power circuit comprising a; an input compensation logic unit. The method of claim 8, wherein the input detection circuit comprises:
a clamping circuit configured to generate a first current corresponding to a difference between the clamping level of the sensing signal and the input voltage delayed by a predetermined time from the zero current time point;
a current mirror circuit for providing a second current copied from the first current; and
In response to the input voltage of a first level, a first reference voltage is used to output the compensation sensing signal corresponding to the second current, and the second reference voltage is used to correspond to the input voltage of a second level. and an output unit outputting the compensation sensing signal corresponding to a second current. The method of claim 8, wherein the input compensation logic unit,
A power circuit that counts the level change of the compensation sensing signal in synchronization with the cycle of the driving signal, and determines that the level of the input voltage is changed when the level of the compensation sensing signal is continuously counted as being maintained three times. According to claim 1, wherein the control unit,
The level of the input voltage using a difference between the clamping level of the sensing voltage sensed at the output of the power conversion circuit and the input voltage in synchronization with a time when the switching element is turned on during a period of a driving signal for driving the switching element A power circuit that counts changes and generates the input compensation signal by determining that the level of the input voltage is changed when the level of the input voltage is maintained by a predetermined number or more. In the power supply circuit for performing power conversion in the power conversion circuit by driving a switching element,
Controls generation of a driving signal provided for driving the switching element, the switching element is switched by driving pulses included in the driving signal, and the turn-off voltage of the switching element after the switching element is turned off a digital signal processing block that detects a base point of a resonance period to control an on-time of the switching element, and receives a digital code corresponding to a feedback signal corresponding to a load to control an on-time of the driving pulse; and
and an analog-to-digital converter that senses the feedback signal and provides the digital code,
The digital signal processing block recognizes the range of the digital code provided from the analog-to-digital converter as two or more divided sections, and controls the driving pulse by applying a change in ON time corresponding to 1 bit of the digital code for each section. power circuit. 13. The method of claim 12,
The digital signal processing block is a power circuit having two or more divided sections set to have the on-time gradually larger in response to a change in the digital code. In the power supply circuit for performing power conversion in the power conversion circuit by driving a switching element,
Controls generation of a driving signal provided for driving the switching element, the switching element is switched by driving pulses included in the driving signal, and the turn-off voltage of the switching element after the switching element is turned off a digital signal processing block that detects a base point of a resonance period to control an on-time of the switching element, and receives a digital code corresponding to a feedback signal corresponding to a load to control an on-time of the driving pulse; and
The feedback signal senses the feedback signal by sampling a feedback voltage provided in response to the load after a blank time set from a turn-off time of the switching element to a predetermined time has elapsed, and the digital corresponding to the feedback signal A power circuit comprising an analog-to-digital converter providing a cord. 15. The method of claim 14,
The blank time may be determined by a sampling clock having a constant period corresponding to a turn-off period of the switching element, and the sampling clock is power generated by the digital signal processing block or the analog-to-digital converter using a pulse of an oscillator Circuit. 16. The method of claim 15,
The analog-to-digital converter may include a plurality of sampling clocks within one turn-off period, and performs sampling of the feedback voltage in response to the sampling clock that has completed a specific order or last sampling.

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