JP5691790B2 - Constant current power supply - Google Patents

Description

  The present invention relates to a constant current power supply device that drives a load with a constant current, and more particularly to a constant current power supply device that drives a load with a pulse signal (hereinafter referred to as a PWM signal) based on PWM control (Pulse Width Modulation).

  An LED (light emitting diode) has a characteristic that the color tone changes in accordance with the magnitude of current. Therefore, the LED is generally driven with a constant current. When dimming control is performed, the LED is turned on / off with a PWM signal, and the light amount is adjusted by the duty ratio of the PWM signal.

  On the other hand, when a switching power supply is used as a constant current power supply device that drives a load with a constant current, it is necessary to detect the output current and perform feedback control. When the LED is driven by the PWM signal as described above, the LED repeats the lighting period and the extinguishing period. Naturally, no current flows through the LED during the extinguishing period, and the output current is fed back as zero. In this way, when the output current is fed back as zero, excessive power is supplied too much, so it is proposed to prevent excessive power supply by limiting the feedback control during the lighting period of the LED. (For example, refer to Patent Document 1).

  Patent Document 1 discloses a non-insulated step-up chopper type switching power supply, and an ON period in which an LED is turned on is an OFF period in which an operating current is supplied based on an LED operating current instruction value and the LED is turned off. The LED and the supply voltage are separated by an n-type MOS transistor, and the switching operation of the switching power supply as the LED supply voltage source is also turned off in synchronization. As described above, in Patent Document 1, power consumption during standby is reduced by turning on / off the switching power supply in synchronization with the PWM signal.

JP 2004-147435 A

7A and 7B are waveform diagrams for explaining the operation of the constant current power supply device of the prior art, where FIG. Current, (d) shows an LED drive signal, and (e) shows an FB signal.
Referring to FIG. 7, when a PWM signal is input at time t0, an LED drive signal synchronized with the PWM signal is also output, power is supplied from the primary side to the secondary side, and the output voltage rises. When the output voltage reaches the forward voltage drop VF at which the output voltage starts to flow through the LED array 2 at time t1, the LED current starts to flow. After the output voltage reaches a predetermined voltage at time t2, the LED array 2 is driven with a constant current.

  However, in the prior art, since the switching power supply is turned on / off in synchronization with the PWM signal, the switching power supply is turned on only during the ON period in which the LED whose driving signal is at the H level is lit even in the startup sequence at the time of power activation. Thus, power is supplied from the primary side to the secondary side. Therefore, as shown in FIG. 7, when the light amount is reduced at the time of starting the power supply and the duty ratio of the PWM signal is small, the switching power supply has a short ON period, so that the rise time of the output voltage is delayed and the prescribed LED There is a problem that it takes time until the LED emits light when current flows. Note that, as disclosed in Patent Document 1, in a non-insulated step-up chopper type switching power supply, an output voltage is obtained by raising an input voltage, and therefore a delay in rise time is short due to a difference between the input voltage and the output voltage. However, in the switching power supply of the insulation type DC-DC converter, the output voltage always rises from 0V, so that the delay of the rise time of the output voltage becomes remarkable.

  Further, since the ON period of the switching power supply changes according to the duty ratio of the PWM signal, the output voltage rise time is not determined, and the time until the LED emits light due to the specified LED current flowing varies.

  The object of the present invention is to solve the problems of the prior art in view of the above problems, and to quickly raise the output voltage even when the light amount is reduced and the duty ratio of the PWM signal is small at power-on. An object of the present invention is to provide a constant current power supply device that can be used.

The constant current power supply device of the present invention is synchronized with an external pulse signal for driving on / off of a load provided on the secondary side, and is controlled from the primary side by on / off control of a switching element provided on the primary side. A constant current power supply device that supplies power to the secondary side and drives the load with a set constant current using the power supplied to the secondary side, and detects the load current flowing through the load Detection means, and load current comparison means for comparing the load current detected by the load current detection means with a preset second reference value, and at startup, the load current is the second reference value. until reaching, the external pulse signal regardless, the said continuous load with a switching element continuously is continuously supplied power from the primary side by controlling oN / oFF on the secondary side on Driven It is characterized by making it.
Furthermore, in the constant current power supply device of the present invention, a fourth reference value generating unit that integrates the external pulse signal to generate a fourth reference value, and a load current flowing through the load is converted into a voltage signal and integrated. An integral signal generating means for generating an integral signal; and an integral signal comparing means for comparing the fourth reference value with the integral signal. When the integral signal exceeds the fourth reference value, the load current is Even when the second reference value is reached, the supply of power from the primary side to the secondary side is stopped and the load is driven off.
In the constant current power supply device of the present invention, the primary is controlled by on / off control of the switching element provided on the primary side in synchronization with an external pulse signal for driving on / off the load provided on the secondary side. A constant current power supply apparatus for supplying power from the side to the secondary side and driving the load with a set constant current using the power supplied to the secondary side, wherein the secondary side output voltage and Output voltage comparison means for comparing with a set third reference value is provided, and at the time of start-up, the switching element is continuously connected regardless of the external pulse signal until the output voltage reaches the third reference value. characterized the Turkey is continuously supplied power from the primary side by controlling oN / oFF on the secondary side Te.
Furthermore, in the constant current power supply device of the present invention, a fourth reference value generating unit that integrates the external pulse signal to generate a fourth reference value, and a load current flowing through the load is converted into a voltage signal and integrated. an integration signal generating means for generating an integrated signal, comprising an integration signal comparing means for comparing said fourth reference value and the integrated signal and, when the integration signal exceeds the fourth reference value, the output voltage is the Even when the third reference value is reached, the supply of power from the primary side to the secondary side is stopped and the load is driven off.

It is a circuit block diagram which shows the circuit structure of 1st Embodiment of the constant current power supply device which concerns on this invention. It is a circuit block diagram which shows the circuit structure of the secondary side control part shown in FIG. It is a wave form diagram which shows the signal waveform and operation waveform of each part of 1st Embodiment of the constant current power supply device which concerns on this invention. It is a circuit block diagram which shows the circuit structure of the secondary side control part of 2nd Embodiment of the constant current power supply device which concerns on this invention. It is a circuit block diagram which shows the circuit structure of the secondary side control part of 3rd Embodiment of the constant current power supply device which concerns on this invention. It is a wave form diagram which shows the signal waveform and operation waveform of each part of 3rd Embodiment of the constant current power supply device which concerns on this invention. It is a wave form diagram for demonstrating operation | movement of the constant current power supply device of a prior art.

Next, embodiments of the present invention will be specifically described with reference to the drawings.

(First embodiment)
The constant current power supply device according to the first embodiment is an insulation type DC-DC converter that drives the LED array 2 with a constant current. As shown in FIG. 1, a rectifier circuit DB, a smoothing capacitor C1, and 1 Secondary side control circuit Cont1, N-type MOSFET (hereinafter referred to as NMOS) Q1, transformer T, rectifier diode D1, smoothing capacitor C2, NMOS Q2, secondary side control circuit Cont2, drive circuit DR, , Resistors R1 and R2, a capacitor C3, and a first photocoupler PC1 and a second photocoupler PC2 each including a light emitting diode and a light receiving transistor.

  A commercial AC power supply AC is connected to the AC input terminals ACin1 and ACin2 of the rectifier circuit DB, and the AC voltage input from the commercial AC power supply AC is full-wave rectified and output from the rectifier circuit DB. The negative terminal of the rectification output of the rectifier circuit DB is connected to the ground terminal, and the source terminal of an N-type MOSFET (hereinafter referred to as NMOS) Q1 which is a switching element is connected. The drain terminal of the NMOS Q1 is the primary of the transformer T. It is connected to the rectified output positive terminal of the rectifier circuit DB via the winding P. The gate terminal of the NMOS Q1 is connected to the primary side control circuit Cont1, and the NMOS Q1 is controlled to be turned on / off by the primary side control circuit Cont1. A DC power source rectified and smoothed by the rectifier circuit DB and the smoothing capacitor C1 is applied to the primary winding P of the transformer T by the on / off control of the NMOS Q1.

  The transformer T stores magnetic energy when the NMOS Q1 is turned on, and the magnetic energy stored when the NMOS Q1 is turned off is released as electric power from the secondary winding S of the transformer T. A smoothing capacitor C2 is connected between both terminals of the secondary winding S of the transformer T via a rectifier diode D1, and the electric power discharged from the secondary winding S of the transformer T is supplied to the rectifier diode D1 and the smoothing capacitor C2. Is rectified and smoothed. The line connected to the positive terminal of the smoothing capacitor C2 is a power supply line for the output voltage V0, and the line connected to the negative terminal of the smoothing capacitor C2 is a GND line connected to the ground terminal.

  An LED array 2 in which n (n is an arbitrary natural number) LEDs 21 to 2n are connected in series is used as a load to be driven. The LED array 2, the NMOS Q2, and the resistor R1 are connected in series between the power supply line and the GND line. The anode side terminal of the LED array 2 is connected to the power supply line, the drain side terminal of the NMOS Q2 is connected to the cathode side terminal of the LED array 2, and the source terminal of the NMOS Q2 is connected to the GND line via the resistor R1. The gate terminal of the NMOS Q2 is connected to the terminal T2 of the secondary side control circuit Cont2. A PWM signal that is an external pulse signal is input to the terminal T1 of the secondary side control circuit Cont2. The secondary side control circuit Cont2 outputs an LED drive signal based on the PWM signal input from the terminal T1 from the terminal T2. As a result, the NMOS Q2 is turned on / off. As a result, the power supplied to the secondary side is used to turn on / off the LED array 2 as a load with a set constant current in synchronization with the PWM signal.

  The terminal T3 of the secondary side control circuit Cont2 is connected to the connection point between the source terminal of the NMOS Q2 and the resistor R1, and the terminal T4 of the secondary side control circuit Cont2 is the cathode of the light emitting diode that constitutes the photocoupler PC1. The anode of the light emitting diode constituting the photocoupler PC1 is connected to the reference voltage Vcc. The primary side control circuit Cont1 is connected to the collector of the light receiving transistor constituting the photocoupler PC1, and the emitter of the light receiving transistor constituting the photocoupler PC1 is grounded. Note that the connection point between the terminal T4 of the secondary control circuit Cont2 and the cathode of the light emitting diode constituting the photocoupler PC1 is grounded via a phase correcting resistor R2 and a capacitor C3. Thereby, the secondary side control circuit Cont2 outputs an FB (feedback) signal based on the voltage drop of the resistor R1 input from the terminal T2 from the terminal T4. The FB signal output from the terminal T4 is sent to the primary side control circuit Cont1 via the photocoupler PC1, and the primary side control circuit Cont1 controls the on / off time of the NMOS Q1 based on the FB signal, so that a predetermined value is obtained. The current is controlled to flow through the LED array 2.

  The connection point between the terminal T2 of the secondary control circuit Cont2 and the gate terminal of the NMOS Q2 is connected to the cathode of the light emitting diode constituting the photocoupler PC2 through the drive circuit DR, and the anode of the light emitting diode constituting the photocoupler PC2. Is connected to a reference voltage Vcc. The primary side control circuit Cont1 is connected to the collector of the light receiving transistor constituting the photocoupler PC2, and the emitter of the light receiving transistor constituting the photocoupler PC2 is grounded. As a result, the LED drive signal which is the gate signal of the NMOS Q2 is sent to the primary side control circuit Cont1 via the photocoupler PC2, and the primary side control circuit Cont1 controls the switching operation or stop based on the LED drive signal. . That is, when the LED drive signal based on the PWM signal is at the H level, the switching operation is performed to supply power from the primary side to the secondary side, and when the LED drive signal is at the L level, the switching operation is stopped. Accordingly, power is supplied from the primary side to the secondary side in synchronization with the PWM signal.

Next, the circuit configuration of the secondary side control circuit Cont2 will be described in detail with reference to FIG.
The secondary side control circuit Cont2 includes an OR circuit OR1, a reset-priority RS flip-flop circuit FF1, a buffer circuit BF1, a comparator CP1, an operational amplifier OP1, sample-and-hold circuits SH1, SH2, 1 reference voltage Vref1 and 2nd reference voltage Vref2.

  A terminal T1 to which a PWM signal for determining the brightness of the LED is input is connected to the set terminal S of the flip-flop FF1, and is also connected to one input terminal of the OR circuit OR1. The other input terminal of the OR circuit OR1 is connected to the output terminal Q of the flip-flop FF1. The output terminal of the OR circuit OR1 is connected to the terminal T2 to which the gate terminal of the NMOS Q2 is connected via the buffer circuit BF1, and the output terminal of the OR circuit OR1 is the control signal input terminal of the sample-and-hold circuits SH1 and SH2. It is connected to the. With this configuration, the PWM signal input to the terminal T1 is output from the terminal T2 to the gate terminal of the NMOS Q2 as the LED drive signal via the OR circuit OR1 and the buffer circuit BF1. Therefore, when the PWM signal becomes H (HIGH) level, the flip-flop FF1 is set, and the LED drive signal output from the terminal T2 also becomes H level, and the NMOS Q2 is turned on and current flows through the LED array 2. Further, when the LED drive signal also becomes H level, the current flowing through the second photocoupler PC2 is turned off via the drive circuit DR, the primary side control circuit Cont1 operates, and the primary side control circuit Cont1 is connected to the NMOS Q1. Start the switching operation.

  A connection point between the source terminal of the NMOS Q2 and the resistor R1 is connected to a terminal T3 of the secondary side control circuit Cont2. The terminal T3 is connected to the non-inverting input terminal of the comparator CP1, and is also connected to the input terminal of the sample and hold circuit SH1. The inverting input terminal of the comparator CP1 is connected to the second reference voltage Vref2, and the output terminal of the comparator CP1 is connected to the reset terminal R of the flip-flop FF1. The output terminal of the sample and hold circuit SH1 is connected to the inverting input terminal of the operational amplifier OP1, and the non-inverting input terminal of the operational amplifier OP1 is connected to the first reference voltage Vref1. Furthermore, the output terminal of the operational amplifier OP1 is connected to the input terminal of the sample and hold circuit SH2, and the output terminal of the sample and hold circuit SH2 is connected to the terminal T4. Therefore, the LED current IL flowing through the LED array 2 and the NMOS Q2 is detected as a voltage drop of the resistor R1. The resistor R1 functions as a load current detection unit that detects the LED current IL flowing through the LED array 2. The LED current IL detected as a voltage drop of the resistor R1 is compared with the second reference voltage Vref2 by a comparator CP1 as a load current comparison unit. The voltage drop of the resistor R1 corresponding to the LED current IL is input to the operational amplifier OP1 via the sample and hold circuit SH1, and a signal obtained by amplifying the error voltage with respect to the first reference voltage Vref1 is sampled and held as the FB signal. It is output via the circuit SH2.

  The second reference voltage Vref2 is set to a value lower than the first reference voltage Vref1, and is 80% of the first reference voltage Vref1 in the present embodiment. As described above, since the output terminal of the comparator CP1 is connected to the reset terminal R of the flip-flop FF1, when the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2, the flip-flop FF1 is Reset. In other words, the flip-flop FF1 is not reset until the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2. When the flip-flop FF1 is set, an H level signal output from the output terminal Q of the flip-flop FF1 is output from the terminal T2 via the OR circuit OR1 and the buffer circuit BF1. Therefore, in the state where the flip-flop FF1 is set, even if the PWM signal input to the terminal T1 becomes L (LOW) level, the LED drive signal output from the terminal T2 becomes H level, and the NMOS Q2 is in the ON state. Maintained. When the flip-flop FF1 is reset, the signal output from the output terminal Q of the flip-flop FF1 becomes L level, and when the PWM signal input to the terminal T1 becomes L level, the output signal of the OR circuit OR1 becomes L level. Become. Therefore, the LED drive signal output from the terminal T2 becomes L level, and the NMOS Q2 is turned off.

  When the output signal of the OR circuit OR1 becomes L level, the sample and hold circuits SH1 and SH2 hold the previous signal voltage. That is, the sample and hold circuit SH1 holds a signal of a voltage drop across the resistor R1, and the sample and hold circuit SH2 holds a signal obtained by amplifying the error voltage between the output of the sample and hold circuit SH1 and the first reference voltage Vref1.

  FIG. 3 shows a rising sequence at the time of starting the constant current power supply device of the first embodiment. (A) is a PWM signal input from the terminal T1 of the secondary side control circuit Cont2. (B) Is the output voltage V0 of the power line, (c) is the voltage drop of the resistor R1 corresponding to the LED current IL flowing through the LED array 2, (d) is the input signal of the set terminal S, and (e) is the flip-flop. FF1 is the input signal of the reset terminal R, (f) is the flip-flop FF1 is the output signal of the output terminal Q, (g) is the LED drive signal output from the terminal T2 of the secondary side control circuit Cont2, and (h) is the FB Each signal is shown.

  As shown in FIG. 3A, when a PWM signal that is a dimming signal that determines the brightness of the LED array 2 is input at time t10, the PWM signal at the H level is changed as shown in FIG. The signal is input to the set terminal S of the flip-flop FF1, and the flip-flop FF1 is set. When the flip-flop FF1 is set, the output signal from the output terminal Q of the flip-flop FF1 becomes H level as shown in FIG. 3 (f), and the OR circuit OR1 and the buffer as shown in FIG. 3 (g). The LED drive signal output from the terminal T2 of the secondary side control circuit Cont2 through the circuit BF1 becomes H level. When the LED drive signal becomes H level, the NMOS Q2 is turned on and the current flowing through the second photocoupler PC2 is turned off via the drive circuit DR, and the primary side control circuit Cont1 starts the switching operation of the NMOS Q1. .

  When the switching operation of the NMOS Q1 is started, electric power is supplied from the primary side to the secondary side, electric charges are accumulated in the smoothing capacitor C2, and the output voltage V0 rises as shown in FIG. 3B. When the output voltage V0 that has risen reaches the forward drop voltage VF where current starts to flow in the LED array 2 at time t11, as shown in FIG. 3C, the LED current IL starts to flow.

  Next, as shown in FIG. 3C, when the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2 at time t12, as shown in FIG. 3E, the flip-flop FF1 Is inputted to the reset terminal R, and as shown in FIG. 3F, the output signal from the output terminal Q of the flip-flop FF1 becomes L level. Even when the output signal from the output terminal Q of the flip-flop FF1 becomes L level at time t12, the PWM signal is at H level as shown in FIG. The signal becomes the H level, and as shown in FIG. 3G, the LED drive signal output from the terminal T2 of the secondary side control circuit Cont2 is maintained at the H level.

  During the period from time t10 to t12, the state in which the flip-flop FF1 is set is maintained, and the LED drive signal output from the terminal T2 of the secondary side control circuit Cont2 is always at the H level as shown in FIG. It is. Accordingly, the switching operation of the NMOS Q1 is performed without being influenced by the PWM signal, that is, even when the PWM signal is at the L level, and the power corresponding to the FB signal shown in FIG. As shown in FIG. 3 (b), the rising time of the output pressure V0 at the time of start-up is greatly reduced. In the period from time t11 to t12, the NMOS Q2 is always turned on regardless of the PWM signal, and the LED current IL flows continuously. Therefore, the slope of the rise of the output pressure V0 is higher than that in the period from time t10 to t12. Slightly looser.

  Next, as shown in FIG. 3A, when the PWM signal becomes L level at time t13, the output signal of the OR circuit OR1 becomes L level, and as shown in FIG. The LED drive signal output from the terminal T2 of Cont2 becomes L level. After time t13, referring to FIGS. 3D, 3E, and 3F, when the PWM signal becomes H level, the flip-flop FF1 is set, but the voltage drop of the resistor R1 corresponding to the LED current IL is reduced. Since the second reference voltage Vref2 is exceeded, the flip-flop FF1 is set almost at the same time, and the signal from the output terminal Q of the flip-flop FF1 instantaneously returns to the L level after instantaneously becoming the H level. Therefore, a pulse signal synchronized with the PWM signal is output from the output terminal of the OR circuit OR1, and as shown in FIG. 3G, the terminal T2 of the secondary side control circuit Cont2 is synchronized with the PWM signal. The LED drive signal is output. Time t14 indicates the time when the voltage drop of the resistor R1 corresponding to the LED current IL reaches a preset value of 100%, and thereafter, the LED is turned on / off at a constant LED current IL regardless of the on-pulse width of the PWM signal. The output voltage V0 is a voltage corresponding to the LED current IL.

  In the present embodiment, power is continuously supplied from the primary side to the secondary side regardless of the PWM signal until the LED current IL detected as the voltage drop of the resistor R1 exceeds the second reference voltage Vref2. The LED array 2 is continuously turned on as the operation continues. The second reference voltage Vref2 is set to a value lower than the first reference voltage Vref1, and is 80% of the first reference voltage Vref1. The first reference voltage Vref1 is a value detected as a voltage drop of the resistor R1 when the LED current IL is a preset value of 100%. Therefore, in the present embodiment, power is continuously supplied from the primary side to the secondary side regardless of the PWM signal until the LED current IL exceeds 80% of the preset value. The second reference voltage Vref2 can be set as appropriate. As the second reference voltage Vref2 is made closer to the first reference voltage Vref1, the time during which power is continuously supplied from the primary side to the secondary side becomes longer, so that the rise time of the output compression pressure V0 is shortened. However, as in the example shown in FIG. 3, when the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2 when the PWM signal is at the H level, the secondary side is still from the primary side. Since electric power continues to be supplied, overshoot may occur.

  As described above, according to the first embodiment, the LED current IL flowing through the LED array 2 is detected by the voltage drop caused by the resistor R1, and the voltage drop of the resistor R1 corresponding to the LED current IL detected by the comparator CP1 is detected. Is compared with the second reference voltage Vref2, and at the time of start-up, the secondary voltage from the primary side is increased regardless of the PWM signal until the voltage drop of the resistor R1 corresponding to the LED current IL reaches the second reference voltage Vref2. The power is continuously supplied to the side and the LED array 2 is continuously turned on. With this configuration, the first embodiment has an effect that the output voltage V0 can be quickly raised even when the amount of light is reduced when the power is turned on and the duty ratio of the PWM signal is small.

(Second Embodiment)
In the first embodiment, the state in which the flip-flop FF1 is set is maintained until the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2. This embodiment is different in that the state where the flip-flop FF1 is set is maintained until the output voltage V0 exceeds the third reference voltage Vref3.

  Referring to FIG. 4, the secondary side control circuit Cont2a used in the second embodiment has an output voltage V0 of the second side control circuit Cont2 instead of the comparator CP1 of the secondary side control circuit Cont2 used in the first embodiment. A comparator CP2 that compares the three reference voltages Vref3, an OR circuit OR2, and a terminal T5 to which a POR signal is input are provided.

  The non-inverting input terminal of the comparator CP2 is connected to the power supply line V0, and the inverting input terminal of the comparator CP2 is connected to the third reference voltage Vref3. The third reference voltage Vref3 is lower than the preset value 100% of the power supply line V0 and is set to 80, which is a preset value of the power supply line V0. The output terminal of the comparator CP2 is connected to one input terminal of the OR circuit OR1, and the other input terminal of the OR circuit OR1 is connected to a terminal T5 to which the POR signal is input. The output terminal of the OR circuit OR1 is connected to the reset terminal R of the flip-flop FF1.

  When the POR signal or the output signal of the comparator CP2 becomes H level and the output signal of the OR circuit OR1 becomes H level, the flip-flop FF1 is reset. The POR signal is a signal notifying that the primary side control circuit Cont1 has risen, and the flip-flop FF1 is reset in the initial stage. Therefore, after the PWM signal is input to the terminal T1 and the flip-flop FF1 is set, as shown in FIG. 3B, the output voltage V0 exceeds the third reference voltage Vref3 until the output from the primary side to the secondary side. Is continuously supplied with electric power.

  As described above, according to the second embodiment, the comparator CP2 compares the output voltage V0 and the third reference voltage Vref3 until the output voltage V0 reaches the third reference voltage Vref3 at startup. Regardless of the PWM signal, power is continuously supplied from the primary side to the secondary side and the LED array 2 is continuously turned on. With this configuration, the second embodiment has an effect that the output voltage V0 can be quickly raised even when the light amount is reduced when the power is turned on and the duty ratio of the PWM signal is small.

(Third embodiment)
In the third embodiment, the LED current IL continuously flows until the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2 at the time of startup. In the embodiment, the period in which the LED current IL continuously flows is improved so as to be shorter than that in the first embodiment.

  Referring to FIG. 5, the secondary side control circuit Cont2b used in the second embodiment includes a buffer circuit BF2 and a resistor in addition to the configuration of the secondary side control circuit Cont2 used in the first embodiment. An integration circuit 10 including R3 and a capacitor C4, an integration circuit 11 including a resistor R4 and a capacitor C3, a comparator CP3, OR circuits OR3 and OR4, and a terminal T5 to which a POR signal is input are provided.

  The terminal T1 is connected to the inverting input terminal of the comparator CP3 through the buffer circuit BF2 and the integrating circuit 10 including the resistor R3 and the capacitor C4. The buffer circuit BF2 and the integration circuit 10 function as fourth reference value generation means for generating a fourth reference value based on the PWM signal, and the generated fourth reference value is input to the inverting input terminal of the comparator CP3. A terminal T3 to which a voltage drop of the resistor R1 corresponding to the LED current IL is input is connected to a non-transfer input terminal of the comparator CP3 via an integrating circuit 11 including a resistor R4 and a capacitor C3. The resistor R1 and the integrating circuit 11 function as integrated signal generating means for generating an integrated signal obtained by converting the LED current IL into a voltage signal, and the generated integrated signal is input to the non-inverting input terminal of the comparator CP3. . Further, the output terminal of the comparator CP3 and one input terminal of the OR circuit OR3 are connected. The comparator CP3 functions as an integration signal comparison unit that compares the fourth reference value with the integration signal. The output terminal of the comparator CP1 is connected to the other input terminal of the OR circuit OR3, and the output terminal of the OR circuit OR3 is connected to one input terminal of the OR circuit OR4. Further, the terminal T5 and the other input terminal of the OR circuit OR4 are connected, and the output terminal of the OR circuit OR4 is connected to the reset terminal R of the flip-flop FF1.

  FIG. 6 shows a rising sequence at the time of starting the constant current power supply device according to the third embodiment. (A) is a POR signal inputted from the terminal T5 of the secondary side control circuit Cont2b, and (b). Is the PWM signal input from the terminal T1 of the secondary side control circuit Cont2b, (c) is the output voltage V0 of the power supply line, (d) is the voltage drop of the resistor R1 corresponding to the LED current IL flowing through the LED array 2, ( e) flip-flop FF1 is an input signal of the set terminal S, (f) is an input signal of the comparator CP3, (g) an output signal of the comparator CP3, (h) is an input signal of the flip-flop FF1 is an input signal of the reset terminal R, (i ) Is the output signal of the output terminal Q from the flip-flop FF1, (j) is the LED drive signal output from the terminal T2 of the secondary side control circuit Cont2, and (k) is the FB signal. Re respective shows.

  First, as shown in FIG. 6A, the POR signal is input from the terminal T5 of the secondary control circuit Cont2b when the power is turned on, and the flip-flop FF1 is reset. Next, as shown in FIG. 6B, when a PWM signal that is a dimming signal that determines the brightness of the LED array 2 is input at time t20, as shown in FIG. The PWM signal is input to the set terminal S of the flip-flop FF1, and the flip-flop FF1 is set. When the flip-flop FF1 is set, the output signal from the output terminal Q of the flip-flop FF1 becomes the H level as shown in FIG. 6 (i), and the OR circuit OR1 and the buffer as shown in FIG. 6 (j). The LED drive signal output from the terminal T2 of the secondary side control circuit Cont2b via the circuit BF1 becomes H level. When the LED drive signal becomes H level, the NMOS Q2 is turned on and the current flowing through the second photocoupler PC2 is turned off via the drive circuit DR, and the primary side control circuit Cont1 operates to perform the primary side control. The on / off control of the NMOS Q1 by the circuit Cont1 is started.

  When the switching operation of the NMOS Q1 is started, electric power is supplied from the primary side to the secondary side, electric charges are accumulated in the smoothing capacitor C2, and the output voltage V0 rises as shown in FIG. 6B. Further, the PWM signal amplified by the buffer circuit BF2 is integrated by the integrating circuit 10, and the input signal to the inverting input terminal of the comparator CP3 rises as shown in FIG. 6 (f).

  When the output voltage V0 that has risen reaches the forward drop voltage VF at which current starts to flow in the LED array 2 at time t21, as shown in FIG. 6C, the LED current IL starts to flow. When the LED current IL starts to flow, the LED current IL is detected at the terminal T3 as a voltage drop of the resistor R1, integrated by the integrating circuit 10, and as shown in FIG. 6 (f), to the non-inverting input terminal of the comparator CP3. The input signal rises. When the input signal to the non-inverting input terminal of the comparator CP3 exceeds the input signal to the inverting input terminal at time t22, an H level signal is output from the output terminal of the comparator CP3 as shown in FIG. The H level signal is input to the reset terminal R of the flip-flop FF1 via the OR circuits OR3 and OR4 as shown in FIG. 6H, and the flip-flop FF1 is reset. Thereby, as shown in FIG. 6 (i), the output from the output terminal Q of the flip-flop FF1 becomes L level. Therefore, when the PWM signal is at the L level, the output signal of the OR circuit OR1 is also at the L level, and the LED drive signal output from the terminal T2 of the secondary control circuit Cont2, as shown in FIG. Becomes L level.

Referring to FIG. 6 in the same operation, in the third embodiment, even if the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2 at time t23, the comparator CP3 The input signal to the non-inverting input terminal rises. Each time the input signal to the non-inverting input terminal of the comparator CP3 exceeds the input signal to the inverting input terminal at time t22, the LED drive signal becomes L level. Therefore, in the first embodiment, in order to shorten the rise time at the time of starting the power supply, the LED current IL continues until the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2. In the third embodiment, the rise time at the time of starting the power supply is slightly longer than that in the first embodiment, but the voltage drop of the resistor R1 corresponding to the LED current IL is the second reference. Even before the voltage Vref2 is exceeded, the LED current IL having a pulse width based on the PWM signal to some extent can be allowed to flow.

  The third embodiment is the same as the first embodiment after time t23 when the voltage drop of the resistor R1 corresponding to the LED current IL exceeds the second reference voltage Vref2. Time t24 indicates the time when the LED current IL reaches a preset value of 100%, and thereafter, the LED current IL is turned on / off based on the on-pulse width of the PWM signal and at a constant LED current IL. The output voltage V0 is a voltage corresponding to the LED current IL. Furthermore, the third embodiment can be applied to the configuration of the second embodiment.

  In the above-described embodiment, an example has been described in which the LED array 2 in which n (n represents an arbitrary natural number) LEDs 21 to 2n are connected in series is driven as a load, but one LED may be used. . Further, the load is not limited to the LED as long as it can be driven with a direct current.

  Note that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to a number, position, shape, and the like that are suitable for implementing the present invention. In each figure, the same numerals are given to the same component.

2 LED array 10, 11 Integration circuit 21-2n LED
BF1, BF2 Buffer circuit C1, C2 Smoothing capacitor C3, C4, C5 Capacitor Cont1 Primary side control circuit Cont2 Secondary side control circuit (first embodiment)
Cont2a secondary side control circuit (second embodiment)
Cont2b secondary side control circuit (third embodiment)
CP1, CP2, CP3 Comparator DB Rectifier circuit DR Drive circuit FF1 Flip-flop circuit D1 Rectifier diode OR1, OR2, OR3, OR4 OR circuit OP1 Operational amplifier PC1 First photocoupler PC2 Second photocoupler Q1 MOSFET (NMOS)
R1, R2, R3, R4 Resistance Q2 MOSFET (NMOS)
SH1, SH2 Sample and hold circuit T transformer Vref1 first reference voltage Vref2 second reference voltage (second reference value)
Vref3 Third reference voltage (third reference value)

Claims (4)

Power is supplied from the primary side to the secondary side by on / off control of the switching element provided on the primary side in synchronization with an external pulse signal for driving on / off the load provided on the secondary side, A constant current power supply device that drives the load with a set constant current using electric power supplied to a secondary side,
Load current detection means for detecting a load current flowing through the load;
Load current comparison means for comparing the load current detected by the load current detection means with a preset second reference value;
During startup, power is continuously supplied from the primary side to the secondary side by continuously turning on / off the switching element regardless of the external pulse signal until the load current reaches the second reference value. The constant current power supply apparatus is characterized in that the load is continuously turned on and the load is continuously turned on. A fourth reference value generating means for integrating the external pulse signal to generate a fourth reference value;
An integrated signal generating means for generating an integrated signal obtained by converting a load current flowing through the load into a voltage signal and integrating;
An integration signal comparison means for comparing the fourth reference value with the integration signal;
When the integration signal exceeds the fourth reference value, the supply of power from the primary side to the secondary side is stopped and the load is reduced even when the load current reaches the second reference value. 2. The constant current power supply device according to claim 1, wherein the constant current power supply device is driven off. Power is supplied from the primary side to the secondary side by on / off control of the switching element provided on the primary side in synchronization with an external pulse signal for driving on / off the load provided on the secondary side, A constant current power supply device that drives the load with a set constant current using electric power supplied to a secondary side,
Comprising output voltage comparison means for comparing the output voltage on the secondary side with a preset third reference value;
During startup, power is continuously supplied from the primary side to the secondary side by continuously turning on / off the switching element regardless of the external pulse signal until the output voltage reaches the third reference value. constant current power supply unit, wherein the benzalkonium is supplied with. A fourth reference value generating means for integrating the external pulse signal to generate a fourth reference value;
An integrated signal generating means for generating an integrated signal obtained by converting a load current flowing through the load into a voltage signal and integrating;
An integration signal comparison means for comparing the fourth reference value with the integration signal;
When the integrated signal exceeds the fourth reference value, the supply of power from the primary side to the secondary side is stopped and the load is reduced even when the output voltage reaches the third reference value. 4. The constant current power supply device according to claim 3, wherein the constant current power supply device is driven off.

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