JP5568779B2 - Logic verification method and logic verification system - Google Patents

Description

  The present invention relates to a logic verification method and a logic verification system in logic design.

  Improving the efficiency of verification is also an important issue in order to cope with the large scale and multi-functionality of logic circuits. Formal logic verification is known as one of logic verification methods.

  Formal logic verification defines the expected and prohibited operations of a logic circuit as properties, and checks whether the logic circuit to be verified is designed not to violate the properties. It is.

  A property defines the behavior of an input pattern and the expected output value associated therewith. Specifically, “a signal is output within 3 cycles after a certain signal is input” and “two signals never become“ 1 ”at the same time”.

  As a method of formal logic verification having a property detection function, a behavioral synthesis tool synthesizes an RTL (Register Transfer Level) circuit description from a behavioral level circuit description. Further, the property generation unit generates a behavior level property from the behavior level circuit description. Subsequently, the property conversion unit converts the generated behavior level property into an RTL property. A property generation system in which a model checking unit verifies an RTL circuit description by using a model checking technique using an RTL property is known (see Patent Document 1).

JP2009-230677

  The above-described conventional technique extracts properties from a description with a high degree of abstraction such as C language in a design using a behavioral synthesis tool, and converts the extracted properties into RTL properties.

  However, with the conventional technology, it is possible to extract properties from the logic description format, but all the verification items cannot be satisfied with the extracted properties alone, and comprehensive verification is performed on the verification circuit. Because of that. Therefore, it is necessary to generate properties comprehensively, but this involves a lot of time and human costs.

  The present invention has been made in view of such problems, and provides a logic verification method and a logic verification apparatus capable of efficiently generating properties that are inspection items in logic verification.

  According to one embodiment of the present invention, a first procedure for acquiring logic and a first property that is a verification item for verifying the logic, and events occurring in the first property are arranged in time series. A second procedure for creating a time series table, a third procedure for creating a second property representing the reverse, reverse or even number of verification items based on the first property and the time series table; And a fourth procedure for verifying the logic using the first property and the created second property.

  According to the present invention, since the second property meaning reverse, reverse, even number is created based on the first property created by the verifier, the logical property can be generated by exhaustively generating a plurality of properties. The verification quality of verification can be improved. Furthermore, time and human costs in logic verification can be reduced.

It is a block diagram of the logic verification assistance part of the 1st Embodiment of this invention. It is a flowchart of the logic device design in the 1st Embodiment of this invention. It is a block diagram which shows the hardware constitutions of the logic verification assistance system of the 1st Embodiment of this invention. It is explanatory drawing of an example of the property of the 1st Embodiment of this invention. It is explanatory drawing of an example of the property language of the 1st Embodiment of this invention. It is explanatory drawing of an example of the operator used by the property of the 1st Embodiment of this invention, and a function. In 1st Embodiment of this invention, it is explanatory drawing of the difference in the verification content by each property of the reverse, back, and even number with respect to a proposition property. It is a flowchart of the logic verification process of the 1st Embodiment of this invention. It is a flowchart of the time series table preparation process of the 1st Embodiment of this invention. It is explanatory drawing of an example of the delay time table of the 1st Embodiment of this invention. It is a table | surface which shows an example of the function conversion table of the 1st Embodiment of this invention. It is explanatory drawing which shows the delay time table after converting the function of the 1st Embodiment of this invention. It is explanatory drawing of an example of the time series table of the 1st Embodiment of this invention. It is a flowchart which shows the production | generation method of the reverse property of the 1st Embodiment of this invention. It is explanatory drawing of an example of the delay time table of the 1st Embodiment of this invention. It is explanatory drawing of an example of the delay time table of the 1st Embodiment of this invention. It is explanatory drawing of the production | generation of the reverse property of the 1st Embodiment of this invention. It is explanatory drawing of the production | generation of the back property of the 1st Embodiment of this invention. It is explanatory drawing of the production | generation of the even number property of the 1st Embodiment of this invention. It is explanatory drawing of the formal logic verification of the 1st Embodiment of this invention. It is a flowchart of the formal logic verification of the 1st Embodiment of this invention. It is a block diagram of the logic verification assistance part of the 2nd Embodiment of this invention. It is a block diagram of the logic verification assistance part of the 3rd Embodiment of this invention.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of the logic verification support unit 10 of this embodiment.

  The logic verification support unit 10 of the present embodiment is a device that performs formal logic verification on a logic circuit of a logic device designed by an operator using properties.

  Formal logic verification defines the expected behavior or prohibited behavior of a logic circuit as a property, and checks whether the logic circuit to be verified is designed not to violate the property. Is.

  The logic verification support unit 10 includes an input reception unit 101, a table creation unit 102, a property generation unit 103, a verification unit 104, and a verification result output unit 105.

  The input receiving unit 101 receives input of property data and commands from the operator. The table creation unit 102 creates a time series table to be described later from the input properties.

  The property generation unit 103 generates properties having the meanings of reverse, reverse, and even even with the property input by the operator as a proposition.

  The verification unit 104 verifies the property. The verification result output unit 105 outputs a property verification result.

  FIG. 2 is a flowchart of logic device design to which formal logic verification in this embodiment is applied.

  In the logical device design, the operator executes the method review (S300) for examining the method of the logical device, executes the function review (S301) for examining the function for realizing the method, and performs the logic to realize the function. The logic design (S302) describing is executed. In logic design, logic described by RTL (Register Transfer Level) is created.

  Next, the operator executes logic verification (S303) in order to formally verify the created RTL. In step S303, the logic verification support unit 10 executes formal logic verification using properties to be described later.

  After the logic verification is completed and the validity of the RTL is confirmed, the logic synthesis (S304) for synthesizing the RTL to the gate level is executed, and the implementation (S305) for arranging the created gate in the actual device is executed. .

  A logical device is designed by such a procedure.

  FIG. 3 is a block diagram showing a hardware configuration of the logic verification support system 11 that implements the logic verification support unit 10 of the present embodiment.

  The logic verification support system 11 includes a CPU 111, a memory 112, an HDD 113, an input / output interface 114, a display unit 117, and an input unit 118. The CPU 111, the memory 112, the HDD 113, and the input / output interface 114 are connected to each other via a bus 115.

  The CPU 111 is a control unit that controls the logic verification support system 11. The CPU 111 reads the logic verification support program 116 stored in the HDD 113 onto the memory 112 and executes it. The logic verification support unit 10 is executed when the CPU 111 executes the logic verification support program 116.

  The memory 112 is constituted by a DRAM, for example. The memory 112 temporarily records the logic verification support program 116 and data and tables used for the execution of the logic verification support program 116.

  The HDD 113 is configured by a magnetic disk drive, for example. The HDD 113 records programs, data, and the like executed by the logic verification support system 11. For example, the RTL of the logic circuit subject to logic verification, the function conversion table 130 representing the cycle delay of operators, functions, etc. are stored in advance by the operator. The memory 112 and the HDD 113 constitute a storage unit.

  The input / output interface 114 displays information related to the operation of the logic verification support unit 10 on the display unit 117. The input / output interface 114 transmits information input to the input unit 118 by an operator or the like to the logic verification support unit 10.

  Note that the display unit 117 and the input unit 118 may be configured to transmit and receive data to and from other computers and storages via a network or the like. The logic verification support system 11 may be configured to input data from another computer or display the result on another computer.

  Next, formal logic verification executed by the logic verification support unit 10 will be described.

  In the formal logic verification, a verification item called a property is created for the logic RTL created in step S302 of FIG. 2, and the logic of the RTL is verified using this verification item. As a result, the validity and equivalence of the RTL logic is verified.

  FIG. 4 is an explanatory diagram of an example of the property of the present embodiment.

  The property describes that when a certain signal is a condition represented in the hypothesis part, the result represented in the consequent part is obtained.

  A table 60 shown in FIG. 4 shows an example of a property described in a natural language. A column 61 describes a property type and a column 62 describes a property content.

  This table 60 indicates what kind of reverse property, reverse property, or even number property is for the proposition property. The definitions of the reverse property, the reverse property, and the even number property are equivalent to the reverse, reverse, and even number in mathematical logic.

  If the proposition property is “if A, then it is B”, then the inverse property is in the form of “if B, it is A” by replacing the hypothesis part and the consequent part.

  The kinematic property takes the form of “if it is not B, it is not A” in which the assumption part and the result part of the proposition property are interchanged and each of the assumption part and the result part is a negative form.

  Further, the back property takes the form of “if it is not A, it is not B” with the assumption part and the consequence part of the proposition property being negative.

  In formal logic verification in this embodiment, logic verification is executed by using such properties.

  FIG. 5 is an explanatory diagram of an example of the property language of the present embodiment.

  The example shown in FIG. 4 is a description of properties in natural language. On the other hand, the property is handled by the property language in the logic verification support unit 10.

  That is, the property is described in a property language such as SVA (System Verilog Association) or PSL (Property Specific Language). In the present embodiment, description in the SVA language is used for explanation, but it does not depend on the SVA language, and other property languages may be used.

  In the table 70 shown in FIG. 5, a property type is described in a column 71, a property expressed in a natural language is described in a column 72, and a property notation in a property language is described in a column 73.

  In this table 70, if the propositional property in the natural language is “If A, it is B after one cycle”, the description in the property language is “(A == 1)” as a hypothesis. The part “## 1 (B == 1)” is combined with the implication operator “|->”. Note that “##” (cycle delay operator) and “|->” (implication operator) will be described with reference to FIG.

  Further, the back property of this proposition property is a negative form of the hypothesis part and the consequent part, and in a natural language, “if it is not A, it is not B after one cycle”. In addition, what is described in the property language is a description in which an operator “!” Representing negation is added to the assumption part and the result part of the property language.

  The logic verification support unit 10 executes processing based on the property language input by the operator. In the present embodiment, the notation in natural language is also described for ease of explanation.

  FIG. 6 is an explanatory diagram of an example of operators and functions used in the properties of this embodiment.

  The property language represents signal names and signal values using implication operators, functions, delay times, and the like.

  In the table 90 shown in FIG. 6, a symbol in the property language is described in a column 91, and a meaning of the symbol is described in a column 92.

  In this table 90, the implication operator is an operator that is represented by a symbol “|->” or “| =>” and represents an assumption part and a consequent part. “|->” Represents “if it is, then becomes”. Further, “| =>” represents “if it is, then becomes after one cycle”.

  The cycle delay is expressed in the form “## n”, where “## n” is an operator indicating “after n cycles”.

  The function represents a change in the state of the signal. For example, “$ past” represents the past, and “$ rose” represents the rise of a specific signal.

  “!” Is an operator representing negation.

  The property represents the result of the signal in the consequent part according to the condition of the signal represented in the hypothesis part by such a combination of operators and functions.

  The logic verification uses this property to verify the RTL of the design circuit.

  FIG. 7 is an explanatory diagram of the difference in verification contents according to the reverse, reverse, and even properties for the proposition property in this embodiment.

  The table 80 shown in FIG. 7 describes the contents of verification that can be performed in the property language in the column 81, the proposition property in the column 82, the reverse property in the column 83, the back property in the column 84, and the even property in the column 85. Is done.

  This table 80 explains the difference in the verification contents of the reverse property, the back property, and the even property, taking as an example the case where the proposition property is “A == '1' |-> B == '1'”.

  This proposition property indicates that when “A == 1”, the value of B is verified.

  However, due to the nature of formal logic verification, verification is not executed when “A == 1” in the first place. Therefore, verification when “A == 0” cannot be executed.

  Further, even if it can be proved that “B == 1 if A == 1”, it cannot be verified what value A is when B == 1. That is, the influence of the third signal that is neither A nor B cannot be verified.

  Therefore, in order to verify when “A == 1 is not true”, it is necessary to generate a back property. In order to verify when “B == 1”, it is necessary to generate an inverse property.

  Thus, since it is difficult to comprehensively verify a signal with one proposition property, it is necessary to create many properties for logical verification.

  The proposition property, the reverse property, the back property, and the even property have different verification contents. Therefore, conventionally, in order to realize exhaustive verification, an operator creates these properties according to the nature of design logic. This involves a lot of labor, and when a property is created manually, it is necessary to further verify that the property is correct, resulting in a lot of time and human costs.

  Therefore, in the present embodiment, for the proposition property created by the operator, a property meaning reverse, reverse and even number is automatically created, and logical verification is executed by each of these properties, thereby performing formal logic verification. It was configured to be able to perform efficiently.

  Next, the operation of the logic verification support unit 10 will be described.

  FIG. 8 is a flowchart of the logic verification process executed by the logic verification support unit 10 of this embodiment.

  The logic verification support unit 10 has a function of generating properties having the meanings of reverse, reverse, and even with the property created by the verifier as a proposition, and performing formal logic verification using the generated property.

  When the logic verification process is executed, the logic verification support unit 10 receives input of the logic to be verified, the proposition property that is a verification item for verifying the logic, and the conversion designated value (S201).

  The input reception unit 101 of the logic verification support unit 10 receives the RTL of the logic circuit to be verified, the property created by the operator, and information on which of the reverse, reverse, and even properties are generated. The input receiving unit 101 can receive information on a plurality of properties as input. These are temporarily recorded in the memory 112.

  The conversion specification value is a value that specifies whether to convert a property (first property) as a proposition to a reverse property, reverse property, or even property (second property). In the present embodiment, 1 is specified when designating the conversion to the reverse property, 2 is designated when designating the conversion to the even property, and 3 is designated when designating the back property. If neither property is specified, 0 is specified.

  Next, when there are a plurality of input properties, the logic verification support unit 10 determines whether all the properties have been verified (S202). If it is determined that all the properties have been verified, the logic verification support unit 10 ends the process according to this flowchart.

  If it is determined that at least one of the plurality of properties has not been verified, the logic verification support unit 10 proceeds to step S202, selects one of the input properties that has not been verified, and selects the selected property. Get a proposition property and a conversion specification value corresponding to the selected property.

  Next, the logic verification support unit 10 creates a time series table (S203). The table creation unit 102 of the logic verification support unit 10 converts the signal from the acquired property into a table corresponding to the change of the time axis. This process will be described later with reference to FIG.

  Next, the logic verification support unit 10 determines which of the conversion designation values corresponding to the property for which the time series table has been created (S204).

  When the conversion designation value is 1, that is, when the generation of the reverse property is instructed, the process proceeds to step S205.

  When the conversion designation value is 2, that is, when the generation of the even property is instructed, the process proceeds to step S206.

  If the conversion designation value is 3, that is, if generation of the back property is instructed, the process proceeds to step S214.

  If the conversion specification value is 0, it means that conversion to any property is not instructed for the proposition property. In this case, the process proceeds to step S220 without proceeding to step S205, S206, or step S214.

  When generation of the reverse property is instructed in step S204, the process proceeds to step S205, and the logic verification support unit 10 reads the time series table created in step S203 from the reverse of the time series. An inverse property is created by this processing (S210).

  If generation of the even property is instructed in step S204, the process proceeds to step S206, and the logic verification support unit 10 reads the time series table created in step S203 from the reverse of the time series. An inverse property is created by this processing (S210). Next, the logic verification support unit 10 converts each of the assumption part and the result part of the inverse property into a negative form (S212). By this process, an even number property is generated (S213).

  If generation of the back property is instructed in step S204, the process proceeds to step S214, and the logic verification support unit 10 converts each of the hypothesis part and the consequent part into a negative form for the property acquired in step S202. A back property is created by this processing (S215).

  After creating the reverse property, the even property, or the back property, the process proceeds to step S220, and the logic verification support unit 10 executes formal logic verification. Then, it returns to step S201 and repeats the process after S201. This process will be described later with reference to FIG.

  Next, generation of a time series table by the table creation unit 102 will be described.

  FIG. 9 is a flowchart of time-series table creation processing executed by the table creation unit 102 of the logic verification support unit 10 of this embodiment.

  First, the table creation unit 102 pays attention to the input proposition property implication operator and the sequence operator representing the cycle delay, and extracts a character string delimited by them as a signal event (S1).

For example,
(A == 1) |->## 1 (B == 1); (If A == '1', B == '1' after one cycle)
In the case of the property, the character string excluding the implication operator “|->” and the sequence operator “## 1” is “A == 1” and “B == 1”. Extracts these as events that cause a change in the state of the signal.

  Next, the table creation unit 102 extracts the event extracted in step S1 and the delay time described in the property, and generates a delay time table 120 representing the correspondence between the event and the delay time ( S2).

  FIG. 10 is an explanatory diagram of an example of the delay time table 120 created by the table creation unit 102 of this embodiment.

The example shown in FIG.
$ Rose (ready) ## 10 $ rose (request) |->## 1 cnt == $ past (cnt, 1) +1; (If request rises after 10 cycles from ready rise, one cycle after request (The cnt value becomes the cnt value +1 before one cycle.)
An example of the proposition property will be described.

  In the delay time table 120 shown in FIG. 10, the contents of an event, that is, a signal name and its value, a function, and a sequence operator are described in a column 121. Column 122 describes the delay time of the event, that is, the timing of how long the event occurs from the start of verification.

  In the delay time table 120, the function “$ rose (ready)” occurs 0 and 1 cycle after the start of verification of this event. The operator “## 1” occurs 11 cycles after the start of verification of this event.

  In this way, the table creation unit 102 creates the delay time table 120 by associating events and event occurrence timings as delay times from the proposition properties.

  Returning to FIG. 9, the table creation unit 102 detects whether a function exists in the column 121 of the delay time table 120 generated in step S2. If a function exists, the function is converted into a notation based on a change in signal (S3). A function conversion table 130 is used for this function conversion.

  The logic verification support unit 10 stores a function conversion table 130 in advance. The function conversion table 130 is a table in which functions are associated with cycle delays and signal changes. In the logic verification support system 11, the function conversion table 130 is stored in advance in the HDD 113 or the memory 112.

  FIG. 11 is a table showing an example of the function conversion table 130 of the present embodiment.

  In the function conversion table 130 shown in FIG. 11, the function notation is described in the column 121 and the function is described in the column 132 as the cycle delay notation.

  In the function conversion table 130, it is indicated that the function “$ rose (A)” representing the rising edge is associated with a combination of “A == 0” and “## 1 A == 1”. That is, the function “$ rose (A)” indicates that the value of the signal A at the start is 0, and the value of the signal A changes to 1 after one cycle.

  In addition, “$ fell (A)” indicating the falling edge is associated with a combination of “A == 1” and “## 1 A == 0”.

  The table creation unit 102 refers to the function conversion table 130 and converts the function into a cycle delay notation when the proposition property includes a function recorded in the function conversion table.

  The contents of the function conversion table 130 are not limited to the functions as shown in FIG. Sequence operators such as [* n] (continuous repetition), [= n] (non-continuous repetition), and [-> n] (goto repetition) may be converted.

  FIG. 12 is an explanatory diagram showing the delay time table 120 after the function is converted by the table creation unit 102 of the present embodiment.

  In the example of FIG. 12, the delay time table shown in FIG. 10 is created by converting a function by referring to the function conversion table shown in FIG.

  The function “$ rose (ready)” shown in the column 121 of FIG. 10 is converted into two notations of “ready == 0” and “ready == 1” based on the function conversion table 130 of FIG. Each has a delay time.

  Similarly, the function “$ rose (request)” is converted into two notations “request == 0” and “request == 1” based on the function conversion table 130 of FIG. Is applied.

  By such processing, the table creation unit 102 converts the property into a delay time table 120 corresponding to the event and the delay time as shown in FIG.

  Returning to FIG. 9, next, the table creation unit 102 generates the time series table 20 based on the table created in step S3.

  The table creation unit 102 creates the delay time table shown in FIG. 10 from the properties, and creates the delay time table 120 shown in FIG. 12 by dividing the functions of this table. The table creation unit 102 creates a time series table 20 in which the delay time of the delay time table 120 is represented as a time series, and at which timing which event occurs as a time series table.

  FIG. 13 is an explanatory diagram of an example of the time series table 20 of the present embodiment.

  FIG. 13 shows an example of the time series table 20 generated from the table 120 shown in FIG.

  Table 120 shows events with a delay time between 0 and 12 cycles. Therefore, the time between 0 and 12 is set as a time series.

  The time series table 20 includes an item number 21 and a signal name 22.

  The table creation unit 102 assigns signal names included in events in chronological order. Since the table 120 includes signals “ready”, “request”, and “cnt”, each signal name is recorded corresponding to the time at which the signal in the time series table 20 is generated. Item numbers are assigned in the order of events that occur.

  In the example of FIG. 13, “1” of item number 21 is applied to “ready”, “2” of item number 21 is applied to “request”, and “3” of item number 21 is applied to “cnt”.

  The signal “ready” has a value “0” at time 0 and a value “1” at time 1.

  The signal “request” has a value “0” at time 10 and a value “1” at time 11.

  Further, the signal “cnt” is a self-reference “X” at time 11 and is “X + 1” obtained by adding 1 to this value at time 12.

  The table creation unit 102 records the value that is the result of the event at each corresponding time. A portion where there is no signal change is left blank.

  By such processing, the table creation unit 102 creates the time series table 20.

  Returning to FIG. 9, the table creation unit 102 executes a process of determining an assumption part and a result part in parallel with the creation of the time series table 20 including a time series and a signal (S <b> 5).

  The hypothesis part and the consequent part are determined by detecting the implication operator. The table creation unit detects the right side and the left side sandwiching the implication operator from the properties, and determines the left side as an assumption unit and the right side as a consequent unit.

  The description in the property language described above is “$ rose (ready) ## 10 $ rose (request)” on the left side of the implication operator.

  Further, the right side is “## 1 cnt == $ past (cnt, 1) +1”, which is a consequent part.

  The left side is converted into a signal “ready” and a signal “request” by the processing in steps S2 and S3 described above. Therefore, the table creation unit 102 detects that the factors of the assumption part are “ready” and “request”.

  Further, since the right side is a description of only the signal “cnt”, the table creation unit 102 detects that the factor of the consequent part is the signal “cnt”.

  From this detection result, the table creation unit 102 creates a result expression that expresses the relationship between the hypothesis part and the result part as an arithmetic expression using signals from this detection result (S6).

  In the example detected in step S5, the consequent formula is “cnt = ready * request”. This means that when the signal “cnt” is verified, the signal “ready” and the signal “request” are assumed parts. Represents.

  The table creation unit 102 records the result formula created in step S6 in the result formula row 23 of the time series table 20 (S7). At this time, the table creation unit 102 expresses the consequent expression by the item number corresponding to the signal name when filling in.

  In the table 120, since the signal “cnt” is a logical product of the signal “ready” and the signal “request”, the resulting equation is described as “3 = 1 * 2” by the number of each item number 21. .

  Next, the table creation unit 102 records the reverse time 24 in the time series table 20 (S8). The reverse time 24 is described by counting the time series from the time when the last event in the time series occurs to the start time until the verification start time. This reverse time 24 is used for the process of generating the reverse property.

  Through the processing as described above, the table creation unit 102 creates the time series table 20 from the proposition properties. The created time series table 20 is recorded in the memory 112. The time series table 20 is used for the generation process of the reverse property or the even property described below.

  Next, generation of inverse properties will be described.

  Based on the proposition property, the property generation unit 103 generates properties that mean reverse, reverse, and even numbers based on the time series table 20 output from the table creation unit 102. Here, generation of inverse properties will be described.

  FIG. 14 is a flowchart showing the inverse property generation method of this embodiment.

  The property generation unit 103 first extracts the signal name 22, the signal value, and the reverse time 24 with reference to the time series table 20 (S11). The extracted signal name 22, signal value, and reverse time 24 are created as a delay time table 120.

  FIG. 15 is an explanatory diagram of an example of the event and delay time table 120 created in step S11 of the present embodiment.

  The property generation unit 103 writes the event and its value acquired from the time series table 20 and the time at which the event occurs in the delay time table 120.

  Note that since the delay time column 122 extracts the reverse time, it may be negative.

  Next, the property generation unit 103 refers to the function conversion table 130 shown in FIG. 11 described above with respect to the created delay time table 120, so that the signal sequence can be converted into a function. It is determined whether or not it can be converted to (S12).

  The property generation unit 103 determines whether the function can be functionalized by comparing the signal change pattern in the column 121 with the function conversion table 130.

  The property generation unit 103 performs functionalization on the sequence of signals determined to be functionalizable in step S12 (S13).

  Then, the property generation unit 103 converts the event into a function, and then creates a table indicating the correspondence between the event and the delay time (S14).

  FIG. 16 is an explanatory diagram illustrating an example of the delay time table 120 created by the property generation unit of the present embodiment in step S14.

  The property generation unit 103 converts the event into a function with reference to the delay time table 120 shown in FIG.

  Specifically, the property generation unit 103 has “cnt == x + 1” when the delay time is “0” and “cnt == x” when the delay time is “−1”. Referring to the function conversion table 130, “cnt == $ past (cnt, 1) +1” (“cnt” when the delay time is “0” is obtained by incrementing “cnt” one cycle before by “+1”. There is a function.

  Similarly, the property generation unit 103 has “request == 1” when the delay time is “−1” and “request == 0” when the delay time is “−2”. Then, referring to the function conversion table 130, the function is converted into “$ past ($ rose (request), 1)” (“request” rises when the delay time is “−1”).

  Further, since the property generation unit 103 has “ready == 0” when the delay time is “−11” and “ready == 0” when the delay time is “−12”, Referring to the function conversion table 130, the function is converted to “$ past ($ rose (ready, 11))” (“ready rises when the delay time is“ −11 ”).

  These functionalized events are recorded in the delay time table 120 (FIG. 16) having the same format as that shown in FIG.

  On the other hand, since the inverse property is obtained by inverting the hypothesis part and the consequent part with respect to the proposition property, the signal relationship between the hypothesis part and the consequent part obtained from the consequent expression 23 of the time series table 20 is inverted. Thus, the reverse property can be generated.

  Using this, the property generation unit 103 performs a process of inverting the signal relationship between the hypothesis part and the consequent part of the consequent expression 23 (S15).

  Referring to the time series table 20 shown in FIG. 13, the result is 3 = 1 * 2, which assumes that the signal “ready” and the signal “request” are used when the value of the signal “cnt” is verified. It represents that becomes.

  The property generation unit 103 inverts the assumption part and the consequent part to obtain the consequent expression “1 * 2 = 3”. This indicates that the signal “cnt” is assumed when the values of the signal “ready” and the signal “request” are verified.

  Next, the property generation unit 103 generates an inverse property by combining the table created in step S14 and the consequent expression obtained in step S15 (S16). Specifically, each event described in the table and its delay time are applied to the consequent formula, and this is recorded as an inverse property.

  By the process of step S16, the generation of the reverse property is completed.

  FIG. 17 is an explanatory diagram of reverse property generation executed by the property generation unit 103 of this embodiment.

  FIG. 17A shows an example in which proposition properties are described in a natural language and a property language corresponding to the proposition property.

  The table creation unit 102 analyzes this property language and creates the time series table 20 by the processing of FIG. 9 described above. FIG. 17B is an example of the time series table 20 corresponding to the property language of FIG.

  The property generation unit 103 refers to the time series table 20 and the property language of the proposition property, and generates an inverse property by the process of FIG. 14 described above.

  FIG. 17C is an example in which the inverse property generated for the proposition property shown in FIG. 17A is described in a natural language and a corresponding property language.

  Next, generation of the back property will be described.

  The property generation unit 103 generates an inverse property based on the time series table 20 output from the table creation unit 102 based on the proposition property as described above.

  On the other hand, the reverse property is generated by adding “!” Representing negation to the property language of the proposition property.

  FIG. 18 is an explanatory diagram of back property generation executed by the property generation unit 103 according to the present embodiment.

  FIG. 18A shows a proposition property described in a natural language and a property language corresponding thereto.

  When creating a back property from this property description, the property generation unit 103 detects an assumption part and a consequent part by an implication operator. Note that the hypothesis part and the consequent part may be detected with reference to the time series table 20 already created.

  Next, the property generation unit 103 adds “!” Representing negation to each event described in the assumption unit and the consequent unit.

  FIG. 18B is an example in which the back property generated for the proposition property shown in FIG. 18A is described in a natural language and a corresponding property language.

  The negative meaning is an instruction for an operation other than the operation of the corresponding event.

  For example, the negative form of “$ rose (ready)” (when ready is set up) is “! $ Rose (ready)” (when ready is not set up).

  Specifically, it means a state where the value of “ready” is maintained at “0”, a state where “1” is maintained, and a state where the value falls from “1” to “0”. It becomes.

  Similarly, the negative form of “cnt == $ past (cnt, 1) +1” (the cnt value should be cnt value + 1 before one cycle) is “! (Cnt == $ past (cnt, 1) +1”. ) "(The cnt value is not the cnt value of the previous cycle + 1). This satisfies all the conditions if the value of “cnt” is a value other than the value “cnt” of the previous cycle plus one.

  Next, generation of the even property will be described.

  The kinematic property is generated by inverting the hypothesis part and the consequent part with respect to the proposition property, and further adding “!” Representing a negative form to all the events. That is, as described above, an inverse property is generated based on the time series table 20 output from the table creation unit 102 based on the proposition property, and the inverse property is converted into a reverse property, thereby generating an even property. .

  FIG. 19 is an explanatory diagram of the generation of the even property executed by the property generation unit 103 of this embodiment.

  The reverse property is generated by the processing shown in FIGS. 9 and 14 as described above. Further, as shown in FIG. 18, the back property is generated by adding “!” Representing a negative form to each event.

  FIG. 19A shows an example in which proposition properties are described in a natural language and a property language corresponding to the proposition property.

  The table creation unit 102 analyzes this property language and creates the time series table 20 by the processing of FIG. 9 described above. FIG. 19B is an example of a time series table 20 corresponding to the property language of FIG.

  The property generation unit 103 refers to the time series table 20 and the property language of the proposition property, and generates an inverse property by the process of FIG. 14 described above.

  FIG. 19C is an example in which the inverse property generated for the proposition property shown in FIG. 19A is described in a natural language and a property language corresponding thereto.

  Further, as described in FIG. 18, the property generation unit 103 adds “!” Representing negation to each event described in the hypothesis unit and the consequent unit for the generated reverse property.

  FIG. 19D is an example in which the even property generated for the proposition property shown in FIG. 19A is described in a natural language and a corresponding property language.

  Through the processing described above, the logic verification support unit 10 can automatically generate properties that mean reverse, reverse, and even numbers from proposition properties.

  Next, formal logic verification will be described.

  The verification unit 104 is a function that performs formal logic verification by inputting a proposition property input by the operator or an inverse property, a reverse property, and an even property generated by the property generation unit 103.

  FIG. 20 is an explanatory diagram of formal logic verification executed by the verification unit 104 of this embodiment.

  Formal logic verification compares the logic cone extracted from the netlist to be verified with the logic cone extracted from the expected value to be verified, and verifies their equivalence to verify the correctness of the logic circuit. Is a method to mathematically prove

  The logic cone is obtained by replacing the logic with an equivalent circuit having a combination circuit network having FF (Flip Flop) as a vertex.

  The verification unit 104 extracts a logic cone using the RTL of the logic circuit as a netlist to be inspected. Similarly, the logic cone is extracted from the expected value of the inspection object based on the property.

  Then, the verification unit 104 compares the logic cone to be verified with the logic cone that is the expected value, and verifies their equivalence.

  As a method for verifying equivalence, a conventionally known method such as OBDD (Ordered Binary Decision Diagram) can be used. Note that the method of performing formal logic verification is not limited to this.

  In the example illustrated in FIG. 20, the verification unit 104 includes a logic cone 31 that is a combination of the FF30, FF30-1, and FF30-2 of the logic circuit, and an FF30-3 that represents an expected value based on the generated property. An example of verifying the comparison with the logic cone 31-1 that is a combination of the FF 30-4 and the FF 30-5 will be described.

  FIG. 21 is a flowchart of formal logic verification executed by the verification unit 104 of this embodiment.

  When formal logic verification is started, the verification unit 104 first inputs the RTL of the logic to be verified from the input unit 118 and the inverse, reverse, and even property generated by the proposition property or property generation unit 103. Is received (S101).

  Next, the verification unit 104 executes a process of extracting a logic cone that is an expected value from the property and a process of extracting an RTL logic cone of the logic circuit (S102).

  Next, the verification unit 104 compares the logic cone of the expected value extracted in step 102 with the logic cone of the design circuit (S103). Then, as a result of the comparison, it is determined whether or not the logic cone is equivalent (S104).

  As a result of the comparison, when it is recognized that the logic cones are equivalent, the process proceeds to step S105, and the verification unit 104 confirms that the designed logic circuit operates as expected. This result is output to the verification result output unit 105.

  On the other hand, if it is recognized that the results are not equivalent, it means that there is an error in the designed logic or the property itself. In this case, the verification unit 104 notifies an error from the verification result output unit 105. At this time, debug information can be presented through the verification result output unit 105 by generating a combination waveform (a counter example waveform) inconsistent with the expected value from the logic cone.

  Formal logic verification is completed by such processing.

  As described above, in the embodiment of the present invention, the logic verification support unit 10 obtains the logic of the design circuit and the proposition property that is the first property that is the verification item for verifying the logic, Based on the proposition property and the time series table 20, the reverse, reverse or even number of the proposition properties is determined based on the proposition property and the time series table 20. A property generation unit 103 that creates a second property that means, a verification unit 104 that verifies logic using a proposition property, an inverse property, a back property, or an even property, and a verification result output that outputs a verification result of the verification unit 104 Unit 105.

  With such a configuration, a second property that means reverse, reverse, or even number can be created from the proposition property prepared by the operator. Thereby, a plurality of properties can be automatically generated, and the properties can be generated comprehensively, so that the verification quality of logic verification can be improved. Furthermore, time and human costs in logic verification can be reduced and logic verification can be performed efficiently.

  Next, a second embodiment of the present invention will be described.

  The logic verification support unit 10 according to the second embodiment has a function of generating properties representing reverse, reverse, and even numbers from the proposition properties and verifying the proposition properties as well as a function of verifying the properties.

  FIG. 22 is a block diagram of the logic verification support unit 10 of this embodiment. In addition, the same structure as 1st Embodiment attaches | subjects the same code | symbol, and the description is abbreviate | omitted.

  As described above with reference to FIG. 1, the logic verification support unit 10 includes an input reception unit 101, a table creation unit 102, a property generation unit 103, a verification unit 104, and a verification result output unit 105.

  The logic verification support unit 10 includes a table output unit 201. The table output unit 201 has a function of displaying the time series table 20 generated by the table creation unit 102 on the display unit 117.

  The time series table 20 output from the table output unit 201 is the time series table 20 illustrated in FIG. Since the time series table 20 does not display signals and their values that are not declared in the property, it is easy for the operator to visually determine the consistency of the property.

  Therefore, by displaying the time series table 20 by the table output unit 201, the operator can use it as a method for debugging whether or not the intended property is generated.

  Next, a third embodiment of the present invention will be described.

  The logic verification support unit 10 according to the third embodiment displays a time series table 20 of the reverse, reverse, and even properties generated in addition to the function for visually confirming the proposition property as in the second embodiment described above. Also has a display function.

  FIG. 23 is a block diagram of the logic verification support unit 10 of this embodiment. In addition, the same structure as 1st and 2nd embodiment attaches | subjects the same code | symbol, and the description is abbreviate | omitted.

  The logic verification support unit 10 includes a table output unit 201 and a table creation unit 202. The table output unit 201 has a function of displaying the time series table 20 generated by the table creation unit 102 on the display unit 117.

  The table creation unit 202 has a function of creating the time series table 20 of the reverse, reverse, and even properties generated by the property generation unit 103.

  Similar to the second embodiment, the table output unit 201 displays the time series table 20 created based on the proposition properties.

  Further, the table output unit 201 displays the time series table 20 of reverse, reverse and even properties created by the table creation unit 202.

  By doing in this way, the operator can visually confirm the time series table 20 of the reverse, reverse, and even property created automatically by the logic verification support unit 10. This makes it easy to share properties between operators.

  Further, the time series table 20 output by the table output unit 201 may be registered in the external database together with the generated property. This makes it possible to perform the property verification work by comparing the equivalences of the time series table 20 and extracting properties having different property language notations but the same verification contents.

10 logic verification support unit 11 logic verification support system 20 time series table 101 input reception unit 102 table creation unit 103 property generation unit 104 verification unit 105 verification result output unit 111 CPU
112 Memory 113 HDD
114 Input / output interface 115 Bus 116 Logic verification support program 117 Display unit 118 Input unit 201 Table output unit 202 Table creation unit

Claims (8)

In a logic verification system comprising a control unit for executing a program, a storage unit, an input unit, and a display unit for displaying information , the logic is verified using a first property that is a verification item for verifying the logic. A logical verification method to
Obtaining logic input from the input unit, the first property input from the input unit, and a conversion specification value that is input from the input unit and specifies a proposition generated from the first property A first procedure for recording in the storage unit;
A second procedure for creating a time-series table representing events occurring in the first property in time series from the first property, and recording the created time-series table in the storage unit;
A procedure for generating a second property corresponding to a proposition designated by the conversion designated value and recording the generated second property in the storage unit, wherein the first property is produced by the conversion designated value. When the opposite of the above or the even number is specified, the second property is generated based on the first property and the time series table, and the reverse side of the first property is specified by the conversion specification value Generating a second property based on the first property in a third procedure;
A fourth procedure for verifying the logic using each of the first property and the created second property;
Equipped with a,
The second procedure is:
Extracting an assumption part and a consequence part by detecting an operator included in the first property;
For each of the extracted assumption part and the consequent part, a procedure for acquiring a change in the signal that is the content of the event and a time at which the change occurs;
Creating the time series table representing the change of the signal in a time series based on the time, and recording the created time series table in the recording unit;
Creating a consequence formula representing the relationship between the hypothesis part and the consequence part, and recording the created outcome formula in the time series table;
Creating a reverse time that is a reverse time series from the last time represented in the time series to a start time, and recording the created reverse time in the time series table;
A procedure for displaying the created time series table on the display unit;
Including
The third procedure is:
A procedure for creating a new time series table that represents a change of the signal in the generated second property in a time series based on the time, and displaying the created new time series table on the display unit
Logic verification method characterized by comprising a.   The second procedure further converts the function into a representation of the signal, the change in the signal, and the time when the change in the signal obtained from the first property is expressed as a function. The logic verification method according to claim 1, further comprising a procedure.   The third procedure is:
  Obtaining the signal, the change of the signal, the time, and the reverse time from the time series table;
  From the time series table, the result formula is acquired, and converted into a new result formula obtained by replacing the assumption part and the result part of the acquired result formula;
  Applying the signal, the change in the signal, and the time to the new consequent formula, the second property that means the opposite is created, and the created second property that means the opposite is stored in the storage unit Recording procedure,
The logic verification method according to claim 1, further comprising:   The third procedure creates the second property that means the reverse by converting the hypothesis part and the result part of the first property into negative forms, respectively, and the second property that means the created reverse The logic verification method according to claim 1, further comprising a procedure of recording a property in the storage unit.   The third procedure is:
  Obtaining the signal, the change of the signal, the time, and the reverse time from the time series table;
  From the time series table, the result formula is acquired, and converted into a new result formula obtained by replacing the assumption part and the result part of the acquired result formula;
  Applying the signal, the change in the signal and the time to the new consequence formula to create the second property, which means the opposite;
  The hypothetical part and the consequent part of the second property that mean the reverse created are converted into negative forms, respectively, the second property that means the even number is created, and the second property that means the created even number Recording properties in the storage unit;
5. The logic verification method according to claim 1, further comprising:   The fourth procedure includes:
  Creating a logic cone based on the logic and an expected value logic cone based on the first or second property;
  Determining whether the result of the logic cone and the result of the logic cone of the expected value are equivalent;
The logic verification method according to claim 1, further comprising:   7. The logic verification method according to claim 1, wherein the logic is described by a register transfer level.   In a logic verification system that includes a control unit, a storage unit, an input unit, and an output unit, and that verifies the logic using a first property that is a verification item for verifying logic,
  By executing the program recorded in the storage unit by the control unit, a table creation unit, a property generation unit and a verification unit are realized,
  Obtaining logic input from the input unit, the first property input from the input unit, and a conversion specification value that is input from the input unit and specifies a proposition generated from the first property Recorded in the storage unit,
  The table creation unit creates a time series table that represents, in a time series, events occurring in the first property from the first property, records the created time series table in the storage unit,
  The property generation unit generates a second property corresponding to the proposition specified by the conversion specification value, records the generated second property in the storage unit,
  The property generation unit generates the second property based on the first property and the time series table when the reverse of the first property or an even number is specified by the conversion specification value, When the reverse side of the first property is designated by the conversion designated value, the second property is generated based on the first property,
  The verification unit verifies the logic using each of the first property and the created second property,
  The output unit outputs a verification result of the verification unit;
  The table creation unit
  Extracting an assumption part and a consequence part by detecting an operator included in the first property;
  For each of the extracted hypothesis part and the consequent part, obtain a change in the signal that is the content of the event, and a time at which the change occurs,
  Create the time series table that represents the change of the signal in a time series based on the time, record the created time series table in the recording unit,
  Create an outcome formula that represents the relationship between the hypothesis part and the outcome part, record the created outcome formula in the time series table,
  Create a reverse time that is a reverse time series from the last time represented in the time series to the start time, and record the created reverse time in the time series table,
  The output unit displays the time series table created by the table creation unit,
  The property generation unit creates a new time series table that represents the change of the signal in the generated second property in a time series based on the time,
  The output unit displays the created new time series table.

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