JP2004326650A - Logic verification program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the logic verification efficiency. <P>SOLUTION: The logic verification program allows a personal computer 100 to function as a verification item input editor (S1) which enables an input of a verification item in a natural language on a tabular display screen and to function as a verification result feedback means (S5) which enables the creation of a test report by feeding-back the verification result to the verification item input editor. The processing of the personal computer 100 reduces the time required for creating the test report as compared with the case of manual operation, and also reduces man-made mistakes due to the unnecessity for troublesome manual operations. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a logic debugging technique, a logic verification program executable by a computer, and a computer-readable recording medium recording the logic verification program.
[0002]
[Prior art]
In a design process of a logic circuit or the like, a logic simulator or a waveform viewer is used as a tool for verifying a logic function, timing, or the like of the designed logic circuit. In a logic simulator, a simulation is performed based on a test vector that describes a test pattern created from a netlist describing circuit information of a semiconductor device in accordance with the specifications of the semiconductor device. In the waveform viewer, the result of the simulation is displayed as a waveform. In the waveform viewer, a horizontal axis is a time axis, and signal names are listed in a vertical axis direction, and a temporal change of each signal is displayed in a waveform. The designer checks whether the simulation result matches the specification based on the waveform display by the waveform viewer.
[0003]
As a method for making the waveform display easier to see, for example, the display color is changed in accordance with a change in the value of the specified trigger signal, and the value of the signal line that changes depending on the change in the value of the trigger signal is displayed in the same color as the trigger signal. It is known to display (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-7-21244 [0005]
[Problems to be solved by the invention]
In logic verification based on waveform display by a waveform viewer as a waveform display tool, identifiers of properties to be satisfied by a circuit described in a verification language (hereinafter referred to as “verification properties”) and verification results are displayed in a table format, and verification properties are displayed. Can be highlighted on the waveform viewer. However, according to such a waveform display tool, verification items cannot be described in a natural language. Therefore, a test specification and a test report must be separately created using an editor or the like. As a result, the creation and modification of test specifications, verification properties, and test reports are all performed manually. In addition, since the editor used for creating the test specifications does not have a version management function of the verification items, it is necessary to manually create the update history. As described above, according to the related art, there are many manual operations, and the number of man-hours is increased and human errors are likely to occur.
[0006]
Furthermore, when analyzing the cause of a bug on a timing chart, it is a precondition that the logical relationship between events indicated by the simulation results be accurately understood. As a means of expressing a logical relationship between events on a timing chart, an “annotated timing diagram” has been conventionally used. The verification engineer himself creates the annotated timing diagram himself when analyzing the cause of the bug. However, if the logical relationship between events is so complex that it cannot be created in the mind, if the cause of the bug needs to be explained to a third party, or if it is to be recorded, the timing chart on the waveform display tool must be printed. The logical relationship between the events is visualized on a timing chart by printing the information on the screen and adding an annotation with a pen. However, the work is complicated, and the number of verification steps must be increased.
[0007]
An object of the present invention is to improve the efficiency of logic verification.
[0008]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0010]
That is, the first means is a logic verification program that causes a computer to input a verification item in a tabular display screen in a natural language into a verification item input editor and to feed back a verification result to the verification item input editor. It functions as a verification result feedback means that can generate a test report.
[0011]
According to the first means, a test report is created by feeding back the verification result to the display screen of the tabular verification item input editor by computer processing. According to the processing by the computer, a test report can be created in a shorter time than in the case of manual operation. In addition, since a complicated manual operation is omitted in creating the test report, human error is reduced. This achieves an improvement in logic verification efficiency. Further, the verification item input editor achieves simplification of input of verification items by enabling input of verification items in a natural language.
[0012]
The second means is a logic verification program, which links the computer to a verification item input editor that enables input of verification items in a natural language on a tabular display screen. A verification property input editor that can be created, an assertion checker generating means for generating an assertion checker based on the verification property, an annotated timing diagram based on waveform data obtained by a logic simulation based on the assertion checker and the verification property, and Annotated timing diagram for generating verification results and verification result generation means, verification result feedback that enables generation of a test report by feeding back the verification results to the verification item input editor To function as a click means.
[0013]
When analyzing the cause of a bug on the timing chart as described above, it is a prerequisite that the logical relationship between the events indicated by the simulation results be accurately understood, and the logical relationship between the events on the timing chart is determined. Conventionally, a "timing diagram with annotations" has been used as a means for expressing the data. However, the manual creation work is complicated, and the number of verification steps must be increased.
[0014]
However, according to the second means, the annotated timing diagram and the verification result generation means generate the annotated timing diagram, and the test result is generated by feeding back the verification result to the verification item input editor. According to the processing by the computer, annotated timing diagrams and test reports can be created in a shorter time than in the case of manual processing. In addition, since a complicated manual operation is unnecessary in creating an annotated timing diagram and a test report, human errors are reduced. This achieves an improvement in logic verification efficiency.
[0015]
The annotated timing diagram and verification result generating means include state transition graph generating means for generating a state transition graph based on the verification property, and waveform data with annotation information based on the state transition graph and the waveform data. And a state transition graph tracing means for obtaining the above verification result.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 10 shows a personal computer system on which the logic verification program according to the present invention is executed.
[0017]
Although not particularly limited, the personal computer system 100 shown in FIG. 10 executes the logic verification program according to the present invention, and various types of functions are performed between the microcomputer 102 that performs various functions for logic verification and the outside. An external interface 101 that allows information to be exchanged, a hard disk device storing various programs and various data executed by the microcomputer 102, and a semiconductor used as a work area in arithmetic processing by the microcomputer 102 The display device 103 includes a storage device 104 including a storage device and the like, and a display device 103 capable of displaying a calculation result of the microcomputer 102 and various necessary information. The program executed by the microcomputer 102 is sent from the program provider to the personal computer system 100 via the network 200, or loaded into the personal computer system 100 via the portable storage medium 300. There is. The logic verification program according to the present invention is stored in the storage device 104 via the network 200 or via the portable storage medium 300. The portable storage medium 300 includes various disks such as a floppy disk, a CD-ROM, a magnetic disk, an optical disk, and a magneto-optical disk. Here, the storage device 104 and the portable storage medium 300 are examples of a computer-readable recording medium on which a logic verification program is recorded.
[0018]
FIG. 1 shows an overall configuration example of a logic verification tool realized by executing a predetermined program related to logic verification in the microcomputer 102.
[0019]
Although the logic verification tool shown in FIG. 1 is not particularly limited, a verification item input editor S1, a verification property input editor S2, an assertion checker generation unit S3, an annotated timing diagram and verification result generation unit S4, a verification result feedback unit S5, And a logic simulator 7.
[0020]
The verification item input editor S1 has a version management function and enables input of the verification items S1A in a table format. The input of the verification item S1A can be performed in a natural language in order to facilitate the input. Although not particularly limited, examples of the verification items input by the verification item input editor S1 include "execute a write transaction to the count register", initialize all registers by a reset signal, and "start counting up by asserting a count start signal". And the like.
[0021]
The verification property input editor S2 enables input of a verification property. The verification property input editor S2 is linked to a verification item (SB1), and the verification property 1 can be created in a verification language using the verification property input editor S2.
[0022]
The assertion checker generation means S3 generates an assertion checker 2 for checking how the specific design behaves or should not behave based on the verification property 1.
[0023]
The logic simulator 7 reads each information of the test bench 5, the verification target circuit 6, and the assertion checker 2 and executes a logic simulation. Then, waveform data 3 is obtained as a result of the logic simulation.
[0024]
The annotated timing diagram and verification result generation means S4 generates the verification result 4 based on the waveform data S4 and the verification property 1, and also generates the annotated timing diagram S4A. The generated verification result The generated verification result 4 is fed back to the verification item input editor S1 by the verification result feedback means S5 to generate a test report.
[0025]
The display screen of the annotated timing diagram includes, in the actual simulation waveform, an annotation symbol S4A1 indicating a logical relationship between events, an error message S4A2, and an expected value S4A3 of the waveform. The verification result S1C and the annotated timing diagram S4A on the display screen of the verification item input editor S1 are linked to each other, and are selected by selecting an item that satisfies the verification property 1 (Pass) or does not satisfy the verification property 1 (Fail). An annotated timing diagram is displayed.
[0026]
Next, the logic verification tool will be described in more detail.
[0027]
FIG. 2 shows an input example of the verification item input editor S1. In the example shown in FIG. 2, the verification item input editor S1 describes the verification item S1A of "signal B rises three cycles after signal A rises" in natural language. Natural language can be easily input via a keyboard in the personal computer system 100.
[0028]
FIG. 3 shows an example of generation of a verification property and generation of an assertion checker.
[0029]
The verification property is created using the verification property input editor S2 linked to the verification item input editor S1. More specifically, the verification property S2 is linked to the verification item verification item S1A of the verification item input editor S1.
[0030]
When a verification property is first created, the verification property input editor S2 is started by selecting a verification item S1A with an input device such as a mouse, and the verification property is input to the verification property input editor S2. Once the verification property has been input, for example, by selecting the verification item S1A with an input device such as a mouse, the corresponding input verification property can be confirmed in the verification property input editor S2. The link mechanism S1B always guarantees the correspondence between the verification item and the verification property. When the verification property 1 is input to the assertion checker generating means S3, an assertion checker is generated in the assertion checker generating means S3.
[0031]
FIG. 4 shows the execution of the logic simulation and the results thereof.
[0032]
The test bench 5, the test target circuit 2, and the assertion checker are read by the logic simulator S1, a logic simulation is executed, and waveform data 4 is generated. The waveform data 4 stores the time of each cycle and the signal value (signal value of A, signal value of B) at that time.
[0033]
FIG. 5 shows a configuration example of the annotated timing diagram and the verification result generation means S4.
[0034]
As shown in FIG. 5, the annotated timing diagram and verification result generation means S4 include a state transition graph generation means S6 for generating a state transition graph 8 based on the verification property 1, and a state transition graph generation means S6. And a state transition graph tracing means S7 for obtaining waveform data 9 with annotation information and a verification result 4 by tracing the state transition graph 8 generated based on the waveform data 3. The waveform viewer S4A reads the annotated waveform data 9 and generates an annotated timing diagram.
[0035]
FIG. 6 shows a flow of the state transition graph generation by the state transition graph generation means S6.
[0036]
“A” on the timing chart indicates the precondition of the verification property, and “b” indicates the result. The verification property 1 indicates a value that a signal should take in each cycle, and a state transition graph is formed by adding the value as a transition condition to each arc of the graph. The “end state” indicates a state reached when the verification property is satisfied as a result of a state transition graph trace described later. The fail state indicates a state reached when the result verification property of a trace of a state transition graph described later is not satisfied.
[0037]
FIG. 7 shows the flow of generation of the annotation-added waveform data and the verification result by the state transition graph tracing means.
[0038]
The trace of the state transition graph starts from the start state of the state transition graph. By reading the signal value of each cycle from the waveform data and comparing it with the transition condition of the state transition graph, it is possible to trace the state transition graph. In FIG. 7, a state with a state name (Rise (A), Rise (B)) indicates an event defined in the verification property. And the time at which the state exited from the state are written together with the state name and the waveform data with annotation information. In this example, at time 50 (ns), the value of the signal value B of the waveform data is “0”, and the signal value expected from the verification property is “1”, so that the state transits to the fail state. After the transition to the fail state, the expected value of the signal, which is the condition for transition to the other state, is obtained. The signal value at the time of failure based on the expected value of this signal is written in the annotated waveform data. After transition to the fail state, the failed property name, time, and verification result are written to a file.
[0039]
FIG. 8 shows an annotated timing diagram generated based on the annotated waveform data. An error message 80 is displayed based on the verification result. Further, based on the expected value of the signal value stored in the waveform data with the annotation information, the expected signal waveform is displayed so as to overlap the actual waveform. Based on the event information stored in the annotation-added waveform data, an arrow symbol 81 indicating the logical relationship between the events is displayed.
[0040]
FIG. 9 shows a state of feedback of the verification result.
[0041]
As shown in FIG. 9, the verification result 4 is fed back to the verification item input editor S1 by the verification result feedback means S5. In the verification item input editor S1, the total number of times that the verification property is satisfied (“0” in the example of FIG. 9) is shown in the “Pass” item, and the number of times the verification property is not satisfied in the “Fail” item. (“1” in the example of FIG. 9) is displayed.
[0042]
According to the above example, the following effects can be obtained.
[0043]
(1) A test report is created by feeding back the verification result to the display screen of the tabular verification item input editor S1. The processing by the personal computer 100 can be performed in a shorter time as compared with the case where a test report is created manually, and the troublesome manual operation can be omitted in creating the test report, thereby reducing human error. As a result, the efficiency of logic verification can be improved.
[0044]
(2) When analyzing the cause of a bug on a timing chart, it is prerequisite to accurately understand the logical relationship between events indicated by the simulation results, and express the logical relationship between events on the timing chart. Conventionally, a "timing diagram with annotations" has been used as a means for performing such a task. However, the manual creation work is complicated, and the number of verification steps must be increased. On the other hand, the annotated timing diagram and verification result generation means S4 generates the annotated timing diagram S4A, and the verification result is fed back to the display screen of the tabular verification item input editor S1 to generate a test report. Is done. The processing by the personal computer 100 can be performed in a shorter time than when annotated timing diagrams and test reports are created manually. In addition, since a complicated manual operation is not required in creating an annotated timing diagram and a test report, human errors are reduced, thereby improving logic verification efficiency.
[0045]
(3) Due to the effects of the above (1) and (2), it is possible to provide the IP purchaser with materials that can quantitatively indicate the quality of the company's IP core.
[0046]
Although the invention made by the present inventors has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention.
[0047]
For example, the logic simulator can be provided as a separate program from the logic verification tool shown in FIG. The annotations in the annotated timing diagram include not only arrow symbols but also various lines such as straight lines, curves, and broken lines, various symbol strings, and character strings.
[0048]
In the above description, the case where the invention made by the inventor is mainly applied to a personal computer system which is a utilization field as a background has been described. However, the present invention is not limited thereto, and may be applied to a workstation or the like. Can be applied.
[0049]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
[0050]
In other words, annotated timing diagrams and test reports can be quickly created by computer processing, and human errors can be reduced by eliminating cumbersome manual operations. Therefore, the logic verification efficiency can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an overall configuration example of a logic verification tool realized by a logic verification program according to the present invention.
FIG. 2 is an explanatory diagram of an input example in a verification item input editor included in the logic verification tool.
FIG. 3 is an explanatory diagram concerning generation of a verification property and an assertion checker by the logic verification tool.
FIG. 4 is an explanatory diagram of execution of a logic simulation in the logic verification tool and a result of the simulation.
FIG. 5 is an explanatory diagram of a configuration example of “annotated timing diagram and verification result generation means” included in the logic verification tool.
FIG. 6 is an explanatory diagram of state transition graph generation by a state transition graph generation unit included in the logic verification tool.
FIG. 7 is an explanatory diagram of generating waveform data with annotation information and a verification result by a state transition graph tracing means included in the logic verification tool.
FIG. 8 is an explanatory diagram of an annotated timing diagram generated based on annotated waveform data.
FIG. 9 is an explanatory diagram of feedback of a verification result in the logic verification tool.
FIG. 10 is a block diagram illustrating a configuration example of a personal computer system on which a logic verification program according to the present invention is executed.
[Explanation of symbols]
Reference Signs List 100 personal computer system 101 external interface 102 microcomputer 103 display device 104 storage device 200 network 300 portable storage medium S1 verification item input editor S2 verification property input editor S3 assertion checker generation means S4 verification result generation means S5 verification result feedback means

Claims (4)

A verification item input editor that enables a computer to input verification items in a natural language on a tabular display screen;
A logic verification program characterized by functioning as verification result feedback means for generating a test report by feeding back a verification result to the verification item input editor. A verification item input editor that enables a computer to input verification items in a natural language on a tabular display screen;
Validation property input editor linked to the above validation item input editor, which can create validation properties in the validation language,
Assertion checker generating means for generating an assertion checker based on the verification property,
Annotated timing diagram and verification result generating means for generating an annotated timing diagram and verification result based on the waveform data obtained by the logic simulation based on the assertion checker and the verification property,
A logic verification program characterized by functioning as verification result feedback means for generating a test report by feeding back the verification result to the verification item input editor. The annotated timing diagram and verification result generation means, state transition graph generation means for generating a state transition graph based on the verification properties,
3. The logic verification program according to claim 2, further comprising: state transition graph tracing means for obtaining waveform data with annotation information and the verification result based on the state transition graph and the waveform data. A computer-readable recording medium recording the logic verification program according to claim 1.

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