JP2013200745A - Information processing device, information processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance detection accuracy of a checker.SOLUTION: An information processing device comprises: a reading unit 1b that reads a first checker 2a which is used in verifying the validity of a logic circuit and checks the occurrence/non-occurrence of a postcondition at the time of the occurrence of a precondition; and a generation unit 1c that generates a second checker 2b which checks the non-occurrence of the postcondition at the time of the non-occurrence of the precondition on the basis of the first checker 2a read by the reading unit 1b.

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

  In LSI (Large Scale Integration) development, a description method called a register transfer level (RTL) is used based on design specifications, and logic of a circuit is expressed by combining logical expressions. In order to verify whether the logic circuit designed in the RTL can realize the function / operation as specified, a logic simulation is performed using a computer.

  At this time, a checker described in an assertion language such as PSL (Property Specification Language) / SVA (System Verilog Assertion) is developed as a mechanism for automatically detecting when a specification violation occurs. This is applied to the logic simulation, and it is confirmed whether or not the logic circuit violates the specification based on the detection result of the checker.

JP 2008-310663 A JP 2010-113395 A

  For example, consider a checker that checks whether a post-condition has occurred when a pre-condition has occurred, passes the check if the post-condition has occurred, and detects an error if the post-condition has not occurred.

  This checker cannot detect the post-condition when the post-condition occurs even though the pre-condition does not occur due to the influence of a logical failure or the like, because the condition for starting the inspection is not satisfied. As described above, when an unintended operation occurs due to a logic failure or an operation occurs under conditions that are not described in the specification, there is a problem that a detection failure occurs.

  In one aspect, the present invention aims to increase the detection accuracy of a checker.

In order to achieve the above object, a disclosed information processing apparatus is provided. This information processing apparatus includes a reading unit and a generation unit.
The reading unit reads a first checker that is used when verifying the validity of the logic circuit and checks whether or not a post-condition is generated when a pre-condition is generated. Based on the first checker read by the reading unit, the generation unit generates a second checker that checks that no post-condition is generated when the precondition does not occur.

  In one aspect, the checker detection accuracy can be increased.

It is a figure which shows the information processing apparatus of 1st Embodiment. It is a figure which shows the hardware constitutions of the information processing apparatus of 2nd Embodiment. It is a block diagram which shows the function of the information processing apparatus of 2nd Embodiment. It is a figure explaining the process of a checker reading part. It is a figure which shows the information stored in the database. It is a flowchart which shows the process of the production | generation part of 2nd Embodiment. It is a figure explaining the check pattern which cannot be covered with the 2nd checker of a 2nd embodiment. It is a figure explaining the process of the checker reading part of 3rd Embodiment. It is a figure which shows the information stored in the database of 3rd Embodiment. It is a flowchart explaining a grouping detection process. It is a flowchart explaining the process of the production | generation part of 3rd Embodiment. It is a figure explaining the process result of 3rd Embodiment. It is a figure explaining the 1st checker of 4th Embodiment.

Hereinafter, an information processing apparatus according to an embodiment will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a diagram illustrating the information processing apparatus according to the first embodiment.

  The information processing apparatus (computer) 1 according to the first embodiment includes a storage unit 1a, a reading unit 1b, a generation unit 1c, and a storage unit 1d. The storage units 1a and 1d can be realized by a data storage area provided in a RAM (Random Access Memory) or a hard disk drive (HDD) included in the information processing apparatus 1. Further, the reading unit 1b and the generation unit 1c can be realized by functions provided in a CPU (Central Processing Unit) included in the information processing apparatus 1.

  The storage unit 1a stores a first checker 2a that is used when verifying the validity of the logic circuit to be designed, and checks whether or not a post-condition has occurred when a pre-condition occurs. The storage unit 1a may be outside the information processing apparatus 1. The first checker 2a is described in an assertion language. The first checker 2a includes an assertion name (assertion_name), a synchronization condition (event), an abort condition (abort), a precondition (precond), a minimum allowable interval (n) between a precondition and a postcondition, and a precondition and a postcondition. The maximum allowable interval (m) and post-condition (postcond) are described. Specifically, the first checker 2a has an assertion name “chk_xx”, a synchronization condition “possed clock”, an abort condition “C1 == 0”, a precondition “A1 == 1”, The minimum allowable interval for the postcondition is “2”, the maximum allowable interval for the precondition and the postcondition is “4”, and the postcondition is “B1 == 1”. The first checker 2a includes an assertion whose assertion name is “chk_xx” (hereinafter referred to as “assertion“ chk_xx ””), which checks that “the post-condition B1 becomes 1 after 2-4 cycles when the precondition A1 becomes 1. ")".

The reading unit 1b reads the first checker 2a from the storage unit 1a.
Based on the first checker 2a read by the reading unit 1b, the generation unit 1c generates a second checker 2b that inspects that no post-condition is generated when the precondition does not occur.

  In the second checker 2b, in addition to the assertion “chk_xx” described in the first checker 2a, the assertion “chk_xx_precond_chk” defined by the generation unit 1c is described. This assertion “chk_xx_precond_chk” functions as a precondition checker 2b1 that checks that the precondition A1 was 1 to 2 to 4 cycles before the postcondition B1 becomes 1. Regarding the description on the fourth line of the precondition checker 2b1, the numerical value of the minimum allowable interval n is incremented by 1 and the description of “$ past (<precond_expr>, delay)” is logically processed until the maximum allowable interval m is reached. Generated by connecting with sum (or).

  In addition, immediately before the generated assertion “chk_xx_precond_chk”, a comment “// CAGS Info: Generated_frox___________________________________________________________________________ Is inserted.

The generation unit 1c stores the generated second checker 2b in the storage unit 1d. The storage unit 1d may be outside the information processing apparatus 1.
For example, the information processing apparatus 1 applies the second checker 2b to the logic simulation, and checks whether or not the logic circuit violates the specification based on the detection result of the checker. By using the second checker 2b, the occurrence of the post-condition B1, which could not be detected when using only the first checker 2a, is triggered, and the occurrence of the post-condition B1 is the occurrence of the pre-condition A1. It is possible to inspect retrospectively that it is caused by Thereby, even when the function of the logic circuit is implemented so that the post-condition B1 is rewritten unintentionally due to a designer's mistake or the like, it can be detected as an error. Therefore, the detection accuracy of the checker can be increased.

Hereinafter, in the second embodiment, the disclosed information processing apparatus will be described more specifically.
<Second Embodiment>
FIG. 2 is a diagram illustrating a hardware configuration of the information processing apparatus according to the second embodiment.

The information processing apparatus 10 is entirely controlled by the CPU 101. The CPU 101 is connected to the RAM 102 and a plurality of peripheral devices via the bus 108.
The RAM 102 is used as a main storage device of the information processing apparatus 10. The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data used for processing by the CPU 101.

  A hard disk drive 103, graphic processing device 104, input interface 105, drive device 106, and communication interface 107 are connected to the bus 108.

  The hard disk drive 103 magnetically writes data to and reads data from a built-in disk. The hard disk drive 103 is used as a secondary storage device of the information processing apparatus 10. The hard disk drive 103 stores an OS program, application programs, and various data. As the secondary storage device, a semiconductor storage device such as a flash memory can be used.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. Examples of the monitor 104a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits signals sent from the keyboard 105a and the mouse 105b to the CPU 101. Note that the mouse 105b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The drive device 106 reads data recorded on a portable recording medium such as an optical disc on which data is recorded so as to be readable by reflection of light or a USB (Universal Serial Bus) memory. For example, when the drive device 106 is an optical drive device, data recorded on the optical disc 200 is read using a laser beam or the like. Examples of the optical disc 200 include Blu-ray (registered trademark), DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), and the like. .

  The communication interface 107 is connected to the network 50. The communication interface 107 transmits / receives data to / from other computers or communication devices via the network 50.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
The following functions are provided in the information processing apparatus 10 having a hardware configuration as shown in FIG.

FIG. 3 is a block diagram illustrating functions of the information processing apparatus according to the second embodiment.
The information processing apparatus 10 includes a first checker storage unit 11, a checker reading unit 12, a generation unit 13, a second checker storage unit 14, an interface unit 15, and a DB input / output unit 16. Yes.

  The first checker storage unit 11 stores at least one first checker used to verify the validity of the logic circuit to be designed. In the following description, it is assumed that the first checker having the same content as the first checker 2a of the first embodiment is stored in the first checker storage unit 11.

The checker reading unit 12 acquires necessary information from the first checker specified by the interface unit 15 and sets it in the checker data model 121.
FIG. 4 is a diagram for explaining the processing of the checker reading unit.

The first checker 111 shown in FIG. 4 has the same contents as the first checker 2a of the first embodiment.
The checker data model 121 is a structure having each piece of information of the first checker 111 as a member.

  The checker reading unit 12 stores each information in an appropriate member of the checker data model 121. Each piece of information stored in a member of the checker data model 121 when the first checker 111 is input is shown at the tip of the arrow indicated by a dotted line on the right side of the checker data model 121.

  The generation unit 13 generates the precondition checker 131a based on the information set in the checker data model 121. When generating the precondition checker 131a, the generation unit 13 first sets a fixed sentence. The fixed phrase is a place other than the place shown in italics of the precondition checker 131a shown in FIG. Then, the information stored in the checker data model 121 is inserted into the standard sentence. The inserted information is a portion expressed in italics of the precondition checker 131a shown in FIG. Here, with respect to the description on the fourth line of the precondition checker 131a, the numerical value of the minimum allowable interval n is incremented by 1, and “$ past (<precond_expr>, delay)” is reached until the maximum allowable interval m is reached. Generated by connecting descriptions with logical OR. In addition, the generation unit 13 displays information indicating that the precondition checker 131a is generated by the information processing apparatus 10 and which assertion in the input checker is generated from the precondition checker 131a. Describe in comment format at the beginning of the line.

  The second checker 131 generated in this way describes the assertion “chk_xx_precond_chk” defined by the generation unit 13 in addition to the assertion “chk_xx” described in the first checker 111. This assertion “chk_xx_precond_chk” is an assertion for inspecting that the precondition A1 is 1 to 2-4 cycles before the postcondition B1 becomes 1.

  Further, immediately before the generated assertion, a comment “// CAGS Info: Generated from chk_xx” indicating that the assertion “chk_xx_precond_chk” is an assertion generated by the information processing apparatus 10 based on the assertion “chk_xx”. Has been inserted.

The generation unit 13 stores the second checker 131 in which the generated precondition checker 131 a and the first checker 111 are collected in the second checker storage unit 14.
The interface unit 15 controls the information processing apparatus 10 in accordance with user input contents. For example, the interface unit 15 specifies the first checker 111 stored in the first checker storage unit 11 in accordance with a user input. Then, as described above, the checker reading unit 12 acquires necessary information from the first checker 111 specified by the interface unit 15 and sets it in the checker data model 121.

  Further, the interface unit 15 can display the information stored in the database by the DB input / output unit 16 on the monitor 104a. When the user rewrites the information displayed on the monitor 104a, the interface unit 15 reflects the rewritten information on the checker data model 121. The interface unit 15 instructs the DB input / output unit 16 to update the database.

  The DB input / output unit 16 creates a database of information set in the checker data model 121. This information is displayed in a format that can be easily changed by the user by the interface unit 15 and can be edited. By using this function, the user can operate the information set in the checker data model 121 and generate a desired checker. Conversely, the DB input / output unit 16 can also extract information stored in the database 20.

FIG. 5 is a diagram showing information stored in the database.
A table 20 a illustrated in FIG. 5 indicates information stored in the database 20.
In the table 20a, columns for storing information described in the first checker 111 are set.

Next, the process of the production | generation part 13 shown in FIG. 4 is demonstrated using a flowchart.
FIG. 6 is a flowchart illustrating processing of the generation unit according to the second embodiment.
[Step S1] The generation unit 13 creates a fixed phrase. Thereafter, the process proceeds to step S2.

  [Step S <b> 2] The generation unit 13 refers to the checker data model 121 and inserts an assertion name, a synchronization condition, an abort condition, and a postcondition into the fixed sentence created in Step S <b> 1. Thereafter, the process proceeds to step S3.

[Step S3] The generation unit 13 refers to the checker data model 121 and sets the minimum allowable interval n to the prepared parameter k. Thereafter, the process proceeds to step S4.
[Step S4] The generation unit 13 determines whether or not the value of the parameter k matches the maximum allowable interval m. When the value of the parameter k matches the maximum allowable interval m (Yes in step S4), the process proceeds to step S6. If the value of the parameter k does not match the maximum allowable interval m (No in step S4), the process proceeds to step S5.

[Step S <b> 5] The generation unit 13 connects the descriptions of “$ past (<precond_expr>, delay)” with a logical sum. Then, the process proceeds to step S5a.
[Step S5a] The generation unit 13 increments the value of the parameter k. Thereafter, the process proceeds to step S4.

[Step S6] The generation unit 13 inserts the combination of the logical sums generated in step S5 after the fixed phrase. Then, the process proceeds to step S7.
[Step S7] The generation unit 13 inserts “;)” indicating the end of generation of the precondition checker 131a. Thereafter, the process proceeds to operation S8.

[Step S8] The generation unit 13 adds the first checker 111 to the precondition checker 131a to generate the second checker 131. Thereafter, the process proceeds to operation S9.
[Step S <b> 9] The generation unit 13 stores the second checker 131 generated in step S <b> 8 in the second checker storage unit 14. Then, the process of FIG. 6 is complete | finished.

  As described above, according to the information processing apparatus 10, the second checker 131 including the precondition checker 131a that can check that the precondition has occurred in the past due to the occurrence of the postcondition is generated. By verifying the validity of the logic circuit using the second checker 131, it is possible to detect a case where a post-condition has occurred even though a pre-condition has not occurred, as an error. By leaving this error in the log file, the user can determine the presence or absence of an error (the presence or absence of a failure) simply by checking the log file.

  Therefore, it is possible to cover checks that are not described in the specifications (detection of occurrence of post-conditions that do not depend on preconditions), occurrence of unintended operations due to logic faults, and conditions that are not described in the specifications The checker can detect the occurrence of the operation in (the omission of specification description). Thereby, the comprehensiveness of the checker is improved as compared with the conventional case, and the verification quality is improved.

<Third Embodiment>
Next, an information processing apparatus according to a third embodiment will be described.
Hereinafter, the information processing apparatus according to the third embodiment will be described with a focus on differences from the above-described second embodiment, and description of similar matters will be omitted.

  In the second embodiment, the case where there is only one type of assertion “chk_xx” in the input first checker 111 has been described. However, when a plurality of assertions are described in the first checker, the information processing apparatus 10 according to the second embodiment generates a precondition checker for each. If assertions with the same post-condition and different pre-conditions are described in the first checker, there is a check pattern that cannot be covered by the second checker generated by the information processing apparatus 10 according to the second embodiment. To do.

FIG. 7 is a diagram for explaining check patterns that cannot be covered by the second checker according to the second embodiment.
In the first checker 112 that is a source for generating the precondition checker 132a shown in FIG. 7, a specification that “the condition that the postcondition B1 is 1 is that the precondition A1 or the precondition A2 is 1” is described. ing. The first checker 112 to be input includes an assertion “chk_xx” for checking that the post-condition B1 becomes 1 after 2 to 4 cycles when the pre-condition A1 becomes 1, and the pre-condition A2 becomes 1. The assertion “chk_yy” for checking that the postcondition B1 becomes 1 after 2 to 4 cycles is described.

  In both the assertion “chk_xx” and the assertion “chk_yy”, “B1 == 1” is defined as the postcondition. When the first checker 112 is input as it is to the information processing apparatus 10 of the second embodiment, a precondition checker 132a in which the assertion “chk_xx_precond_chk” and the assertion “chk_yy_precond_chk” are described is generated.

  As described above, the first checker 112 describes a specification that “the condition that the postcondition B1 is 1 is that the precondition A1 or the precondition A2 is 1”. For this reason, if any of the preconditions occurs when the postcondition (B1 == 1) occurs, it may be determined that the operation is correct. However, the generated precondition checker 132a notifies an error when a postcondition occurs, as long as all the plurality of preconditions are not generated. That is, the checker detects an error as a violating operation even though the verification target performs a correct operation.

The information processing apparatus according to the third embodiment includes a function (grouping function) for solving a check pattern that cannot be covered by the second checker generation method according to the second embodiment.
FIG. 8 is a diagram illustrating processing of the checker reading unit according to the third embodiment.

  A first checker 112 similar to that shown in FIG. 7 is stored in the first checker storage unit 11 shown in FIG. The first checker 112 describes an assertion “chk_xx” and an assertion “chk_yy”.

  The checker reading unit 12 according to the third embodiment compares the postconditions of the input assertion “chk_xx” and the assertion “chk_yy” with character strings, and the postconditions are equivalent to the previously input assertion. In this case, the assertion “chk_xx” and the assertion “chk_yy” are determined to be grouping target assertions.

Based on the determination result, the checker reading unit 12 sets the information described in the first checker 112 in the checker data model 122 for grouping.
As shown in FIG. 8, the information stored in the members of the checker data model 122 when the first checker 112 is input is shown at the tip of the arrow indicated by a dotted line on the right side of the checker data model 122. .

  Further, the checker reading unit 12 determines that the assertion “chk_xx” and the assertion “chk_yy” are in the same group because the postcondition “B1 == 1” is defined. Then, the checker reading unit 12 converts post-condition information to generate a group name. Specifically, when the postcondition is “signal == n”, the group attribute is “Grp_“ signal ”eq“ n ””, and when “signal! = N”, “Grp_“ signal ”ne“ n ” " When this is applied to the example shown in FIG. 8, the group name is “Grp_B1eq1”.

The generation unit 13 generates a second checker 133 including a checker 112 a and a precondition checker 133 a based on the checker data model 122.
The checker 112a includes a comment “CAGS Info: Member of“ Grp_B1eq1 ”indicating that the assertion“ chk_xx ”and the assertion“ chk_yy ”are determined to be grouping-targeted assertions in a line before each assertion of the first checker 112. “Group.” Is inserted. This comment has a comment format of “CAGS Info: Member of XX Group.”, And the generation unit 13 inserts a group name in the “XX” part.

  The precondition checker 133a can check that either the precondition A1 or the precondition A2 has occurred before when the postcondition B1 becomes 1. A method for generating the precondition checker 133a will be described later.

The DB input / output unit 16 stores information set in the checker data model 122 in the database 20.
FIG. 9 is a diagram illustrating information stored in the database according to the third embodiment.

A table 20b shown in FIG. 9 shows information stored in the database 20.
In addition to the table 20a, the table 20b further includes columns for group attribute and group assertion.

In the group attribute column, group names of assertions grouped by the checker reading unit 12 are set.
In the group assertion column, the postcondition of the input assertion is compared with a character string, and if there is an equivalent postcondition in the previously input assertion, the assertion name is set.

  When the interface unit 15 displays the information set in the table 20b on the monitor 104a, it can be confirmed that both the assertion “chk_xx” and the assertion “chk_yy” belong to the group having the group name “Grp_B1eq1”. By using this method, the grouping function can be validated without the user manually adding grouping information to the first checker 112 (without bothering the user). For this reason, it is possible to prevent an assertion that should belong to the same group from being missed.

Next, processing (grouping detection processing) in which the checker reading unit 12 illustrated in FIG. 8 detects assertions to be grouped will be described.
FIG. 10 is a flowchart for explaining the grouping detection process.

[Step S11] The checker reading unit 12 acquires the first checker 112. Thereafter, the process proceeds to operation S12.
[Step S12] The checker reading unit 12 calculates the number n of assertions included in the acquired first checker 112. Thereafter, the process proceeds to operation S13.

[Step S13] The checker reading unit 12 sets the parameter k = 0. Thereafter, the process proceeds to operation S14.
[Step S14] The checker reading unit 12 determines whether or not the parameter k matches the number of assertions n. When the parameter k matches the number of assertions n (Yes in step S14), the process in FIG. When the parameter k does not match the assertion number n (No in step S14), the process proceeds to step S15.

  [Step S15] The checker reading unit 12 determines whether there is an assertion in the first checker 112 acquired in step S11 that matches the post-condition. If there is an assertion that matches the post-condition (Yes in step S15), the process proceeds to step S16. If there is no assertion that matches the post-condition (No in step S15), the process proceeds to step S18.

  [Step S <b> 16] The checker reading unit 12 determines that the assertion whose post-conditions match is the grouping target assertion. Thereafter, the process proceeds to operation S17.

[Step S <b> 17] The checker reading unit 12 generates a group attribute name of the grouping target assertion based on the precondition name. Thereafter, the process proceeds to operation S18.
[Step S18] The checker reading unit 12 increments the parameter k. Thereafter, the process proceeds to operation S14.

Next, the process of the production | generation part 13 shown in FIG. 8 is demonstrated using a flowchart.
FIG. 11 is a flowchart illustrating the processing of the generation unit according to the third embodiment.
[Step S21] The generation unit 13 creates a fixed sentence. Thereafter, the process proceeds to operation S22.

  [Step S22] The generation unit 13 refers to the checker data model 122 and inserts an assertion name, a synchronization condition, an abort condition, and a postcondition into the fixed sentence created in step S21. Thereafter, the process proceeds to operation S23.

[Step S <b> 23] The generation unit 13 extracts one element of “checker_group.checkers []”. Thereafter, the process proceeds to operation S24.
[Step S24] The generation unit 13 refers to the checker data model 122 and sets the minimum allowable interval n to the prepared parameter k. Thereafter, the process proceeds to operation S25.

  [Step S25] The generation unit 13 determines whether or not the value of the parameter k matches the maximum allowable interval m. When the value of the parameter k matches the maximum allowable interval m (Yes in step S25), the process proceeds to step S27. When the value of the parameter k does not match the maximum allowable interval m (No in step S25), the process proceeds to step S26.

[Step S <b> 26] The generation unit 13 connects the descriptions of “$ past (<precond_expr>, delay)” with a logical sum. Thereafter, the process proceeds to operation S26a.
[Step S26a] The generation unit 13 increments the value of the parameter k. Thereafter, the process proceeds to operation S25.

  [Step S27] The generation unit 13 determines whether all elements set in “checker_group.checkers []” have been extracted. When all the elements have been extracted (Yes in step S27), the process proceeds to step S28. When all the elements have not been extracted (No in step S27), the process proceeds to step S23, where elements that have not been subjected to the processes in steps S24 to S26 are extracted, and the processes after step S24 are executed.

[Step S28] The generation unit 13 inserts the combination of the logical sums generated in step S26 after the fixed phrase. Thereafter, the process proceeds to operation S29.
[Step S29] The generation unit 13 inserts “;)” indicating the end of the generation of the precondition checker 133a. Thereafter, the process proceeds to operation S30.

  [Step S <b> 30] The generation unit 13 adds the checker 112 a with the comment added to the first checker 112 to the precondition checker 133 a, and generates the second checker 133. Thereafter, the process proceeds to operation S31.

[Step S31] The generation unit 13 stores the second checker 133 generated in step S30 in the second checker storage unit 14. Then, the process of FIG. 11 is complete | finished.
FIG. 12 is a diagram for explaining the processing result of the third embodiment.

  According to the second checker 133 generated by the information processing apparatus 10 according to the third embodiment, if any of the preconditions A1 and A2 occurs when the postcondition (B1 == 1) occurs, It can be determined that the operation is correct. This can also prevent oversight of assertions that should belong to the same group.

<Fourth embodiment>
Next, an information processing apparatus according to the fourth embodiment will be described.
Hereinafter, the information processing apparatus according to the fourth embodiment will be described with a focus on differences from the second embodiment and the third embodiment described above, and descriptions of similar matters will be omitted. .

  The information processing apparatus 10 according to the fourth embodiment is different in that information to be set in the checker data model 121 is acquired by input from the interface unit 15 and a second checker is generated based on the set information. .

  In the present embodiment, an example of generating the assertion “chk_xx” of the first checker input as the input in the second embodiment and the third embodiment and the assertion “chk_xx_precond_chk” for checking the precondition thereof are generated. I will give you.

  The user inputs information for generating the assertion “chk_xx” according to the input format of the interface unit 15. Thereafter, as described in the second embodiment, this input information is stored in the database 20 and reflected in the checker data model 121.

  The generation unit 13 generates an assertion “chk_xx_precond_chk” for the precondition checker using the same algorithm as in the second embodiment. Further, as shown in FIG. 4, the generation unit 13 also generates the first checker assertion “chk_xx” by embedding the information of the checker data model 121 in the italicized part, and generates a second checker in which these are summarized. The data is stored in the second checker storage unit 14.

By the way, the user can also manually input information for grouping assertions having the same post-condition into the first checker.
In order to group assertions with the same post-condition, the user inserts a dedicated comment on the preceding line of the assertion using the keyboard 105a and the mouse 105b. By inputting the first checker in which the comment of this format is inserted into the information processing apparatus 10, it is possible to check that the assertion “chk_xx” and the assertion “chk_yy” are both the same group having the postcondition “B1 == 1”. The reading unit 12 recognizes. In the checker reading unit 12, those belonging to the same group are collectively output as one assertion when the precondition checker is generated.

FIG. 13 is a diagram illustrating the first checker according to the fourth embodiment.
The format of the grouping comment of the first checker 113 of the present embodiment is determined as “CAGS Info: Member of XX Group.”, And the xx part can be arbitrarily designated by the user. The label of the assertion generated at this time is “xxx_precond_chk”. In the example illustrated in FIG. 13, it is generated as “Grp_B1_precond_chk”. As a result, a second checker having a function equivalent to that of the third embodiment can be generated.

  The information processing apparatus, information processing method, and program of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit has the same function. Any configuration can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
Note that the processing performed by the information processing device 10 may be distributed by a plurality of devices. For example, one apparatus may generate the checker data model 121, and another apparatus may generate the second checker 131 using the checker data model 121.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions of the information processing apparatuses 1 and 10 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic storage device include a hard disk drive, a flexible disk (FD), and a magnetic tape. Examples of the optical disk include a DVD, a DVD-RAM, and a CD-ROM / RW. Examples of the magneto-optical recording medium include an MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  Further, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

1, 10 Information processing device 1a, 1d Storage unit 1b Reading unit 1c, 13 Generation unit 2a, 111, 112, 113 First checker 2b, 131, 133 Second checker 2b1, 131a, 132a, 133a Precondition checker 11 First checker storage unit 12 Checker reading unit 121, 122 Checker data model 14 Second checker storage unit 15 Interface unit 16 DB input / output unit 20 Database 20a, 20b Table

Claims (6)

A reading unit that reads a first checker that inspects whether or not a post-condition is generated when a pre-condition occurs when verifying the validity of the logic circuit;
Based on the first checker read by the reading unit, a generation unit that generates a second checker that checks that no post condition occurs when the pre-condition does not occur;
An information processing apparatus comprising:   The generating unit generates the second checker by adding a logical sum of preconditions from a minimum allowable interval to a maximum allowable interval between a precondition and a postcondition described in the first checker. The information processing apparatus according to claim 1.   When there is a checker having a plurality of preconditions for the same postcondition in the first checker read by the reading unit, the generation unit is when any one of the plurality of preconditions is satisfied 2. The information processing apparatus according to claim 1, wherein information for determining that the logic of the logic circuit is valid is added to the second checker.   The generation unit determines whether there is an assertion having the same postcondition among the assertions included in the first checker, and associates the assertions having the same postcondition to the assertions of the same group based on the determination result. The information processing apparatus according to claim 1. Computer
When verifying the correctness of the logic circuit, the first checker for checking whether or not the post-condition is generated when the pre-condition is generated is read.
Based on the read first checker, a second checker is generated to check that no post condition occurs when the pre-condition does not occur.
An information processing method characterized by the above. On the computer,
When verifying the correctness of the logic circuit, the first checker for checking whether or not the post-condition is generated when the pre-condition is generated is read.
Based on the read first checker, a second checker is generated to check that no post condition occurs when the pre-condition does not occur.
A program characterized by causing processing to be executed.

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