JP2010140255A - Reconfigurable logic circuit, verification method and verification program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase in scale of a verification circuit mounted on a reconfigurable logic circuit when the number of assertions in assertion-based verification increases. <P>SOLUTION: The reconfigurable logic circuit includes a designed circuit and a verification circuit for verifying the designed circuit. The verification circuit is shared in verifications based on a plurality of assertions included in assertion-based verification. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a reconfigurable logic circuit, a verification method, and a verification program, and more particularly to a reconfigurable logic circuit, a verification method, and a verification program related to assertion-based verification.

  In the design of system LSIs that are becoming larger and more complicated, the time required for simulation and confirmation of simulation results is increasing. Therefore, it is a problem to speed up simulation and automate simulation result confirmation. In order to solve these problems, assertion-based verification based on the expansion of the function of the software simulator is widely used.

  An assertion expresses a condition that should originally be satisfied in a circuit to be designed. How a circuit should or should not be defined is defined by an assertion description language (eg, PSL, System Verilog Assertion). Assertion-based verification refers to identifying the occurrence time and location of a malfunction in a circuit to be designed by constantly monitoring the operation of the circuit to be designed during simulation and checking the success or failure of the assertion. .

  However, when the assertion-based verification is applied, a load for monitoring the operation of the circuit by the software simulator is large. Therefore, there is a problem that the simulation time is longer than that when the assertion-based verification is not applied. Therefore, in order to speed up the simulation, it is desirable to realize assertion-based verification based on cooperative simulation in which a software simulator and a hardware emulator are connected.

  In Patent Document 1, hardware and software co-simulation is described. Referring to FIG. 2 of Patent Document 1, the simulation apparatus includes a programmable circuit 1a on which a design target circuit 3a that performs a cycle operation is mounted, and a computer 2 that executes a program created as an operation description without time constraints. .

  The programmable circuit 1a verifies whether the operations of the data transfer circuits 41a and 41b that perform data transfer between the computer 2 and the design target circuit 3a in units of transactions and the design target circuit 3a satisfy the specifications, and the design target circuit 3a The verification circuits 31_1 to 31_n and 31_1 to 31_k that notify the error detection when the operation does not satisfy the specifications, and the operation of the design target circuit 3a when the error detection is notified are temporarily stopped, and the verification circuit And verification result transfer circuits 42 a and 42 b that transfer the results of verification by 31 — 1 to 31 — n and 31 — 1 to 31 — k to the computer 2.

Japanese Patent Laying-Open No. 2007-094591 (FIG. 2)

  The following analysis was made by the present inventors. In the simulation apparatus described in Patent Document 1, the numbers of the first to nth verification circuits 31_1 to 31_n and the first to kth verification circuits 32_1 to 32_k are the number of assertions (for example, inserted in the HDL description). It corresponds to the number. That is, the assertion for the design target circuit 3a is implemented as a separate verification circuit.

  Therefore, in the simulation apparatus described in Patent Document 1, when the number of assertions increases as the scale of the design target circuit 3a increases, it is mounted on a programmable circuit (also referred to as a reconfigurable logic circuit). There is a problem that the scale of the verification circuit to be increased.

  Therefore, it becomes a problem to suppress an increase in the scale of the verification circuit mounted on the reconfigurable logic circuit when the number of assertions in the assertion-based verification increases.

  A reconfigurable logic circuit according to a first aspect of the present invention includes a design target circuit and a verification circuit that verifies the design target circuit, and the verification circuit performs verification based on a plurality of assertions included in assertion-based verification. Shared by

  A verification method according to a second aspect of the present invention is a verification method using a reconfigurable logic circuit including a design target circuit and a verification circuit for verifying the design target circuit, and the verification circuit performs assertion-based verification. A step of performing verification based on the first assertion included, and a step of performing verification based on the second assertion included in the assertion base verification by the verification circuit.

  A verification program according to a third aspect of the present invention includes a design target circuit and a verification circuit for verifying the design target circuit, and the verification circuit is shared for verification based on a plurality of assertions included in assertion-based verification. A computer connected to the reconfigurable logic circuit configured as described above is caused to transmit a control code for selecting which of the plurality of assertions is to be used to verify the design target circuit.

  With the reconfigurable logic circuit, the verification method, and the verification program according to the present invention, when the number of assertions in the assertion-based verification increases, it is possible to suppress an increase in the size of the verification circuit mounted on the reconfigurable logic circuit. .

(First embodiment)
A verification circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a verification circuit according to the present embodiment. Referring to FIG. 1, a co-simulation is performed between the reconfigurable logic circuit 20 and the computer 10. The reconfigurable logic circuit 20 includes a verification circuit 27 and a design target circuit 21.

  The verification circuit 27 verifies the design target circuit 21. The verification circuit 27 is shared for verification based on a plurality of assertions included in the assertion-based verification.

  The verification circuit 27 is preferably shared for verification based on similarities among the plurality of assertions included in the assertion-based verification.

  The reconfigurable logic circuit 20 may further include a setting register 28. The setting register 28 records a control code for selecting which of the plurality of assertions included in the assertion-based verification should verify the design target circuit 21. The verification circuit 27 verifies the design target circuit 21 based on the assertion selected by the control code recorded in the setting register 28.

  The computer 10 is also connected to a reconfigurable logic circuit 20. The verification program 11 may cause the computer 10 to transmit a control code for selecting which of the plurality of assertions is to be used to verify the design target circuit 21.

  By sharing the verification circuit 27 among a plurality of assertions included in the assertion-based verification, an increase in the size of the verification circuit 27 mounted on the reconfigurable logic circuit 20 can be suppressed when the number of assertions increases. Can do.

  Even if the assertion description includes an error, the error can be corrected without reconfiguring the reconfigurable logic circuit 20. This is because the function of the verification circuit 27 can be corrected by rewriting the setting register 28 for the verification circuit 27 by the verification program 11.

  Embodiments of a verification circuit according to the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a configuration of a simulation apparatus including the verification circuit of this embodiment. The simulation apparatus includes a computer 60 and a reconfigurable logic circuit 70, and both are connected via an IO port 50 of the reconfigurable logic circuit 70.

  The reconfigurable logic circuit 70 includes a design target circuit 71, a verification circuit 77, a clock control circuit 73, a break control circuit 72, and an IO port 50. The circuit to be designed is designed by HDL, for example. The verification circuit 77 is generated according to the assertion defined for the design target circuit 71. The clock control circuit 73 generates a clock for operating the verification circuit 77 and the design target circuit 71. The break signal 76 is a signal for notifying the break control circuit 72 and the clock control circuit 73 that an assertion or error has occurred. The break control circuit 72 generates a break request signal 75. The break request signal 75 is a signal requesting that the check result be transferred to the verification program 61 on the computer 60. The IO port 50 controls communication between the verification program 61 on the computer 60 and the reconfigurable logic circuit 70.

  The verification circuit 77 includes first to nth assertion circuits 74_1 to 74_n, first to nth setting registers 78_1 to 78_n, first to nth verification result registers 79_1 to 79_n, and a verification program I / F51. The first to nth assertion circuits 74_1 to 74_n observe the design target circuit 71 and check whether the operation is an expected operation. The first to nth setting registers 78_1 to 78_n control the functions of the first to nth assertion circuits 74_1 to 74_n. The first to nth verification result registers 79_1 to 79_n store verification results. The verification program I / F 51 is an I / F for accessing the verification circuit 77 from the verification program 61 on the computer 60.

  The verification program 61 provided in the computer 60 includes first assertion control codes 62_1_1 to 62_1_m, which are setting codes for changing the functions of the first to nth assertion circuits 74_1 to 74_n, and nth assertion control codes 62_n_1 to 62_n_k. Is provided.

  The first assertion control codes 62_1_1 to 62_1_m,..., Nth assertion control codes 62_n_1 to 62_n_k are set in the first to nth setting registers 78_1 to 78_n via the IO port 50 and the verification program I / F51. The first to nth assertion circuits 74_1 to 74_n operate according to the assertion control code set in the first to nth setting registers 78_1 to 78_n.

  The IO port 50 is connected to the verification program I / F 51 of the verification circuit 77, the break control circuit 72, and the clock control circuit 73. The break control circuit 72 and the clock control circuit 73 receive the break signal 76 that is the output of the verification circuit 77.

  The verification program 61 receives the break request signal 75. The first to nth assertion circuits 74_1 to 74_n of the verification circuit 77 receive the internal signal of the design target circuit 71.

  The operation of the simulation apparatus shown in FIG. 2 will be described with reference to FIG. The verification program 61 provided in the computer 60 receives one of the first assertion control codes 62_1_1 to 62_1_m, which is an assertion code for the first assertion circuit, via the IO port 50 and the verification program I / F 51. 1 is set in the 1 setting register 78_1. Similarly, the verification program 61 sets any one of the nth assertion control codes 62_n_1 to 62_n_k, which is an assertion code for the nth assertion circuit, in the nth setting register 78_n (step S10).

  Next, the clock control circuit 73 supplies a clock to the design target circuit 71 and the verification circuit 77, and starts a simulation (step S11).

  It is determined whether or not the simulation is finished (step S14). When the simulation is finished (Yes in step S14), the verification is finished.

  On the other hand, if the simulation has not ended (No in step S14), an assertion check (step S15) is performed. Here, as a check for the success or failure of the assertion, the first to nth assertion circuits 74_1 to 74_n receive the internal signal of the design target circuit 71 and the assertion control set in the first to nth setting registers 78_1 to 78_n is performed. It is checked whether an assertion corresponding to the code is established (step S15). If the assertion is not established (No in step S15), the process returns to step S14 and the simulation is continued.

  When the assertion is established (Yes in step S15), the first to nth assertion circuits 74_1 to 74_n notify the break control circuit 72 of the generation of the assertion verification by the break signal 76. The break control circuit 72 notifies the verification program 61 of the break request signal 75 (step S16). When receiving the break signal 76, the clock control circuit 73 stops the clock supplied to the design target circuit 71 (step S17).

  When the verification program 61 receives the break request signal 75 from the break control circuit 72, the verification program 61 reads (reads) a factor register (not shown) of the break control circuit 72 via the IO port 50, and It is determined which of the first to nth assertion circuits 74_1 to 74_n is the notification from the assertion circuit, and the break factor is cleared (erased) after the determination (step S18).

  The verification program 61 reads the verification result stored in any of the first to nth verification result registers 79_1 to 79_n according to the determination result via the IO port 50 (step S19).

  Next, returning to step S11, the clock supply is resumed, and the above steps S11 to S19 are repeated until the simulation end condition is satisfied (Yes in step S14).

  After the simulation, when there is an assertion to be verified next, that is, when there is an assertion control code that has not been checked, one of the first assertion control codes 62_1_1 to 62_1_m,. Any one of the assertion control codes 62_n_1 to 62_n_k is set in the first to nth setting registers 78_1 to 78_n via the IO port 50 and the verification program I / F 51, respectively (step S10).

  The simulation (steps S11 to S19) is performed again. The simulation process is repeated until all the assertions to be verified are completed.

  As a second embodiment of the verification circuit according to the present invention, sharing of an assertion circuit will be described. FIG. 4 shows property declarations in the assertion definition, and in particular, shows a property named Lib1 defined by the designer. The property declaration in FIG. 4 indicates that “the specification is satisfied if ARG3 and ARG4 match after 3 clocks after the values of ARG1 and ARG2 match”.

  Hereinafter, the fact that the values of ARG1 and ARG2 match as shown in FIG. 4 is referred to as an assertion precondition. The fact that ARG3 and ARG4 match three clocks after the assertion precondition is satisfied is called assertion generation.

  FIG. 5 is an example in which a property called Lib defined by the designer is called to instantiate different assertion definitions called check1 and check2.

  The assertion of FIG. 5 verifies that “c and d match after 3 clocks after the values of a and b match” in check 1. On the other hand, check2 verifies that “g and h match after 3 clocks after the values of e and f match”.

  FIG. 6 is a block diagram illustrating the configuration of the assertion circuit according to the present embodiment. FIG. 6 is a diagram in which the assertion instances check1 and check2 in FIG. 5 are converted into one assertion circuit. The assertion circuit 80 in FIG. 6 includes a verification circuit unit 81 and an input selection unit 82.

  The verification circuit unit 81 includes a first comparator 83, a second comparator 84, a controller 86, and a result determination circuit 85. The controller 86 controls the result determination timing.

  The first selector of the input selection unit 82 receives the input signal a and the input signal e and outputs the input signal selected by the input selection signal CNT1 to the first comparator 83. The second selector of the input selection unit 82 receives the input signal b and the input signal f, and outputs the input signal selected by the input selection signal CNT2 to the first comparator 83. The third selector of the input selection unit 82 receives the input signal c and the input signal g of the input selection unit 82 and outputs the input signal selected by the input selection signal CNT3 to the second comparator 84. The fourth selector of the input selection unit 82 receives the input signal d and the input signal h, and outputs the input signal selected by the input selection signal CNT4 to the second comparator 84.

  The operation of the assertion circuit 80 in FIG. 6 will be described. The input selection unit 82 selects an input signal according to the settings of the input selection signals CNT <b> 1 to CNT <b> 4 and outputs the input signal to the first comparator 83 and the second comparator 84.

  The controller 86 receives the comparison result of the first comparator 83 and transmits a result determination instruction to the result determination circuit 85 three clocks after the inputs match.

  The result determination circuit 85 receives the result determination instruction from the controller 86 and simultaneously receives the comparison result of the second comparator 84. The result determination circuit 85 outputs the comparison result (hereinafter referred to as a determination result) of the second comparator 84 to the terminal RESULT.

  When the assertion circuit 80 of FIG. 6 is mounted as the first assertion circuit 74_1 of the simulation apparatus of FIG. 2, the first setting register 78_1 outputs the input selection signals CNT1 to CNT4 of the assertion circuit 80. On the other hand, the first verification result register 79_1 is connected to the terminal RESULT and receives the determination result. The verification program 61 reads the verification result from the first verification result register 79_1.

  According to the above configuration, the assertion verification contents can be switched by preparing a plurality of assertion control codes. Therefore, the assertion circuit 80 can be shared among a plurality of assertions.

  In this embodiment, as shown in the specification of FIG. 4, a setting is made that “the specification is satisfied if ARG3 and ARG4 match after 3 clocks after the values of ARG1 and ARG2 match”, and the assertion is referred to The signal name to be changed can be changed as an argument. Assertion that can be shared by setting "ARG3 and ARG4 meet the specifications if ARG3 and ARG4 match after n clocks after the values of ARG1 and ARG2 match" and specifying the number of clocks n as an argument The number of can also be increased.

  The simulation apparatus according to the present embodiment includes a setting register that can be controlled from a verification program, an assertion circuit whose function can be changed by the setting register, a verification program that transfers and controls an assertion control code to the setting register, and an assertion circuit And a register for storing the verification result. In the simulation apparatus described in Patent Document 1, there is a problem that the scale of the verification circuit mounted on the reconfigurable logic circuit increases as the number of assertions increases. However, such a problem can be solved by the simulation apparatus according to the present embodiment.

  A verification circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram illustrating a configuration of a simulation apparatus including a verification circuit according to the present embodiment. Referring to FIG. 7, the simulation apparatus includes a verification program 91 and a verification circuit 92.

  In this embodiment, it is assumed that 10 assertions are defined. Of the 10 assertions, the verification contents by the first, second, fourth, eighth and ninth assertions are similar, and the third, fifth, sixth, seventh and tenth of the assertion definition The contents of verification by assertion are similar. In the simulation apparatus described in Patent Document 1, since the same number of verification circuits as the number of defined assertions are required on the reconfigurable logic circuit, 10 verification circuits are realized on the reconfigurable logic circuit. There is a need to.

  In the simulation apparatus of this embodiment, assertions whose verification contents are similar to each other are grouped, and the grouped assertions share a single assertion circuit in the verification circuit 92. Further, the assertion function is realized by changing the operation of the assertion circuit based on the assertion control code set by the verification program 91.

  The ten assertions are divided into two groups of the first assertion control code 91a and the second assertion control code 91b in the verification program 91. The first assertion control code 91a shares the first assertion circuit 92a, and the second assertion control code 91b shares the second assertion circuit 92b.

  The first assertion circuit 92a is connected to the setting register 92c and the verification result register 92d. The second assertion circuit 92b is connected to the setting register 92e and the verification result register 92f.

  The verification program 91 changes the first assertion control code 91a set in the setting register 92c and also changes the second assertion control code 91b set in the setting register 92e. As a result, the two assertion circuits, that is, the first assertion circuit 92a and the second assertion circuit 92b can verify the circuit to be designed for the ten assertions. At this time, it is possible to suppress an increase in the circuit scale of the verification circuit realized in the reconfigurable logic circuit accompanying the increase in assertion. Therefore, the problem in the simulation apparatus described in Patent Document 1 is solved.

  A simulation apparatus according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram illustrating a configuration of a simulation apparatus including the verification circuit according to the present embodiment.

  Referring to FIG. 8, the difference between the simulation apparatus according to the present embodiment and the simulation apparatus according to the first embodiment is as follows. That is, the verification circuit 77 further includes first to n-th assertion precondition checking registers 100_1 to 100_n for each of the assertion circuits. The verification program 61 further includes first to nth assertion generation schedules 101_1 to 101_n.

  FIG. 9 is a flowchart for generating an assertion generation schedule in the simulation apparatus including the verification circuit according to the present embodiment. Referring to FIG. 9, it is determined whether or not the simulation is finished (step S30), and when the simulation is finished (Yes in step S30), the process is finished. If the simulation has not ended (No in step S30), the assertion control code in the verification program 61 is set in the first to nth setting registers 78_1 to 78_n of each assertion circuit (step S31).

  Next, the first to nth assertion precondition checking registers 100_1 to 100_n are read to check whether or not the assertion precondition is generated at the current time (step S32), and when the assertion precondition is generated, the generation time ( Or the timing) and what control code of the assertion circuit is registered in the assertion generation schedule (step S36).

  When there are a plurality of assertions sharing the assertion circuit, all the assertion control codes are sequentially set in the first to nth setting registers 78_1 to 78_n of the assertion circuit, and whether all the assertion preconditions are generated at the same time Is checked (step S33). If all the assertion preconditions are checked (Yes in step S33), only one clock is supplied (step S34).

  By repeating steps S30 to S34 until the simulation end time, the assertion generation schedule at all times is extracted (step S36).

  FIG. 10 shows an example of assertion (property declaration) in this embodiment. Referring to FIG. 10, the property Lib3 is a property defined by the designer, and indicates that “when ARG9 and ARG10 match, the specification is satisfied when ARG11 and ARG12 match in the same cycle”.

  In the case of the assertion in FIG. 10, the assertion occurrence confirmation (step S32 in FIG. 9) is performed as follows. That is, whether or not the assertion precondition is generated at the assertion occurrence time is confirmed by confirming whether or not “ARG9 = ARG10” is satisfied. In the case of the assertion shown in FIG. 10, the check is completed within one cycle. However, the assertion may include a sequence of multiple clocks.

  FIG. 11 shows an example of assertion call (property instantiation) in this embodiment. Referring to FIG. 11, Lib3 defined by the designer is called, and assertions of check5 to check8 are instantiated. In the case of FIG. 11, four assertion control codes share one assertion circuit.

  FIG. 12 is a block diagram illustrating the configuration of the assertion circuit according to the present embodiment. The assertion circuit 180 is a circuitization of the assertion of FIG. Referring to FIG. 12, the OCCUR signal is further added to the assertion circuit 180 with respect to the assertion circuit 80 of FIG. 6. In the assertion circuit 180, when the observation signals selected by the ARG 9 and the ARG 10 match, the OCCUR signal becomes active.

  When the assertion circuit 180 of FIG. 12 is installed in the simulation apparatus of FIG. 8, the OCCUR signal is connected to one of the first to nth assertion precondition checking registers 100_1 to 100_n. The verification program 60 reads the contents of the first to nth assertion precondition checking registers 100_1 to 100_n via the verification program I / F 51, thereby checking whether or not an assertion precondition has occurred.

  FIG. 13 is a diagram illustrating an example of an assertion generation schedule in the present embodiment. Referring to FIG. 13, an assertion generation schedule for one assertion circuit generated according to the assertion generation schedule extraction flow of FIG. 9 is shown. Each row in FIG. 13 indicates a simulation time, and each column indicates an assertion definition formula. In addition, the occurrence of assertion preconditions at each simulation time is indicated by a circle.

  At times (clocks) 1, 3, 5, 7, 8, 11, 12, 13, 14, 17, and 18 when the assertion preconditions do not overlap, the assertion control code corresponding to the generation time of the assertion preconditions is displayed. The first to nth setting registers 78_1 to 78_n of each assertion circuit are set. On the other hand, at times 4, 6 and 10 at which the generation of assertion preconditions overlaps at the same time, any one assertion control code is selected and set in the first to nth setting registers 78_1 to 78_n of each assertion circuit. And run the simulation.

  For the assertion control codes that are not set because the assertion definition formulas overlap at the same time, after the above simulation is completed, the assertion control codes are assigned to the first to nth setting registers 78_1 to 78_1 of each assertion circuit in the next simulation. Set to 78_n and execute the simulation. The simulation is repeated until all assertion control codes are set.

  FIG. 14 is a flowchart of the verification method according to the present embodiment. Steps S10 to S19 in FIG. 14 are the same as those in the flowchart in the first embodiment, and thus description thereof is omitted.

  The verification program 61 refers to the assertion generation schedules 101_1 to 101_n and determines whether or not there is one that changes the assertion control code at the next clock (step S40). If there is nothing to change (No in step S40), the process proceeds to step S11.

  On the other hand, if there is a change in the assertion control code (Yes in step S40), it is determined which number of the assertion control code corresponds to the number of the assertion circuit based on the assertion generation schedules 101_1 to 101_n. Then, any one of the first assertion control code 62_1_1 to 62_1_m to the nth assertion control code 62_n_1 to 62_n_k is selected as the corresponding assertion control code, and the IO port 50 and the verification program I / F 51 are selected as the corresponding assertion control code. Then, the first to nth setting registers 78_1 to 78_n on the verification circuit 77 are set (step S41), and the process proceeds to step S11.

  After the simulation is completed, the assertion generation schedules 101_1 to 101_n are referred to, and when the assertion to be verified remains, the processes of steps S10 to S41 are performed again, and the simulation is repeated until there is no assertion to be verified.

  According to the present embodiment, when the generation time of the assertion sharing the assertion circuit 180 does not overlap, the assertion control code is set in the setting register of the assertion circuit 180 before the assertion generation time, and simulation is performed. The number of simulations can be reduced.

  Although the above description has been made based on examples, the present invention is not limited to the above examples.

It is a block diagram which shows the structure of the verification circuit which concerns on the 1st Embodiment of this invention. 1 is a block diagram showing a configuration of a verification circuit according to a first exemplary embodiment of the present invention. It is a figure which shows the flowchart of the verification method which concerns on 1st Example of this invention. The example of the assertion (property declaration) in the 2nd Example of this invention is shown. An example of assertion (property instantiation) in the second embodiment of the present invention will be described. It is a block diagram which shows the structure of the assertion circuit based on 2nd Example of this invention. It is a block diagram which shows the structure of a simulation apparatus provided with the verification circuit based on 3rd Example of this invention. It is a block diagram which shows the structure of a simulation apparatus provided with the verification circuit based on the 4th Example of this invention. It is a flowchart for producing | generating the assertion generation schedule in a simulation apparatus provided with the verification circuit based on the 4th Example of this invention. The example of assertion (property declaration) in the 4th example of the present invention is shown. An example of assertion call (property instantiation) in the fourth embodiment of the present invention will be described. It is a block diagram which shows the structure of the assertion circuit based on the 4th Example of this invention. It is a figure which shows the example of the assertion generation schedule in 4th Example of this invention. It is a flowchart of the verification method which concerns on 4th Example of this invention.

Explanation of symbols

10, 60 Computer 11, 61, 91 Verification program 20, 70 Reconfigurable logic circuit 21, 71 Design target circuit 27, 77, 92 Verification circuit 28, 78, 92c, 92e Setting register 50 IO port 51 Verification program I / F
62_1_1 to 62_1_m first assertion control code 62_n_1 to 62_n_k n assertion control code 72 break control circuit 73 clock control circuit 74 assertion circuit 74_1 to 74_n first to nth assertion circuit 75 break request signal 76 break signal 78_1 to 78_n first to N-th setting registers 79_1 to 79_n first to n-th verification result registers 80 and 180 assertion circuits 81 and 181 verification circuit units 82 and 182 input selection units 83 and 183 first comparators 84 and 184 second comparators 85 and 185 results Determination circuit 86, 186 Controller 91a First assertion control code 91b Second assertion control code 92a First assertion circuit 92b Second assertion circuits 92d, 92f Verification result register 1 00_1 to 100_n 1st to nth assertion prerequisite check registers 101_1 to 101_n 1st to nth assertion generation schedule

Claims (7)

A design target circuit and a verification circuit for verifying the design target circuit;
The reconfigurable logic circuit is characterized in that the verification circuit is shared for verification based on a plurality of assertions included in assertion-based verification.   The reconfigurable logic circuit according to claim 1, wherein the verification circuit is shared for verification based on similarities among a plurality of assertions included in the assertion-based verification. A setting register for recording a control code for selecting which of the plurality of assertions included in the assertion-based verification is to be used to verify the design target circuit;
The reconfigurable logic circuit according to claim 1, wherein the verification circuit verifies the design target circuit based on an assertion selected by a control code recorded in the setting register. A verification method using a reconfigurable logic circuit comprising a design target circuit and a verification circuit for verifying the design target circuit,
Performing verification based on a first assertion included in the assertion-based verification by the verification circuit;
And a step of performing verification based on a second assertion included in the assertion-based verification by the verification circuit.   The verification method according to claim 4, wherein the first assertion and the second assertion are similar to each other. Recording a control code for selecting which of the plurality of assertions included in the assertion-based verification should verify the design target circuit in a setting register provided in the reconfigurable circuit;
The verification method according to claim 4, further comprising a step of verifying the design target circuit based on an assertion selected by the control circuit recorded in the setting register by the verification circuit.   A design target circuit and a verification circuit for verifying the design target circuit, and connected to a reconfigurable logic circuit configured to share the verification circuit for verification based on a plurality of assertions included in the assertion-based verification A verification program that causes a computer to transmit a control code that selects which of the plurality of assertions is to be used to verify the design target circuit.

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