JP2011081760A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To develop a high-quality LSI in a short time by reducing processes required for designing and verifying LSI development. <P>SOLUTION: An information processor includes: an assertion property extraction part 11 which extracts properties from an assertion description file 20 input to an HDL conversion device 10; an assertion language-HDL language conversion database 13 storing conversion information for use in conversion between an assertion description language and a hardware description language; and an HDL conversion part 12 which converts the extracted properties to operation descriptions in the hardware description language, on the basis of the conversion information, and outputs the operation descriptions as an HDL file 40 including the operation descriptions. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus. More specifically, the present invention relates to an information processing apparatus suitable for designing a large-scale integrated circuit.

  Large scale integration (LSI) is designed using a hardware description language (HDL). The scale of LSI is increasing year by year, and accordingly, the time spent for verification of the logical system is increased, which is a problem. For this reason, the proposal and implementation of a more efficient verification method is desired.

  As one of the verification methods of this logical system, a circuit operation based on the specification of the verification target (Design Under Test: DUT) is defined, and a warning is issued when an operation that violates this is detected. A technique called assertion using a certain PSL (Property Specification Language) is already known.

  In Patent Document 1, for the purpose of improving verification efficiency in LSI development, verification is performed based on the visual state transition diagram, timing chart, processing sequence diagram, and the like used when creating a circuit specification. An assertion generation system is disclosed that automatically converts power properties into an assertion description language. A property is a plain text that defines the intended and expected behavior of a design product to be verified. For example, the relationship between the reception and response of a request signal and an approval signal in an arbiter circuit is time-series. They are defined by constraints, the valid state of time series constraints, and circuit specifications that are prohibited.

  Patent Document 2 discloses a number of design processes required to create a top-level hierarchical circuit of a semiconductor integrated circuit by using a circuit specification as an input for the purpose of reducing man-hours in LSI development and improving design quality. An automatic circuit generation device that unifies these is disclosed.

  However, in the design and verification of conventional LSI development, “Design work by HDL description”, “Verification content description work by PSL”, “Pseudo external connection device (model) creation work to be operated on test bench” Therefore, each work process of “circuit correction work for a defect (design error) discovered by verification” has to be performed, and there is a problem that the LSI development period is long.

  On the other hand, in the “assertion generation system” described in Patent Document 1, an environment necessary for functional verification is generated automatically only by creating an LSI specification. In the “automatic circuit generation device”, it is possible to improve the reliability of verification in LSI development and reduce man-hours by automatically generating the highest hierarchical circuit of the LSI. However, the techniques described in Patent Document 1 and Patent Document 2 described above have not solved the problem that man-hours are required for "circuit correction work for a defect (design error) discovered by verification".

  Therefore, in the present invention, in the LSI development, “design work based on HDL description” and “pseudo external connection device (model) to be operated on the test bench” which have been manually performed based on the specifications of the LSI. Providing an information processing device that enables the development of high-quality LSIs in a short period of time by reducing the processes required for LSI development design and verification by generating "work" from assertions written in a verification language The purpose is to do.

  In order to achieve this object, an information processing apparatus according to claim 1 is an information processing apparatus used for verification of a logical system in development of a large-scale integrated circuit, and includes a property from an assertion description file input to the information processing apparatus. Extraction means for extracting the data, storage means for storing the conversion information used for conversion between the assertion description language and the hardware description language, and the property extracted by the extraction means in the behavioral description of the hardware description language based on the conversion information. Conversion means for converting and outputting as a hardware description language file including the operation description.

  Further, in the information processing apparatus according to claim 1, the extraction unit extracts a module name to be inspected from the assertion description file, and the conversion unit converts the hardware based on the module name. To hardware description language.

  According to a third aspect of the present invention, in the information processing apparatus according to the first or second aspect, the extracting means extracts the bit width of the register or wire signal specified in the assertion description file, and the converting means Converts to a hardware description language based on the bit width of the signal.

  According to a fourth aspect of the present invention, in the information processing apparatus according to any one of the first to third aspects, the extracting means extracts the hierarchical structure of the assertion description file, and the converting means is based on the hierarchical structure. It converts to a hardware description language.

  According to a fifth aspect of the present invention, in the information processing apparatus according to any one of the first to fourth aspects of the present invention, which information of the conversion information is converted into the hardware description language file. It is provided with comment insertion means for enabling description.

  According to the present invention, it is possible to reduce the processes required for designing and verifying LSI development and to develop a high-quality LSI in a short period of time.

It is a schematic diagram which shows an example of the process of the conventional logic system verification. It is a schematic diagram which shows an example of the process of logic system verification using the information processing apparatus which concerns on this embodiment. It is an example of the functional block diagram of the information processing apparatus which concerns on this embodiment. It is an example of the assertion description file before conversion. It is an example of the operation | movement description part of the HDL file after conversion. It is an example of the assertion language-HDL language conversion information stored in the assertion language-HDL language conversion database. It is an example of an HDL structure file. It is an example of the HDL file after conversion. It is another example of the assertion description file before conversion. It is another example of the HDL file after conversion. It is another example of the assertion language-HDL language conversion information stored in the assertion language-HDL language conversion database. It is another example of the assertion description file before conversion. It is another example of the HDL file after conversion. It is another example of the HDL file after conversion. This is an example of correspondence between a functional expression and its meaning in an assertion description language. It is another example of the assertion description file before conversion. It is another example of the HDL file converted based on the assertion description file shown in FIG. It is explanatory drawing of the error factor detection by an error notification means. It is explanatory drawing of the error factor detection by a logic judgment means. It is an example of graphical data. It is an example of the HDL structure file created based on the graphical data shown in FIG. It is another example of the assertion description file before conversion. It is an example of the HDL file converted based on the assertion description file shown in FIG.

  Hereinafter, the configuration according to the present invention will be described in detail based on the embodiment shown in FIGS.

  The information processing apparatus (HDL conversion apparatus 10) according to the present embodiment includes an extraction unit (assertion) that extracts properties from the assertion description file 20 input to the information processing apparatus when verifying using HDL design and assertion in LSI development. A property extraction unit 11), storage means (assertion language-HDL language conversion database 13) storing conversion information used for conversion between the assertion description language and the hardware description language, and a property extracted by the extraction means based on the conversion information. Conversion means (HDL conversion unit 12) for converting into a hardware description language behavior description and outputting it as a hardware description language file (HDL file 40) including the behavior description. "HD" is an item that was done manually The design work "and by description" task of creating pseudo external connection device to operate on the test bench (Model) ", and generates an HDL using assertions described in verification language. By using the technique described in Patent Document 1, an environment necessary for function verification can be generated simply by creating an LSI specification.

(LSI design and verification process)
First, for comparison with the present embodiment, FIG. 1 shows a schematic diagram of a design and verification process in conventional LSI development. Hereinafter, a conventional design and verification process will be described with reference to FIG.

  First, the specifications of the LSI to be developed are created (specification creation: S901). Next, using the LSI specifications created in S901, HDL design (HDL creation: S902) and external connection device creation (connection model creation: S904) are performed. Here, HDL creation (S902) and connection model creation (S904) are manual. Also, an assertion description is created (assertion description: S903) using the LSI specification created in S901. The assertion description (S903) may be manual or automatic.

  Next, simulation verification is performed using the HDL created in S902, the assertion description created in S903, the connection model created in S904, and the test scenario (S905) created separately (S906).

  In the simulation verification (S906), if a design mistake is found, the specification is corrected (return to S901) and the HDL is corrected (return to S902). If a verification error is found, the assertion description is corrected (returning to S903) and / or the connection model is corrected (returning to S904). On the other hand, if no design error or verification error is found, the verification ends (S907).

  Next, FIG. 2 shows a schematic diagram of a design and verification process in LSI development by the information processing apparatus according to the present embodiment. Hereinafter, the design and verification process in this embodiment will be described with reference to FIG.

  First, the specification of the LSI to be developed is created (specification creation: S101). Next, an assertion description is created (assertion description: S103) using the LSI specification created in S101. The assertion description (S103) may be manual or automatic.

  Next, using the assertion description created in S103, HDL design (HDL creation: S102) and external connection device creation (connection model creation: S104) are automatically created.

  Next, simulation verification is performed using the HDL created in S102, the assertion description created in S103, the connection model created in S104, and the test scenario (S105) created separately (S106).

  If a design mistake is found in the simulation verification (S106), only the correction of the specification (return to S101) is performed, and then the assertion description, HDL, and connection model are created (S103, S102, S104). On the other hand, if no design error or verification error is found, the verification ends (S907).

(Configuration and operation of information processing device)
An example of a functional block diagram of the information processing apparatus according to the present embodiment is shown in FIG. The operation will be described below with reference to FIG. The information processing apparatus illustrated in FIG. 3 is an HDL conversion apparatus 10 that converts an assertion description file 20 into an HDL file 40. As the hardware of the HDL conversion device 10, a known personal computer or the like can be used. An input unit for inputting data, a display unit such as a display, a communication unit for performing data communication, CPU as a control means for controlling the entire apparatus, RAM used as a work area of the CPU, a recording device (HDD) storing various programs and data for operating the CPU, and reading of data on the recording medium / A recording medium drive device that performs writing is provided. The extraction means, conversion means, comment insertion means, function execution means, error notification means, logicality judgment means, graphical information conversion means, and signal conversion means described in detail below are the CPU of the HDL conversion apparatus 10. , RAM, storage device (HDD), etc. are realized in cooperation.

  First, an assertion description file 20 and an HDL structure file 30 are given to the HDL conversion apparatus 10. Here, the HDL structure file 30 includes at least one (or all) of information such as “module instance configuration”, “register name and its bit length”, “wire name and its bit length”, and “module”. The information of “connection signal and input / output between” is included.

  The assertion property extraction unit 11 of the HDL conversion device 10 extracts properties in the assertion description file 20 and transmits the information to the HDL conversion unit 12. Also, the HDL conversion unit 12 of the HDL conversion device 10 refers to the assertion language-HDL language conversion database 13 with the property extracted by the assertion property extraction unit 11 as operation information (also referred to as HDL operation description or HDL description). Convert. Further, the HDL conversion unit 12 generates the HDL file 40 based on the HDL structure file 30 and the operation information.

  Hereinafter, an operation example of the HDL conversion device 10 according to the present embodiment will be described with a specific example. FIG. 4 shows an assertion description file 20 before conversion described in PSL, and FIG. 5 shows an assertion description file 20 shown in FIG. 4 converted to Verilog-HDL by the HDL conversion device 10 (one of the HDL file 40). Part). A, B, C, D, E, F, and G in the figure are "register name and value", "wire name and value", "signal name and change timing", "event", etc. Indicates any condition or operation.

  FIG. 6 shows an example of assertion language-HDL language conversion information (conversion information) 14 stored in the assertion language-HDL language conversion database 13. As shown in FIG. 6, the assertion language-HDL language conversion information 14 extracts “conditional order” and “table information” for extracting and automatically converting condition expressions in this portion. High conditions are used for the conversion. The priority order can be arbitrarily set by the user.

  FIG. 7 shows an example of the HDL structure file 30 given to the HDL conversion apparatus 10. As shown in FIG. 7, the HDL structure file 30 includes “module name”, “register wire name”, “bit width”, “module configuration information”, and the like. Note that the present invention is not limited to the example shown in FIG. 7, and the number of register wires and instanced lower modules is variable.

  Next, FIG. 8 shows an output file (HDL file 40) when the HDL conversion device 10 is given the assertion description file 20 shown in FIG. 4 and the HDL structure file 30 shown in FIG. The HDL file 40 includes a module configuration description converted from the HDL structure file 30 (FIG. 7) and a behavior description portion (FIG. 5) converted from the assertion description file 20 (FIG. 4).

  Here, when the “module name to be inspected” is not included in the HDL structure file 30, it can be extracted from the assertion description file 20 and automatically generated. 9 and 10 show an example in which the HDL module name is converted from the assertion description file 20.

  As shown in FIGS. 9 and 10, the extracting unit can extract the module structure other than the property from the assertion description file 20 and convert it into the HDL description. By doing so, it is not necessary to manually describe the module name in the description of the HDL structure file 30 in advance. Therefore, human errors can be reduced, design quality can be improved, and man-hours can be reduced.

  Further, when “register name and its bit length” and “wire name and its bit length” are not included in the HDL structure file 30, it can be extracted from the assertion description file 20 and automatically generated. it can. FIG. 11 shows an example of the assertion language-HDL language conversion information 14 for predicting and converting the bit length of a register or wire from information set in the property or the like in the assertion description file 20. FIG. 11 shows an example when the signal “a” is 16 bits, and conversion is performed using a factor having a high priority. The priority order can be arbitrarily set by the user.

  This eliminates the need to manually describe the number of signal bits in the description of the HDL structure file 30 in advance. Therefore, human errors can be reduced, design quality can be improved, and man-hours can be reduced.

  Here, in the PSL, when a module is instantiated at a lower level of the module, “higher module name.lower module name” is described, and when a signal in the lower module is described, the instance is assigned to the higher module. In the assertion file, write “Lower module name. Signal name”.

  From this, when the “module instance configuration” is not included in the HDL structure file 30, it can be extracted from the assertion description file 20 and automatically generated. FIGS. 12 and 13 show examples of conversion of the assertion description file 20 that is instantiated in the module and has a hierarchical structure into the HDL file 40.

  As shown in FIG. 12 and FIG. 13, in a signal having a hierarchical structure in the assertion, the hierarchical structure is recognized at the time of assertion extraction, instance description is performed at the time of HDL conversion, and a plurality of files are created It is.

  By doing so, it is not necessary to manually describe the hierarchical structure of modules in the description of the HDL structure file 30 in advance. Therefore, human errors can be reduced, design quality can be improved, and man-hours can be reduced.

(Other embodiments)
Hereinafter, other embodiments of the information processing apparatus according to the present invention will be described. Note that a description of the same points as in the above embodiment will be omitted.

  The information processing apparatus according to the present embodiment preferably includes a comment insertion unit. That is, as shown in FIG. 14, the conversion is performed using any information of the assertion language-HDL language conversion information 14 stored in the assertion language-HDL language conversion database 13 in the description of the HDL file 40 after conversion. It is preferable that the user can describe what has been done as a comment (language conversion information). The “language conversion information” in FIG. 14 includes language information before conversion, language information after conversion, used conversion information table name, value of a row in which the corresponding information of the used conversion information table is described, and the like. This includes information. Moreover, the description of a comment can be made from an input part, for example.

  In this way, by further providing comment insertion means, the conversion information used in the description of the HDL structure file 30 can be confirmed, so that the quality of the design can be improved and the number of man-hours due to rework can be reduced.

  The information processing apparatus according to the present embodiment preferably further includes a function execution unit that extracts a functional expression of the assertion description from the given assertion description file 20 and generates an HDL description capable of continuous operation.

  FIG. 15 shows a correspondence example between the assertion description and the meaning of the assertion description. In the assertion description, a functional expression of a complicated operation as shown in FIG. 15 is possible.

  Therefore, the function execution means uses the assertion language-HDL language conversion information 14 stored in the assertion language-HDL language conversion database 13 for the functional expression as shown in FIG. Extraction is performed from the file 20, and conversion into an HDL description that performs a complicated operation as shown in FIG.

  In the example shown in FIG. 16 and FIG. 17, “property1” indicates that C is asserted at the next clock asserted by B and D is asserted at the next clock, and describes a continuous operation. Yes. In “property2”, “isknown” (see FIG. 15), which is a description that returns (asserts) 1 if an indefinite value is used.

  As described above, by further providing function execution means, it is possible to create a more accurate HDL description by using a functional expression that can be described by assertion for automatic generation of HDL. Therefore, it is possible to design an LSI capable of executing a more complicated operation, and to improve the quality of the LSI.

  In addition, the information processing apparatus according to the present embodiment preferably includes an error notification unit that notifies the user when information cannot be extracted from the assertion language-HDL language conversion database 13 (that is, in the case of an error).

  As shown in FIG. 18, the assertion description 15 extracted by the assertion property extraction unit 11 is sent to the HDL conversion unit 12, and the corresponding assertion language-HDL language conversion information 14 is retrieved from the assertion language-HDL language conversion database 13. If there is no conversion information with the same description and the conversion information cannot be extracted, the error notification means displays an error message and the corresponding assertion description on the display unit such as a display, and converts it to the user. This is to notify that it is impossible. In addition, it is good also as notifying to a user by audio | voice output from a speaker, the printing from a printer, etc. instead of the display on a display part, or this together.

  In this way, by further providing an error notification means, it is possible to detect the error content at the time of HDL generation, and to allow the user to recognize that the generation of the HDL file 40 cannot be completed and the error location. Therefore, it is possible to improve the quality of the LSI without errors remaining in subsequent processes. In addition, man-hours due to rework can be reduced.

  Further, the information processing apparatus of the present embodiment determines the logicality of the contents described in the assertion description when converting the assertion description file 20 to the HDL file 40, and the determination result, for example, a logically incorrect operation. It is also preferable to provide a logic judgment means for notifying the user of an error when the possibility is high. Specifically, for example, when the assertion language-HDL language conversion information 14 used for a signal in the apparatus is held and the same condition is used a plurality of times, the operation is logically erroneous. As an error.

  FIG. 19 shows an example of the operation of the logic judgment means, in which a description in which different values are erroneously input to the same signal under the same condition is shown. For example, as shown in FIG. 19, the logicality determination unit recognizes that the same assertion-HDL conversion information has been used a plurality of times for the same signal and the same condition, and notifies the user as an error.

  As described above, by further including the logic determination means, it is possible to easily recognize and analyze the cause of the operation failure in the generated HDL. Therefore, it is possible to improve the quality of the LSI without errors remaining in subsequent processes. In addition, man-hours due to rework can be reduced.

  In addition, the information processing apparatus according to the present embodiment can use the graphical data 50 created by a graphical editor (such as CAD) as the HDL structure file 30 when converting the assertion description file 20 to the HDL file 40. It is also preferable to provide information conversion means.

  20 and 21 show an example of the operation of the graphical information conversion means. The HDL structure file 30 shown in FIG. 21 is an example of the HDL structure file 30 created based on the graphical data 50 shown in FIG.

  As described above, by further providing the graphical information conversion means, visual information can be used for HDL generation, and the user can easily imagine the HDL structure. Therefore, it is possible to improve the quality of the LSI without errors remaining in subsequent processes. In addition, man-hours due to rework can be reduced.

  In addition to the sequential operation using sampling in the assertion description as described above, the information processing apparatus according to the present embodiment includes a signal conversion unit that performs conversion into an HDL description including a combinatorial operation that directly connects signals. It is also preferable to provide.

  Here, in the assertion language such as PSL, the condition in the property is indicated, and the state of the register and the signal when the condition is satisfied is verified, and the sequential operation using sampling is mainly performed. Therefore, if sampling definition (for example, @posedge A, default clock = posedge A, etc.) is not performed in PSL, it is necessary to perform sampling for each unit time for simulating an assertion and check properties.

  Therefore, in the case of an assertion description in which sampling is not defined, for example, in the case of Verilog-HDL, the signal conversion means uses not always the sequential operation using sampling by using always @ *, assign statement, etc. Conversion to an HDL description including combinatorial operations for direct connection is performed.

  Thus, by further providing the signal conversion means, it is possible to perform LSI design with a higher degree of freedom and improve the design quality of the LSI.

  The above-described embodiment is a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the gist of the present invention.

  For example, in the above embodiment, an assertion description in PSL has been described as an example of information before conversion, but it can also be applied to other assertion descriptions. Also, the description example in the hardware description language in Verilog-HDL (Verilog) as the information after conversion has been described, but other hardware description such as VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware Description Language) It can also be applied to languages.

  Moreover, the conversion control to HDL based on the assertion description by the information processing apparatus demonstrated above can also be performed with a program (information processing program). For example, the information processing program is preferably stored in a storage medium of the information processing apparatus. Further, the present invention is also applied to an aspect of a recording medium (recording medium on which an information processing program is recorded) on which an information processing program is recorded so as to be executable by the information processing apparatus.

10 HDL conversion device (information processing device)
11 Assertion property extraction unit (extraction means)
12 HDL conversion unit (conversion means)
13 Assertion language-HDL language conversion database (storage means)
14 Assertion language-HDL language conversion information 15 Extracted assertion description 20 Assertion description file 30 HDL structure file 40 HDL file 50 Graphical data

JP 2006-99518 A JP 2006-285947 A

Claims (5)

An information processing apparatus used for verification of a logic system in large-scale integrated circuit development,
Extraction means for extracting properties from the assertion description file input to the information processing apparatus;
Storage means for storing conversion information used for conversion between the assertion description language and the hardware description language;
Conversion means for converting the property extracted by the extraction means into a behavioral description of a hardware description language based on the conversion information, and outputting as a hardware description language file including the behavioral description. Processing equipment. The extraction means extracts a module name to be examined from the assertion description file,
The information processing apparatus according to claim 1, wherein the conversion unit converts the information into a hardware description language based on the module name. The extraction means extracts a bit width of a register or wire signal specified in the assertion description file,
The information processing apparatus according to claim 1, wherein the conversion unit converts the information into a hardware description language based on a bit width of the signal. The extracting means extracts a hierarchical structure of the assertion description file;
The information processing apparatus according to claim 1, wherein the conversion unit converts the information into a hardware description language based on the hierarchical structure.   5. The comment insertion means for enabling the hardware description language file to describe which of the pieces of conversion information is used for conversion. Information processing device.

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