JP5568244B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming an element isolation film.

  In an integrated circuit of a semiconductor device, an element isolation region is formed in order to electrically isolate adjacent elements. Hereinafter, a method for forming STI (Shallow Trench Isolation) will be described. 1A to 1C and 2D to 2F are cross-sectional views illustrating a part of a manufacturing process of a conventional semiconductor device.

  First, as shown in FIG. 1A, a silicon oxide film 104 and a silicon nitride film 106 are formed on a silicon substrate 102 by a known method. Next, as shown in FIG. 1B, a trench pattern (concave portion) 108 is formed by a photolithography process and an etching process.

  Next, the silicon substrate 102 is oxidized to form a silicon oxide film 110 on the surface of the silicon substrate 102 as shown in FIG. Subsequently, as shown in FIG. 2D, a silicon oxide film 112 is buried in the trench 108 by HDP-CVD (High Density Plasma-Chemical Vapor Deposition). The film forming conditions at this time are, for example, SiH4: 60 sccm, O2: 120 sccm, Ar: 100 sccm, Source-RF output: 3000 W, and Bias-RF output: 1500 W.

  Next, the surface of the silicon oxide film 112 is planarized by CMP (Chemical Mechanical Polishing) as shown in FIG. Thereafter, as shown in FIG. 2F, the silicon nitride film 106 is removed by a known method. Through the above manufacturing process, the STI (element isolation region) 114 filled with the silicon oxide film 112 is formed on the silicon substrate 102, and adjacent elements can be electrically isolated from each other.

In JP 2008-103645 A (FIGS. 6 to 8, paragraphs [0024] to [0034]), a silicon oxide film is deposited by HDP-CVD and STI is embedded, and then a fine region of a memory device is formed. A method of selectively removing the silicon oxide film in the cell portion and then filling it with an SOG film having good fluidity is disclosed.
JP 2008-103645 A

  Next, problems and disadvantages of the prior art will be described with reference to FIGS. When the STI slit becomes narrower as the integrated circuit becomes finer, voids (voids) are formed in the HDP-CVD film 114 in a fine region such as a cell portion of a memory device as shown on the left side of FIG. ) 116 occurs. The void 116 causes a defect such as a short circuit of the gate wiring in a later process, which causes a decrease in product yield.

  In order to prevent the generation of voids, it is necessary to reduce the D / S ratio of HDP-CVD. Here, the D / S ratio is a coefficient calculated as (D + S) / S from the deposition (D) and sputtering (S) rates during HDP-CVD film formation, and the smaller the value, the more the sputtering ratio. growing. However, when the D / S ratio is reduced (for example, about 2 with respect to 5 in general), as shown in FIG. 4, the Si substrate 102 of the element forming portion is scraped by sputtering, and a desired Si pattern dimension is obtained. There is a problem that circuit failure occurs due to damage to the Si substrate 102. (Especially, isolated patterns in the peripheral circuit section tend to be cut off easily.)

  As a measure for solving this problem, a method of forming trench processing in two steps is conceivable. A manufacturing method thereof will be described with reference to FIGS. 5A to 5D, FIGS. 6E to 6G, and FIGS. 7H and 7I. First, as shown in FIG. 5A, a silicon oxide film 204 and a silicon nitride film 206 are formed on a silicon substrate 202.

  Next, as shown in FIG. 5B, the trench 208 is processed only in the rough pitch portion by a photolithography process and an etching process. Subsequently, as shown in FIG. 5C, an HDP-CVD film 210 is formed on both the fine pitch portion and the rough pitch portion. The HDP-CVD film forming conditions at this time are such that the D / S ratio is about 5 and no void is generated and the silicon nitride film 206 is not scraped.

  Thereafter, as shown in FIG. 5D, the HDP-CVD film 210 in the fine pitch portion is removed. Next, as shown in FIG. 6E, trenches 212 are formed in the fine pitch portions. Thereafter, as shown in FIG. 6F, a silicon oxide film 214 is formed on the inner surface of the trench 212 in the fine pitch portion.

  Next, as shown in FIG. 6G, an HDP-CVD film 216 is formed on both the fine pitch portion and the rough pitch portion. The HDP-CVD film formation conditions at this time are such that the D / S ratio is about 2 and no void is generated in the fine pitch portion. Subsequently, the surface of the silicon oxide film 216 is planarized by CMP (Chemical Mechanical Polishing) as shown in FIG. Thereafter, as shown in FIG. 7I, the silicon nitride film 206 is removed by a known method. Through the above manufacturing process, an STI (element isolation region) filled with the silicon oxide film 216 is formed on the silicon substrate 202, and adjacent elements can be electrically isolated from each other. Note that the rough pitch portion having a pattern that can be easily cut is covered with the first HDP-CVD film 210, and thus the silicon substrate 202 is not cut.

  However, the methods shown in FIGS. 5A to 5D, FIGS. 6E to 6G, and FIGS. 7H and 7I have the disadvantage that the number of steps is large and the manufacturing cost increases. .

In Japanese Patent Application Laid-Open No. 2008-103645 described above, this problem is solved by a method of forming a film once with a void formed by HDP-CVD and then removing only a fine region and embedding with SOG. However, a film using SOG has a very fast wet etch rate and poor STI step controllability. In addition, when a defect such as a scratch due to CMP is introduced, the defect is easily enlarged and a defect such as a short circuit of the gate wiring is likely to occur.

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a good STI region while suppressing an increase in the number of steps and manufacturing cost.

In order to solve the above-described problems, the present invention provides a method for manufacturing a semiconductor device in which element isolation is performed by STI, wherein a first trench on a semiconductor substrate and a second trench different from the first region are provided. Forming a second trench having a width wider than that of the first trench in a region ; forming a first insulating film covering the first region including the inside of the first trench; and Forming the first insulating film without voids so as to cover the second region including the inside of the second trench; leaving the first insulating film covering the second region ; and forming a second insulating film which is inside HDP-CVD film of the first trench; step and removing including the inside of said first trench with said first insulating film covering the first region The first trench can be Embedded with, characterized in that it comprises a step of forming a second insulating film on the first insulating film covering the second region.

  According to the present invention described above, the fine pitch portion can be embedded without voids while preventing the semiconductor substrate from being scraped when forming the insulating film in the trench. As a result, short circuit of the gate wiring due to voids, circuit malfunction due to semiconductor substrate scraping, and the like are prevented, and the yield of semiconductor elements is improved.

Further, as shown in FIGS. 5A to 5D, FIGS. 6E to 6G, and FIGS. 7H and 7I, trench processing is separately performed twice at the fine pitch portion and the rough pitch. Compared with the method of forming separately, the number of steps can be reduced, and an increase in manufacturing cost can be suppressed.

1A to 1C are cross-sectional views illustrating a part of a manufacturing process of a conventional semiconductor device. 2D to 2F are cross-sectional views illustrating a part of the manufacturing process of the conventional semiconductor device. FIG. 3 is a cross-sectional view for explaining a problem in the case of employing a conventional semiconductor device manufacturing process. FIG. 4 is a cross-sectional view for explaining problems in the case where a conventional semiconductor device manufacturing process is employed. 5A to 5D are cross-sectional views illustrating a part of a manufacturing process of a semiconductor device according to another conventional method. 6E to 6G are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to another conventional method. 7 (H) and 7 (I) are cross-sectional views showing a part of a semiconductor device manufacturing process according to another conventional method. 8A to 8D are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 9E to 9G are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIGS. 10H to 10J are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 11A to 11D are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. 12E to 12H are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

  8A to 8D and 9E to 9G are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. In this embodiment, first, as shown in FIG. 8A, a silicon oxide film 304 and a silicon nitride film 306 are formed on a silicon substrate 302.

  Next, as shown in FIG. 8B, trench patterns (concave portions) 312 and 308 are formed in both the fine pitch portion and the rough pitch portion by a photolithography process and an etching process, respectively.

  Next, the silicon substrate 302 is oxidized to form a silicon oxide film 314 on the surface of the silicon substrate 302 (inner surfaces of the trenches 312 and 308), as shown in FIG. 8C.

  Subsequently, as shown in FIG. 8D, an HDP-CVD film 316 is formed on the silicon oxide film 314. The deposition conditions for the HDP-CVD film 316 are, for example, SiH4: 60 sccm, O2: 120 sccm, Ar: 100 sccm, Source-RF output: 3000 W, Bias-RF output: 1500 W, and a D / S ratio of about 5. At this time, the void 318 is generated in the HDP-CVD film 316 in the fine pitch portion (memory cell portion), and the D / S ratio is set so that no void is generated in the HDP-CVD film 316 in the rough pitch portion of the peripheral circuit. Set.

  Next, as shown in FIG. 9E, a rough pitch portion of the peripheral circuit is covered with a resist 320 by a photolithography process. Subsequently, using the resist 320 as a mask, the HDP-CVD film 316 in the fine pitch portion of the cell portion is etched as shown in FIG. This etching process may be a chemical treatment with DHF or a treatment with a CF-based gas. The HDP-CVD film 316 is etched to the height (depth) at which the void 318 is generated by the etching process. At this time, the HDP-CVD film 316 may remain at the bottom of the trench, or the Si substrate 302 on the trench sidewall may be exposed.

  Thereafter, as shown in FIG. 9G, the resist 320 is removed, and the exposed surface 302 of the semiconductor substrate on the side wall of the trench is oxidized again to form a silicon oxide film 322. Next, as shown in FIG. 10H, an HDP-CVD film 324 is formed again on both the fine pitch portion and the rough pitch portion. The HDP-CVD film forming conditions are, for example, SiH4: 60 sccm, O2: 100 sccm, Ar: 100 sccm, Source-RF output: 3000 W, Bias-RF output: 4000 W, and a D / S ratio as small as 3 or less. .

  Usually, in the process of forming the HDP-CVD film 324, when the D / S ratio is set to be small, there is a possibility that the pattern is scraped by the sputter component at the time of HDP-CVD film formation. In particular, a portion having a wide STI width has a feature that the speed of the sputter component is higher than that of the film forming component due to the feature of HDP-CVD. However, the peripheral circuit portion having the easily cut pattern is not cut because it is covered with the first HDP-CVD film 316. Although the D / S ratio is set low, the inside of the cell has a feature that it is difficult to be scraped off by sputtering at a fine pitch, so that the Si substrate 302 can be buried without voids without being cut. Here, since the silicon nitride film 306 is removed in a subsequent process, there is no problem even if it is scraped.

  Subsequently, the surface of the HDP-CVD film 324 is planarized by CMP (Chemical Mechanical Polishing) as shown in FIG. Thereafter, as shown in FIG. 10J, the silicon nitride film 306 is removed by a known method. Through the above manufacturing process, an STI (element isolation region) filled with the silicon oxide film 324 is formed on the silicon substrate 302, and adjacent elements can be electrically isolated from each other.

  As described above, by using the first embodiment of the present invention, the fine pitch portion can be embedded without voids while preventing the Si substrate from being scraped during the HDP-CVD film formation. As a result, short circuit of the gate wiring due to voids, circuit malfunction due to scraping of the Si substrate, and the like are prevented, and the yield of semiconductor elements is improved.

  Further, as shown in FIGS. 5A to 5D, FIGS. 6E to 6G, and FIGS. 7H and 7I, trench processing is separately performed twice at the fine pitch portion and the rough pitch. Compared with the method of forming separately, the number of steps can be reduced, and an increase in manufacturing cost can be suppressed.

  11A to 11D and 12E to 12H are cross-sectional views illustrating a part of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. In this embodiment, first, as shown in FIG. 11A, a silicon oxide film 404 and a silicon nitride film 406 are formed on a silicon substrate 402.

  Next, as shown in FIG. 11B, trench patterns (concave portions) 412 and 408 are formed in both the fine pitch portion and the rough pitch portion by a photolithography process and an etching process, respectively.

  Next, the silicon substrate 402 is oxidized to form a silicon oxide film 414 on the surface of the silicon substrate 402 (inner surfaces of the trenches 412 and 408), as shown in FIG.

  Subsequently, as shown in FIG. 11D, an HDP-CVD film 416 is formed over the silicon oxide film 314. The HDP-CVD film forming conditions are, for example, SiH4: 70 sccm, O2: 120 sccm, Ar: 130 sccm, Source-RF output: 3000 W, Bias-RF output: 1000 W, and the D / S ratio is about 10. At this time, a void 418 is generated in the HDP-CVD film 416 in the fine pitch portion of the memory cell portion, and no void is generated in the HDP-CVD film 416 in the rough pitch portion of the peripheral circuit.

  Further, the distance “a” from the void 418 in the fine pitch portion to the surface of the HDP-CVD film 416 is smaller than the distance “b” from the surface of the HDP-CVD film 416 in the rough pitch portion to the semiconductor substrate 402. Set the S ratio.

  Next, the HDP-CVD film 416 is etched by DHF treatment as shown in FIG. At this time, the etching amount is set so that the surface of the Si substrate 402 is not exposed on the surface in the rough pitch portion, and the void 418 is exposed on the surface in the fine pitch portion and the surface of the Si substrate 402 is not exposed.

  After that, as shown in FIG. 12F, an HDP-CVD film 424 is formed again. The deposition conditions of the HDP-CVD film 424 are, for example, SiH4: 60 sccm, O2: 100 sccm, Ar: 100 sccm, Source-RF output: 3000 W, Bias-RF output: 4000 W, and the D / S ratio is as small as 3 or less. Condition. At this time, since the surface of the Si substrate 402 is not exposed, the Si substrate 402 is not cut, and the HDP-CVD film 424 is embedded without voids in the fine pitch portion.

  Subsequently, the surface of the HDP-CVD film 424 is planarized by CMP (Chemical Mechanical Polishing) as shown in FIG. Thereafter, as shown in FIG. 12H, the silicon nitride film 406 is removed by a known method. Through the above manufacturing process, an STI (element isolation region) filled with the silicon oxide film 424 is formed on the silicon substrate 402, and adjacent elements can be electrically isolated from each other.

  As described above, if the second embodiment of the present invention is used, the fine pitch portion can be embedded without voids while preventing the Si substrate from being scraped during HDP-CVD film formation, as in the first embodiment. As a result, short circuit of the gate wiring due to voids, circuit malfunction due to scraping of the Si substrate, and the like are prevented, and the yield of semiconductor elements is improved. Further, since the number of steps can be further reduced (three steps of photolithography, oxidation, and resist removal) as compared with the first embodiment, the manufacturing cost can be suppressed.

As mentioned above, although the Example of this invention was described, this invention is not limited to these Examples at all, It can change in the category of the technical idea shown by the claim.

302, 402: Semiconductor (Si) substrates 306, 406: Silicon nitride films 308, 408, 312, 412: Trench 316, 416: First insulating film (HDP-CVD film)
318, 418: voids 324, 424: second insulating film (HDP-CVD film)

Claims (5)

In a method of manufacturing a semiconductor device that performs element isolation by STI,
Forming a first trench in a first region on a semiconductor substrate and a second trench having a width wider than that of the first trench in a second region different from the first region ;
Forming a first insulating film covering the first region including the inside of the first trench, and covering the second region including the inside of the second trench; Forming without voids;
Leaving the first insulating film covering the second region, and removing the first insulating film covering the first region including the inside of the first trench ;
By forming a second insulating film, which is an HDP-CVD film, inside the first trench , the first trench is embedded without voids, and the first insulating film covering the second region is formed. And a step of forming the second insulating film . The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is an HDP-CVD film.   3. The semiconductor device manufacturing method according to claim 2, wherein a D / S ratio when forming the first insulating film is higher than a D / S ratio when forming the second insulating film. Method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of removing the first insulating film covering the first region, voids formed in the first insulating film are removed. Method. In the step of forming the first insulating film to cover the second region and the first region,
The distance “b” from the surface of the first insulating film to the surface of the semiconductor substrate of the second trench portion is greater than the distance “a” from the surface of the first insulating film to the hole of the first trench portion. Set the D / S ratio in the formation of the HDP-CVD film so as to be longer,
In the step of removing said first insulating film covering the first region, claims inner surface of the first trench portion is equal to or to leave the first insulating film so as not to be exposed to the surface A method for manufacturing a semiconductor device according to 2 , 3 or 4.

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