JP5544767B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5544767B2
JP5544767B2 JP2009144108A JP2009144108A JP5544767B2 JP 5544767 B2 JP5544767 B2 JP 5544767B2 JP 2009144108 A JP2009144108 A JP 2009144108A JP 2009144108 A JP2009144108 A JP 2009144108A JP 5544767 B2 JP5544767 B2 JP 5544767B2
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semiconductor device
metal plate
semiconductor
electrodes
resin material
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JP2011003636A (en
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卓矢 門口
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、半導体素子と該半導体素子から発せられた熱を放熱する熱交換体とをモールドして構成された半導体装置に関する。   The present invention relates to a semiconductor device configured by molding a semiconductor element and a heat exchanger that dissipates heat generated from the semiconductor element.

半導体装置において、例えばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）、ＳＩＴ（静電誘導トランジスタ）のような動作時に多量の発熱を伴う電力用半導体素子を実装する際には、半導体から発せられた熱を放熱する熱交換体が必要となる。そこで、近時では、電極（端子部）と半導体素子とを接続する金属導体（金属板）を半導体装置から露出させて放熱を行うものが知られている（特許文献１）。   In a semiconductor device, for example, when mounting a power semiconductor element that generates a large amount of heat during operation such as an IGBT (insulated gate bipolar transistor) or SIT (electrostatic induction transistor), the heat generated from the semiconductor is dissipated. A heat exchanger is required. Thus, recently, there has been known a technique in which a metal conductor (metal plate) that connects an electrode (terminal portion) and a semiconductor element is exposed from a semiconductor device to radiate heat (Patent Document 1).

特開２００４−２９６８３７号公報JP 2004-296837 A

ところが、半導体装置から金属導体を露出させて放熱する場合には、放熱を行う金属導体の露出面に電極を設けることができず、電極の配置箇所が制限されてしまう。そのため、電極間の沿面距離を確保するために半導体装置が大型化してしまうという問題があった。   However, when the metal conductor is exposed from the semiconductor device to dissipate heat, an electrode cannot be provided on the exposed surface of the metal conductor that dissipates heat, and the electrode placement location is limited. Therefore, there has been a problem that the semiconductor device is increased in size in order to ensure the creepage distance between the electrodes.

本発明は、こうした実情に鑑みてなされたものであり、その目的は、電極間の沿面距離を確保し、小型化が可能な半導体装置を提供することにある。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device that can ensure a creepage distance between electrodes and can be miniaturized.

以下、上記目的を達成するための手段及びその作用効果について記載する。
請求項１に記載の発明は、１つの半導体素子と、前記１つの半導体素子を上下方向にて挟む２つの金属導体であって、前記１つの半導体素子に接続される前記２つの金属導体と、前記上下方向にて前記２つの金属導体の間に位置する２つの電極であって、前記２つの金属導体のうち、各金属導体における他の金属導体と対向する面に１つずつ接続され、前
記上下方向にて一部が相互に重なり、かつ、前記上下方向と交差する左右方向にて相互に離れる前記２つの電極とを備え、これらを前記金属導体の各々の一部と、前記電極の各々の一部であって前記電極の各々が接続された前記金属導体の縁よりも外側に突出した部分とが各々露出し、かつ、前記２つの電極が相互に絶縁された状態で樹脂材によってモールドした半導体装置であって、前記各電極における前記樹脂材から露出するように突出した部分のうち前記樹脂材側となる基端側部分を絶縁体で被覆し、前記金属導体における前記樹脂材から露出する部分には、隣接する他の半導体装置と連結される連結部が設けられ、該連結部は、前記他の半導体装置の連結部と嵌合接続して連結され、該連結部が設けられた前記金属導体同士が電気的に接続されることを要旨とする。 In the following, means for achieving the above object and its effects are described.
According to one aspect of the present invention, and one semiconductor device, wherein a one of the two metal conductors sandwiching the semiconductor device in the vertical direction, and the two metal conductor connected to said one semiconductor element Two electrodes positioned between the two metal conductors in the vertical direction, one of the two metal conductors being connected to a surface of each metal conductor facing the other metal conductor, Previous
The two electrodes that partially overlap each other in the vertical direction and that are separated from each other in the horizontal direction intersecting the vertical direction are provided with a part of each of the metal conductors and the electrode and each of which protrudes outside the edge of the connected the metallic conductor portion of the electrode a portion of each is exposed each, and the resin material in a state where the two electrodes are insulated from each other The base material side part which becomes the resin material side among the parts which protruded so that it may be exposed from the resin material in each electrode is covered with an insulator, and the resin material in the metal conductor The connection portion connected to another adjacent semiconductor device is provided in a portion exposed from the connection portion, and the connection portion is connected by being connected to the connection portion of the other semiconductor device, and the connection portion is provided. The metal conductors are electrically connected And gist to be connected.

同構成では、半導体素子をモールドした樹脂材から一部が露出するように突出した複数の電極における樹脂材側となる基端側部分がそれぞれ絶縁体に被覆されているため、電極の配置間隔を狭くしても各電極間の沿面距離は絶縁体に沿って延長されることになる。したがって、電極間の沿面距離を確保し、小型化が可能な半導体装置を提供することができる。   In the same configuration, since the base end side portions on the resin material side of the plurality of electrodes protruding so as to be partially exposed from the resin material molded with the semiconductor element are each covered with an insulator, the arrangement interval of the electrodes is increased. Even if the width is narrowed, the creepage distance between the electrodes is extended along the insulator. Therefore, a creeping distance between the electrodes can be ensured, and a semiconductor device that can be miniaturized can be provided.

同構成では、半導体装置同士を連結する場合に、連結部同士を連結して金属導体同士を電気的に接続することにより、半導体素子の接続加工を簡略化することができる。   In the same configuration, when the semiconductor devices are connected to each other, the connection processing of the semiconductor elements can be simplified by connecting the connecting portions and electrically connecting the metal conductors.

本実施形態にかかる半導体装置の底面模式図。1 is a schematic bottom view of a semiconductor device according to an embodiment. 図１における２−２矢視断面模式図。FIG. 2 is a schematic cross-sectional view taken along arrow 2-2 in FIG. 1. 同実施形態における半導体装置の組み付け態様を示す断面模式図。The cross-sectional schematic diagram which shows the assembly | attachment aspect of the semiconductor device in the embodiment. 同実施形態における半導体装置の回路図。The circuit diagram of the semiconductor device in the embodiment. 半導体装置の比較底面模式図。FIG. 6 is a schematic diagram of a comparative bottom surface of a semiconductor device. 図５における６−６矢視断面模式図。FIG. 6 is a schematic cross-sectional view taken along arrow 6-6 in FIG. 5.

以下、本発明を具体化した半導体装置の一実施形態を図１〜図４にしたがって説明する。
図１及び図２に示すように、第１の半導体装置１１は、第１の半導体素子１２と、該第１の半導体素子１２に熱的及び電気的に接続された銅などの金属導体としての２枚の金属板１３，１４とが、エポキシ樹脂等の樹脂材によりモールドされて形成される第１の封止部１５により封止されている。 Hereinafter, an embodiment of a semiconductor device embodying the present invention will be described with reference to FIGS.
As shown in FIGS. 1 and 2, the first semiconductor device 11 includes a first semiconductor element 12 and a metal conductor such as copper that is thermally and electrically connected to the first semiconductor element 12. The two metal plates 13 and 14 are sealed by a first sealing portion 15 formed by molding with a resin material such as an epoxy resin.

第１の半導体素子１２の上側に配置された第１の上側金属板１３は、導体で形成された直方体状の第１のブロック体１６を介して第１の半導体素子１２に電気的に接続されている。すなわち、第１の半導体素子１２と第１のブロック体１６、及び第１のブロック体１６と第１の上側金属板１３は、はんだ１７によってそれぞれ接合されている。そして、第１の上側金属板１３の上面１３ａには、第１の半導体装置１１に他の半導体装置としての第２の半導体装置１８（図３参照）を連結する場合に、半導体装置１１、１８同士を電気的に接続する複数（本実施形態では２つ）の連結部としてのコネクタ１９（図３参照）のうち、一方のメスコネクタ２０が、はんだ１７によって接合されている。   The first upper metal plate 13 disposed on the upper side of the first semiconductor element 12 is electrically connected to the first semiconductor element 12 via a rectangular parallelepiped first block body 16 formed of a conductor. ing. That is, the first semiconductor element 12 and the first block body 16, and the first block body 16 and the first upper metal plate 13 are joined together by the solder 17. When the second semiconductor device 18 (see FIG. 3) as another semiconductor device is connected to the first semiconductor device 11 on the upper surface 13a of the first upper metal plate 13, the semiconductor devices 11 and 18 are connected. One of the female connectors 20 is joined by the solder 17 among a plurality of connectors 19 (see FIG. 3) as a connecting portion (two in the present embodiment) that are electrically connected to each other.

一方、図１及び図２に示すように、第１の半導体素子１２の下側に配置された第１の下側金属板１４は、熱伝導性に優れた導体であって、はんだ１７によって第１の半導体素子１２に接合されると共に、下面１４ｂが第１の封止部１５から露出するようにモールドされている。   On the other hand, as shown in FIGS. 1 and 2, the first lower metal plate 14 disposed below the first semiconductor element 12 is a conductor having excellent thermal conductivity, and is soldered by the solder 17. In addition to being bonded to one semiconductor element 12, the lower surface 14 b is molded so as to be exposed from the first sealing portion 15.

また、第１の封止部１５の左側面１５ａからは、第１の半導体素子１２と第１のワイヤ２１で接続された少なくとも１つ（本実施形態では５つ）の第１の信号端子２２が突出している。また、第１の封止部１５の右側面１５ｂからは、第１の上側金属板１３にはんだ１７で接合された電極としての第１の端子部２３と、第１の下側金属板１４にはんだ１７で接合された電極としての第２の端子部２４とが突出している。なお、信号端子２２及び各端子部２３，２４は図示しない外部配線と接続される。   Further, from the left side surface 15 a of the first sealing portion 15, at least one (five in this embodiment) first signal terminals 22 connected to the first semiconductor element 12 by the first wires 21. Is protruding. Further, from the right side surface 15 b of the first sealing portion 15, the first terminal portion 23 as an electrode joined to the first upper metal plate 13 with the solder 17 and the first lower metal plate 14 are connected. A second terminal portion 24 as an electrode joined by the solder 17 protrudes. The signal terminal 22 and the terminal portions 23 and 24 are connected to an external wiring (not shown).

第１の端子部２３及び第２の端子部２４において、第１の封止部１５から突出した部分は、封止部１５側となる基端側から先端にかけて塩化ビニル等の絶縁体２５に被覆されている。ただし、端子部２３，２４の先端側では、金属板１３，１４と電気的に接続された導体部分が絶縁体２５から部分的に露出している。   In the first terminal portion 23 and the second terminal portion 24, the portion protruding from the first sealing portion 15 is covered with an insulator 25 such as vinyl chloride from the base end side that is the sealing portion 15 side to the tip end. Has been. However, the conductor portion electrically connected to the metal plates 13 and 14 is partially exposed from the insulator 25 on the tip side of the terminal portions 23 and 24.

図３に示すように、本実施形態では、２つの半導体装置１１，１８が上下方向に積層されて連結されると共に、積層された半導体装置１１，１８は、上下両側から冷却機２７，２８で挟み込まれるようになっている。   As shown in FIG. 3, in this embodiment, the two semiconductor devices 11 and 18 are stacked and connected in the vertical direction, and the stacked semiconductor devices 11 and 18 are cooled by the coolers 27 and 28 from both the upper and lower sides. It is designed to be pinched.

ここで、第１の半導体装置１１の上方に積層される第２の半導体装置１８は、第１の半導体装置１１と同様に、第２の半導体素子３０が第２の上側金属板３１及び第２の下側金属板３２に挟まれてモールドされると共に、第２の信号端子３３が第２のワイヤ３４で第２の半導体素子３０に接続されている。すなわち、下側から第２の下側金属板３２、第２の半導体素子３０、第２のブロック体３５、第２の上側金属板３１の順に積層され、各々はんだ１７によって接合されている。   Here, in the second semiconductor device 18 stacked above the first semiconductor device 11, as in the first semiconductor device 11, the second semiconductor element 30 includes the second upper metal plate 31 and the second semiconductor device 31. The second signal terminal 33 is connected to the second semiconductor element 30 by the second wire 34 while being sandwiched between the lower metal plates 32 and molded. That is, the second lower metal plate 32, the second semiconductor element 30, the second block body 35, and the second upper metal plate 31 are stacked in this order from the lower side, and are joined by the solder 17.

そして、第２の半導体装置１８では、第２の上側金属板３１の上面３１ａが第２の封止部３６から露出するようにモールドされている。なお、第２の上側金属板３１には、第１の端子部２３と同様に絶縁体２５で被覆された第３の端子部３７が第２の封止部３６から突出するように接続されている。   In the second semiconductor device 18, the upper surface 31 a of the second upper metal plate 31 is molded so as to be exposed from the second sealing portion 36. The second upper metal plate 31 is connected to the third terminal portion 37 covered with the insulator 25 so as to protrude from the second sealing portion 36 in the same manner as the first terminal portion 23. Yes.

一方、第２の下側金属板３２には、その下面３２ｂに第１の半導体装置１１のメスコネクタ２０と連結可能な該メスコネクタ２０と同数（本実施形態では２つ）のオスコネクタ３８が、はんだ１７によって接合されている。したがって、オスコネクタ３８とメスコネクタ２０とを嵌合接続して第１の半導体装置１１と第２の半導体装置１８とを連結させることにより、コネクタ１９が接合された第１の上側金属板１３と第２の下側金属板３２とが電気的に接続される。すなわち、該金属板１３，３２に接続された半導体素子１２，３０同士も電気的に接続されるようになっている。   On the other hand, the second lower metal plate 32 has the same number (two in this embodiment) of male connectors 38 as the female connectors 20 that can be connected to the female connector 20 of the first semiconductor device 11 on the lower surface 32b. , And joined by solder 17. Therefore, the first upper metal plate 13 to which the connector 19 is joined is obtained by fitting and connecting the male connector 38 and the female connector 20 to connect the first semiconductor device 11 and the second semiconductor device 18. The second lower metal plate 32 is electrically connected. That is, the semiconductor elements 12 and 30 connected to the metal plates 13 and 32 are also electrically connected.

すなわち、図４に示すように、コネクタ１９で接続された半導体装置１１，１８は、例えば、点線で囲まれた第１の半導体装置１１のエミッタ端子と第２の半導体装置１８のコレクタ端子とが第１の端子部２３に接続された状態となる。   That is, as shown in FIG. 4, the semiconductor devices 11 and 18 connected by the connector 19 include, for example, an emitter terminal of the first semiconductor device 11 and a collector terminal of the second semiconductor device 18 surrounded by a dotted line. It will be in the state connected to the 1st terminal part 23. FIG.

また、図３に示すように、冷却機２７，２８は、絶縁シート３９，４０を介して半導体装置１１，１８を挟み込んでいるため、第１の下側金属板１４及び第２の上側金属板３１と冷却機２７，２８とは電気的に遮断されている。したがって、各端子部２３，２４，３７を介して入出力される電気信号は、冷却機２７，２８に伝達されないのに対し、半導体素子１２，３０から発せられた熱は、金属板１４，３１を介して冷却機２７，２８で熱交換されるようになっている。   Further, as shown in FIG. 3, since the coolers 27 and 28 sandwich the semiconductor devices 11 and 18 via the insulating sheets 39 and 40, the first lower metal plate 14 and the second upper metal plate. 31 and the coolers 27 and 28 are electrically disconnected. Therefore, the electric signals input / output via the terminal portions 23, 24, 37 are not transmitted to the coolers 27, 28, whereas the heat generated from the semiconductor elements 12, 30 is the metal plates 14, 31. Heat is exchanged by the coolers 27 and 28 via the.

（比較例）
図５及び図６には、上記実施形態に対する比較例として、端子部が絶縁体に被覆されていない半導体装置を示す。 (Comparative example)
5 and 6 show a semiconductor device in which a terminal portion is not covered with an insulator as a comparative example to the above embodiment.

図５，図６に示すように、第３の半導体装置４３は、上記第１の半導体装置１１と同様に、下から第３の下側金属板４４、第３の半導体素子４５、第３のブロック体４６、第３の上側金属板４７が順に積層されて各々はんだ１７によって接合され、第３の上側金属板４７の上面４７ａと第３の下側金属板４４の下面４４ｂとが露出するように第３の封止部４８によりモールドされている。   As shown in FIGS. 5 and 6, the third semiconductor device 43 includes a third lower metal plate 44, a third semiconductor element 45, a third semiconductor device from the bottom in the same manner as the first semiconductor device 11. The block body 46 and the third upper metal plate 47 are sequentially stacked and joined by the solder 17 so that the upper surface 47a of the third upper metal plate 47 and the lower surface 44b of the third lower metal plate 44 are exposed. The third sealing portion 48 is molded.

第３の半導体素子４５には、第３の信号端子４９が第３のワイヤ５０で接続されている。そして、第３の上側金属板４７と第３の下側金属板４４の右端部は、それぞれ曲げ加工が施されると共に、第３の封止部４８から突出して端子部５１，５２を形成している。   A third signal terminal 49 is connected to the third semiconductor element 45 by a third wire 50. The right end portions of the third upper metal plate 47 and the third lower metal plate 44 are respectively bent and project from the third sealing portion 48 to form terminal portions 51 and 52. ing.

ここで、第３の半導体装置４３の端子部５１，５２は、絶縁体で被覆されておらず、導体が露出した状態となっている。そのため、端子部５１，５２間の沿面距離Ａを確保するためには、半導体装置の幅Ｂを大きくする必要がある。また同様に、図５に示すように、第３の半導体装置４３から露出する第３の下側金属板４４と端子部５１との沿面距離Ｃを確保するために、第３の半導体装置４３の幅Ｄを大きくする必要がある。   Here, the terminal portions 51 and 52 of the third semiconductor device 43 are not covered with the insulator, and the conductor is exposed. Therefore, in order to ensure the creepage distance A between the terminal portions 51 and 52, it is necessary to increase the width B of the semiconductor device. Similarly, as shown in FIG. 5, in order to secure a creepage distance C between the third lower metal plate 44 exposed from the third semiconductor device 43 and the terminal portion 51, It is necessary to increase the width D.

これに対し、上記実施形態では、第１の半導体装置１１及び第２の半導体装置１８の各端子部２３，２４，３７を絶縁体２５で被覆したため、図１に示す端子部２３，２４間の沿面距離Ｅが、絶縁体２５に沿って延長される。   On the other hand, in the above-described embodiment, since the terminal portions 23, 24, and 37 of the first semiconductor device 11 and the second semiconductor device 18 are covered with the insulator 25, the space between the terminal portions 23 and 24 shown in FIG. A creepage distance E is extended along the insulator 25.

したがって、図５に示す幅Ｂに対して図１に示す幅Ｆを小さくしても、端子部２３，２４間の沿面距離Ｅを確保することができる。また、同様に図１に示す端子部２３と第１の下側金属板１４との沿面距離Ｇも端子部２３を被覆する絶縁体２５に沿って延長されるため、図５に示す幅Ｄに対して図１に示す幅Ｈを小さくしても端子部２３と第１の下側金属板１４との沿面距離を確保することができる。   Accordingly, even if the width F shown in FIG. 1 is made smaller than the width B shown in FIG. Similarly, the creepage distance G between the terminal portion 23 and the first lower metal plate 14 shown in FIG. 1 is also extended along the insulator 25 covering the terminal portion 23, so that the width D shown in FIG. On the other hand, even if the width H shown in FIG. 1 is reduced, the creepage distance between the terminal portion 23 and the first lower metal plate 14 can be secured.

以上説明したように、本実施形態によれば次のような効果を得ることができる。
（１）半導体素子１２をモールドした封止部１５から露出するように突出した各端子部２３，２４における封止部１５側となる基端側の部分がそれぞれ絶縁体２５に被覆されているため、端子部２３，２４の配置間隔を狭くしても各端子部２３，２４の沿面距離Ｅは絶縁体２５に沿って延長されることになる。したがって、端子部２３，２４間の沿面距離Ｅを確保し、小型化が可能な半導体装置１１を提供することができる。 As described above, according to the present embodiment, the following effects can be obtained.
(1) Since the base end side portions of the terminal portions 23 and 24 protruding so as to be exposed from the sealing portion 15 molded with the semiconductor element 12 are covered with the insulator 25. Even if the arrangement interval of the terminal portions 23 and 24 is narrowed, the creeping distance E of the terminal portions 23 and 24 is extended along the insulator 25. Therefore, the creeping distance E between the terminal portions 23 and 24 can be ensured, and the semiconductor device 11 that can be miniaturized can be provided.

（２）半導体装置１１，１８同士を連結する場合に、メスコネクタ２０にオスコネクタ３８を嵌合接続して第１の上側金属板１３と第２の下側金属板３２とを電気的に接続することによって溶接が不要となり、半導体素子１２，３０の接続加工を簡略化することができる。   (2) When connecting the semiconductor devices 11 and 18, the male connector 38 is fitted and connected to the female connector 20 to electrically connect the first upper metal plate 13 and the second lower metal plate 32. By doing so, welding becomes unnecessary, and the connection processing of the semiconductor elements 12 and 30 can be simplified.

（３）半導体装置１１，１８を積層して設けることにより、半導体装置１１，１８の搭載面積を縮小することができる。
なお、上記実施形態は以下のように変更してもよい。 (3) By providing the semiconductor devices 11 and 18 in a stacked manner, the mounting area of the semiconductor devices 11 and 18 can be reduced.
In addition, you may change the said embodiment as follows.

・参考例として、第１の半導体装置１１と第２の半導体装置１８とを連結するためにコネクタ１９を設けたが、コネクタ１９を設けず、上側金属板１３，３１と下側金属板１４，３２をそれぞれ封止部１５，３６から露出させてもよい。 As a reference example, the connector 19 is provided to connect the first semiconductor device 11 and the second semiconductor device 18, but the connector 19 is not provided, and the upper metal plates 13, 31 and the lower metal plate 14, 32 may be exposed from the sealing portions 15 and 36, respectively.

１１，１８…半導体装置、１２，３０…半導体素子、１３，１４…金属板（金属導体）、１９…コネクタ（連結部）、２３，２４…端子部（電極）、２５…絶縁体。   DESCRIPTION OF SYMBOLS 11, 18 ... Semiconductor device, 12, 30 ... Semiconductor element, 13, 14 ... Metal plate (metal conductor), 19 ... Connector (connection part), 23, 24 ... Terminal part (electrode), 25 ... Insulator.

Claims (1)

１つの半導体素子と、
前記１つの半導体素子を上下方向にて挟む２つの金属導体であって、前記１つの半導体素子に接続される前記２つの金属導体と、
前記上下方向にて前記２つの金属導体の間に位置する２つの電極であって、前記２つの金属導体のうち、各金属導体における他の金属導体と対向する面に１つずつ接続され、前記上下方向にて一部が相互に重なり、かつ、前記上下方向と交差する左右方向にて相互に離れる前記２つの電極と
を備え、
これらを前記金属導体の各々の一部と、前記電極の各々の一部であって前記電極の各々が接続された前記金属導体の縁よりも外側に突出した部分とが各々露出し、かつ、前記２つの電極が相互に絶縁される状態で樹脂材によってモールドした半導体装置であって、
前記各電極における前記樹脂材から露出するように突出した部分のうち前記樹脂材側となる基端側の部分を絶縁体で被覆し、
前記金属導体における前記樹脂材から露出する部分には、隣接する他の半導体装置と連結される連結部が設けられ、
該連結部は、前記他の半導体装置の連結部と嵌合接続して連結され、該連結部が設けられた前記金属導体同士が電気的に接続されることを特徴とする半導体装置。 One semiconductor element;
Wherein a one of the two metal conductors sandwiching the semiconductor device in the vertical direction, and the two metal conductor connected to said one semiconductor element,
Two electrodes located between the two metal conductors in the up-down direction, one of the two metal conductors connected to a surface of each metal conductor facing the other metal conductor, The two electrodes partially overlapping each other in the vertical direction and separated from each other in the horizontal direction intersecting the vertical direction ,
A portion of each of said metallic conductors, and exposure and each of which protrudes outside the edge of the connected the metallic conductor portion of the electrode a portion of each of said electrodes each and the two electrodes is a semiconductor device which is molded by resin material in a state of being insulated from each other,
Covering the portion on the base end side, which is the resin material side, of the protruding portion so as to be exposed from the resin material in each electrode,
The portion exposed from the resin material in the metal conductor is provided with a connecting portion that is connected to another adjacent semiconductor device,
The connecting portion is connected to a connecting portion of the other semiconductor device by fitting and connected, and the metal conductors provided with the connecting portion are electrically connected to each other.
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