JP5776588B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Patent Document 1 discloses a power semiconductor element. Specifically, the positive conductor and the first conductor are provided on the heat radiating portion so as to face each other, and the first semiconductor chip is bonded therebetween. A negative conductor and a second conductor are provided on the heat radiating portion so as to face each other, and a second semiconductor chip is bonded therebetween.

JP 2007-67220 A

Incidentally, an active element such as a transistor has a control terminal, and it is necessary to take out a signal line from the control terminal.
An object of the present invention is to provide a semiconductor device from which a signal line can be easily taken out.

In the first aspect of the present invention, the first electrode block, the common electrode block provided so as to face the first electrode block, the side surface of the first electrode block, and the side surface of the common electrode block A first semiconductor element that is disposed between the first electrode block and the common electrode block, a second electrode block that is provided to face the common electrode block, and the common In a semiconductor device comprising: a second semiconductor element disposed between a side surface of an electrode block and a side surface of the second electrode block, and joined to the common electrode block and the second electrode block; The first electrode block and the common electrode block are offset so that the electrode pad for the signal line of the first semiconductor element is positioned not to face the common electrode block. Location and, in the position of the first electrode blocks that no longer face the common electrode block by the arrangement, the only electrode pad is connected to said first semiconductor element, the first electrode block, wherein The common electrode block and the second electrode block are fixed to a heat dissipation member, and in each of the first electrode block, the common electrode block, and the second electrode block, the side surface is connected to the heat dissipation member. The gist is that the surface is erected from the fixed surface.

According to the first aspect of the present invention, the first electrode block and the common electrode block are offset from each other so that the signal line electrode pad of the first semiconductor element does not face the common electrode block. Therefore, the signal line can be easily taken out. Further, heat can be radiated by the heat radiating member through the first electrode block, the common electrode block, and the second electrode block.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the common electrode is arranged such that a signal line electrode pad of the second semiconductor element is not opposed to the second electrode block. The gist is that the block and the second electrode block are arranged offset.

  According to the second aspect of the present invention, the common electrode block and the second electrode block are offset so that the electrode pad for the signal line of the second semiconductor element is positioned not to face the second electrode block. Therefore, the signal lines can be easily taken out.

In the invention described in 請 Motomeko 3, in the semiconductor device according to claim 1 or 2, a wiring block for the first semiconductor element wiring material for the signal line of the first semiconductor element is molded with resin The wiring line material for signal lines of the wiring block for the first semiconductor element and the electrode pads for signal lines of the first semiconductor element are electrically connected.

According to the third aspect of the present invention, the signal line wiring material of the first semiconductor element wiring block and the signal line electrode pad of the first semiconductor element are electrically connected, and the signal can be easily obtained. The line can be pulled out.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the wiring material for the signal line of the second semiconductor element is molded with a resin. The wiring block for the signal line of the wiring block for the second semiconductor element and the electrode pad for the signal line of the second semiconductor element are electrically connected to each other. .

According to the fourth aspect of the present invention, the signal line wiring material of the second semiconductor element wiring block and the signal line electrode pad of the second semiconductor element are electrically connected, so that the signal can be easily transmitted. The line can be pulled out.

According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect , the signal line wiring of the first semiconductor element is on the offset direction side of the first electrode block with respect to the common electrode block. A wiring block for a first semiconductor element in which a material is molded with a resin, a wiring material for a signal line of the wiring block for the first semiconductor element, and an electrode pad for a signal line of the first semiconductor element A wiring material for the signal line of the second semiconductor element, which is electrically connected and located on the offset direction side of the common electrode block and opposite to the electrode pad for the signal line of the first semiconductor element. A wiring block for a second semiconductor element molded with resin, and a wiring material for a signal line of the wiring block for the second semiconductor element and an electrode pad for the signal line of the second semiconductor element are electrically connected. Are connected, the wiring block for the second semiconductor element, and summarized in that a recess which opens at a site against toward the electrode pad of the signal line of the first semiconductor element.

According to the fifth aspect of the present invention, the signal line can be easily drawn out from the electrode pad for the signal line of the first semiconductor element by the recess in the wiring block for the second semiconductor element.
In addition, the signal line wiring material of the first semiconductor element wiring block and the signal line electrode pad of the first semiconductor element are electrically connected, and the signal line can be easily drawn out. The signal line wiring material of the wiring block for the second semiconductor element and the electrode pad for the signal line of the second semiconductor element are electrically connected, and the signal line can be easily drawn out.

  According to the present invention, the signal line can be easily taken out.

(A) is a top view of the semiconductor device in the embodiment, (b) is a front view of the semiconductor device, and (c) is a right side view of the semiconductor device. The perspective view of a semiconductor device. The perspective view which shows the principal part in a semiconductor device. FIG. 7 is an electric circuit diagram of a semiconductor device.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
In the drawings, the horizontal plane is defined by the orthogonal X and Y directions, and the vertical direction is defined by the Z direction.

  A semiconductor device 10 shown in FIG. 1 constitutes upper and lower arms 100 and 101 in the inverter shown in FIG. The other upper and lower arms 102 and 103 and the upper and lower arms 104 and 105 are configured in the same manner as the semiconductor device 10 shown in FIG.

  In FIG. 4, the inverter includes upper and lower arms 100 and 101 for the U phase, upper and lower arms 102 and 103 for the V phase, and upper and lower arms 104 and 105 for the W phase. Each arm 100, 101, 102, 103, 104, 105 is configured by an IGBT and a diode connected in parallel. The IGBT has a gate terminal (gate electrode) as a control terminal.

  As shown in FIGS. 1 and 2, the semiconductor device 10 includes a heat dissipation plate 20 as a heat dissipation member, a first electrode block 30 made of copper, a common electrode block 40 made of copper, and a second electrode block 50 made of copper. A gate wiring block 60 and a gate wiring block 70 are provided. Further, the semiconductor device 10 includes a transistor chip 80 and a diode chip 81 that constitute the upper arm 100, and a transistor chip 90 and a diode chip 91 that constitute the lower arm 101.

  The first electrode block 30, the common electrode block 40, and the second electrode block 50 are made of a conductor, have a rectangular column shape with a rectangular cross section, and have four side surfaces. The three electrode blocks 30, 40, 50 have the same cross-sectional shape and cross-sectional dimensions.

  On the upper surface of the heat sink 20, one side surface (lower surface) of the first electrode block 30, one side surface (lower surface) of the common electrode block 40, and one side surface (lower surface) of the second electrode block 50 are interposed via an insulating layer. Is fixed. The first electrode block 30, the common electrode block 40, and the second electrode block 50 are arranged in parallel. That is, the first electrode block 30 having a square bar shape is disposed so as to extend in the X direction, and the common electrode block 40 having a square bar shape is disposed in the X direction at a position spaced from the first electrode block 30 in the Y direction. It is arrange | positioned so that it may extend. At a position spaced in the Y direction with respect to the common electrode block 40, a second electrode block 50 having a square bar shape is disposed so as to extend in the X direction.

  Further, the rising side (standing surface) 31 of the first electrode block 30 and the rising side (standing surface) 41 of the common electrode block 40 face each other, and the transistor chip 80 and the diode chip for the upper arm 100 are interposed therebetween. 81 is arranged.

  The collector of the transistor chip 80 for the upper arm 100 and the cathode of the diode chip 81 are joined to the vertical surface 31 of the first electrode block 30 by soldering or the like. Further, the emitter of the transistor chip 80 for the upper arm 100 and the anode of the diode chip 81 are joined to the vertical side surface 41 of the common electrode block 40 with a conductive adhesive or the like.

  The standing side (standing surface) 42 of the common electrode block 40 and the standing side (standing surface) 51 of the second electrode block 50 face each other, and the transistor chip 90 and the diode chip 91 for the lower arm 101 are disposed therebetween. Has been.

  The collector of the transistor chip 90 for the lower arm 101 and the cathode of the diode chip 91 are joined to the vertical side surface 42 of the common electrode block 40 by soldering or the like. The emitter of the transistor chip 90 for the lower arm 101 and the anode of the diode chip 91 are joined to the vertical side surface 51 of the second electrode block 50 with a conductive adhesive or the like.

  For the three electrode blocks 30, 40, 50 arranged side by side, the left end faces are flush (aligned) in the Y direction. The three electrode blocks 30, 40, and 50 have different lengths, the electrode block 50 being the shortest, the electrode block 40 being next long, and then the electrode block 30 being long.

  As shown in FIG. 3, the gate pad (gate electrode) 85 in the transistor chip 80 for the upper arm 100 is provided at a position protruding from the right end surface of the common electrode block 40. That is, the part where the signal line exits is offset and is shifted so that the common electrode block 40 does not cover the signal line part. In this way, the first electrode block 30 and the common electrode block 40 are offset from each other so that the gate pad 85 as the signal line electrode pad of the transistor chip 80 is positioned not to face the common electrode block 40. Has been.

  A gate wiring block 60 is disposed on the right end surface of the first electrode block 30. The gate wiring block 60 is configured by sealing a gate wiring material 61 with a resin 62, and forms a rectangular parallelepiped. As described above, the gate wiring block 60 is provided as a wiring block for the first semiconductor element in which the wiring material 61 for the signal line of the first semiconductor element is molded with the resin 62.

  The gate wiring block 60 is fixed to the heat sink 20. The pad 61a at one end of the gate wiring member 61 is exposed on one side surface of the resin rectangular parallelepiped. The other end side of the gate wiring member 61 projects from the top surface of the resin rectangular parallelepiped into three branches and extends upward. The signal line drawing gate pad 61a is located close to the gate pad (element-side gate pad) 85 of the transistor chip 80.

  The gate pad 85 in the transistor chip 80 for the upper arm 100 and the pad 61a of the gate wiring material 61 of the gate wiring block 60 are bonded by a wire W1. The gate of the transistor chip 80 is connected to the gate wiring material 61 of the gate wiring block 60 via the wire W 1, and extends upward by the gate wiring material 61. Thus, the wiring material 61 of the gate wiring block 60 and the gate pad 85 are electrically connected.

  As shown in FIG. 3, the gate pad (gate electrode) 95 in the transistor chip 90 for the lower arm 101 is provided at a position protruding from the right end surface of the second electrode block 50. That is, the portion where the signal line exits is offset and is displaced so that the second electrode block 50 does not cover the signal line portion. In this way, the common electrode block 40 and the second electrode block 50 are arranged so that the gate pad 95 as the electrode pad for the signal line of the second semiconductor element is in a position not facing the second electrode block 50. It is arranged with an offset.

  As shown in FIG. 2, a gate wiring block 70 is disposed on the right end surface of the common electrode block 40. The gate wiring block 70 is configured by sealing a gate wiring material 71 with a resin 72, and forms a rectangular parallelepiped. Thus, the gate wiring block 70 is provided as a wiring block for the second semiconductor element in which the wiring material 71 for the signal line of the second semiconductor element is molded with the resin 72.

  The gate wiring block 70 is fixed to the heat sink 20. The pad 71a at one end of the gate wiring material 71 is exposed on one side surface of the resin rectangular parallelepiped. The other end side of the gate wiring member 71 projects from the top surface of the resin rectangular parallelepiped into three branches and extends upward. The signal line drawing gate pad 71 a is located close to the gate pad (element side gate pad) 95 of the transistor chip 90.

  Further, a recess 75 (see FIG. 1) is formed on the surface of the gate wiring block 70 facing the blocks 30 and 60, and the wire W1 is disposed inside the recess 75. Therefore, the concave portion 75 prevents the wire W1 from contacting the gate wiring block 70. That is, the gate wiring block 70 has a recess 75 that opens at a portion corresponding to the gate pad 85.

  The gate pad 95 in the transistor chip 90 for the lower arm 101 and the pad 71a of the gate wiring material 71 of the gate wiring block 70 are bonded by a wire W2. The gate of the transistor chip 90 is connected to the gate wiring material 71 of the gate wiring block 70 via the wire W2, and extends upward by the gate wiring material 71. Thus, the wiring material 71 of the gate wiring block 70 and the gate pad 95 are electrically connected.

  One side of the external connection terminal 35 made of an L-shaped strip is joined to the left side portion of the upper surface of the electrode block 30, and the other side extends upward. Similarly, one side of the external connection terminal 45 made of an L-shaped strip is joined to the left part of the upper surface of the electrode block 40, and the other side extends upward. One side of the external connection terminal 55 made of an L-shaped strip is joined to the left portion of the upper surface of the electrode block 50, and the other side extends upward.

Next, the operation of the semiconductor device 10 configured as described above will be described.
Three electrode blocks 30, 40, 50 are arranged side by side on the heat sink 20. Elements (transistor chip 80, diode chip 81) constituting the upper arm 100 are joined between the first electrode block 30 and the common electrode block 40, and the common electrode block 40 and the second electrode block 50 are connected to each other. Elements (transistor chip 90 and diode chip 91) constituting the lower arm 101 are joined between them. Further, the first electrode block 30, the common electrode block 40, and the second electrode block 50 are shifted from each other at the right end, and gate pads 85 and 95 are disposed at these portions, and the gate wiring block 60 is formed by wires W1 and W2. , 70 are connected to gate wiring members 61, 71.

  As the transistor chip 80 is driven, the transistor chip 80 and the diode chip 81 generate heat. The heat is transferred to the electrode blocks 30 and 40. Further, the heat is transmitted from the lower surfaces of the electrode blocks 30 and 40 to the heat sink 20. And it escapes from the heat sink 20.

  Similarly, the transistor chip 90 and the diode chip 91 generate heat as the transistor chip 90 is driven. The heat is transmitted to the electrode blocks 40 and 50. Further, the heat is transmitted from the lower surfaces of the electrode blocks 40 and 50 to the heat sink 20. And it escapes from the heat sink 20.

  In this way, the common electrode block 40 sandwiched between the chips 80 and 81 and the chips 90 and 91 as the two upper and lower elements has a thickness and radiates heat on a surface (lower surface) different from the surface where the elements are joined. be able to.

  In addition, when using switching elements which are IGBTs constituting the upper and lower arms, the electrode blocks 30, 40, 50 are arranged offset so that the gate pads 85, 95 are not covered with the electrode blocks 40, 50. Yes. Thereby, a signal line (gate signal line) can be taken out.

According to the above embodiment, the following effects can be obtained.
(1) As the configuration of the semiconductor device 10, the first electrode block 30, the common electrode block 40, the transistor chip 80 and the diode chip 81 as the first semiconductor element, the second electrode block 50, and the second The transistor chip 90 and the diode chip 91 are provided as semiconductor elements. The common electrode block 40 is provided to face the first electrode block 30, and the transistor chip 80 and the diode chip 81 are disposed between the first electrode block 30 and the common electrode block 40, so that the first electrode The block 30 and the common electrode block 40 are joined. The second electrode block 50 is provided so as to face the common electrode block 40, and the transistor chip 90 and the diode chip 91 are disposed between the common electrode block 40 and the second electrode block 50. Are joined to the second electrode block 50. In addition, the first electrode block 30 and the common electrode block 40 are offset from each other so that the gate pad 85 as the signal line electrode pad of the transistor chip 80 does not face the common electrode block 40. .

  Therefore, since the first electrode block 30 and the common electrode block 40 are offset so that the gate pad 85 of the transistor chip 80 does not face the common electrode block 40, the signal line can be easily taken out. be able to.

  (2) The common electrode block 40 and the second electrode block 50 are offset so that the gate pad 95 as the electrode pad for the signal line of the second semiconductor element is positioned not to face the second electrode block 50. Therefore, the signal line can be easily taken out.

  (3) Since the 1st electrode block 30, the common electrode block 40, and the 2nd electrode block 50 are being fixed to the heat sink 20 as a heat radiating member, it is excellent in heat dissipation. Specifically, heat dissipation is excellent by radiating heat on a surface different from the surface where the elements in the electrode blocks 30, 40, 50 are joined.

  (4) A gate wiring block 60 as a wiring block for a first semiconductor element obtained by molding a wiring material 61 for a signal line of the first semiconductor element with a resin 62, and the wiring material 61 and the gate of the gate wiring block 60 are provided. Since the pad 85 is electrically connected, the signal line can be easily pulled out.

  (5) A gate wiring block 70 as a wiring block for a second semiconductor element obtained by molding a wiring material 71 for a signal line of the second semiconductor element with a resin 72, and the wiring material 71 and the gate of the gate wiring block 70 are provided. Since the pad 95 is electrically connected, the signal line can be easily pulled out.

  (6) Since the gate wiring block 70 has the recess 75 opened at the portion corresponding to the gate pad 85, the signal line can be easily drawn from the transistor chip 80 by the recess 75. That is, it is possible to avoid the gate wiring block 70 from interfering with the drawing of the signal line.

The embodiment is not limited to the above, and may be embodied as follows, for example.
-Although the semiconductor element was IGBT, it is not restricted to this, For example, power MOSFET etc. may be sufficient.

-Instead of the heat sink 20, you may use a cooler (for example, a water cooling type cooler) as a heat radiating member.
-Although embodied in an inverter, other electronic devices may be used.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 20 ... Heat sink, 30 ... 1st electrode block, 40 ... Common electrode block, 50 ... 2nd electrode block, 60 ... Gate wiring block, 70 ... Gate wiring block, 80 ... Transistor chip, 81 ... Diode chip, 85 ... Gate pad, 90 ... Transistor chip, 91 ... Diode chip, 95 ... Gate pad.

Claims (5)

A first electrode block;
A common electrode block provided to face the first electrode block;
A first semiconductor element disposed between a side surface of the first electrode block and a side surface of the common electrode block, and joined to the first electrode block and the common electrode block;
A second electrode block provided to face the common electrode block;
A second semiconductor element disposed between a side surface of the common electrode block and a side surface of the second electrode block, and joined to the common electrode block and the second electrode block;
In a semiconductor device comprising:
The first electrode block and the common electrode block are arranged so as to be offset so that an electrode pad for a signal line of the first semiconductor element does not face the common electrode block, and the common electrode block is arranged by the arrangement. At the position of the first electrode block that is no longer opposed to the electrode block, only the electrode pad is connected to the first semiconductor element,
The first electrode block, the common electrode block, and the second electrode block are fixed to a heat dissipation member,
In each of the first electrode block, the common electrode block, and the second electrode block, the side surface is a surface erected from a fixed surface to the heat dissipation member.   The common electrode block and the second electrode block are offset and arranged so that an electrode pad for a signal line of the second semiconductor element does not face the second electrode block. The semiconductor device according to claim 1. A wiring block for a first semiconductor element in which a wiring material for a signal line of the first semiconductor element is molded with a resin, the wiring material for a signal line of the wiring block for the first semiconductor element, and the first the semiconductor device according to claim 1 or 2 electrode pads for the signal lines of the first semiconductor device is characterized in that it is electrically connected. A wiring block for a second semiconductor element in which a wiring material for a signal line of the second semiconductor element is molded with a resin, the wiring material for a signal line of the wiring block for the second semiconductor element, and the first the semiconductor device according to any one of claims 1 to 3, the electrode pad for signal lines of the second semiconductor element is characterized by being electrically connected. A first semiconductor element wiring block in which a signal line wiring material of the first semiconductor element is molded with a resin on an offset direction side of the first electrode block with respect to the common electrode block; A wiring member for a signal line of the wiring block for the semiconductor element and an electrode pad for the signal line of the first semiconductor element are electrically connected;
A wiring material for a signal line of the second semiconductor element is molded with a resin at a position opposite to the electrode pad for the signal line of the first semiconductor element on the offset direction side of the common electrode block. A wiring block for signal lines of the second semiconductor element and a signal line electrode pad of the second semiconductor element are electrically connected to each other. ,
The second wiring blocks for a semiconductor device, a semiconductor according to claim 1 or 2, characterized in that a recess which opens at a site against toward the electrode pad of the signal line of the first semiconductor element apparatus.