JP5509506B1 - Game machine - Google Patents

Abstract

Control data transmitted from a main control board to a sub control board is prevented from being altered by an unauthorized electronic component in contact with a wire harness.
A detection circuit for detecting that a current flowing from a data signal line to a data signal output terminal exceeds a predetermined amount is provided on a substrate on a control data transmission side, and the detection circuit detects the current. When it is detected that the amount exceeds the predetermined value, a signal is output from the detection circuit to the control data transmission circuit, and the control data transmission circuit is put into a sleep state where normal control data cannot be output, and the current falls below a predetermined amount. After that, the detection circuit continues to output a signal for setting the control data transmission circuit in the dormant state for a predetermined pause delay period, and at least once in the pause delay period, the control data is transmitted from the main control board. Send part or all.
[Selection] Figure 13

Description

  The present invention relates to a technique for preventing illegal acts of gaming machines.

  A gaming machine such as a slot machine or a pachinko machine may be composed of a plurality of control boards in order to distribute the control burden. In these gaming machines, the control boards are connected to each other by a signal line, and a command is transmitted from one control board to the other control board, so that the processes executed by each control board are interlocked and executed by each control board. It realizes that the processing becomes the operation of an integrated gaming machine.

  For example, the gaming machine described in Patent Document 1 has a game content that gives a predetermined profit to a player when a predetermined role continuously wins in a game. In such a gaming machine, The winning itself is controlled by the main control board, and the profit granting by the continuous winning of the predetermined role is controlled by the sub-control board. Specifically, every time a winning occurs, the main control board transmits a command notifying the occurrence of winning and the type of winning to the sub control board. The sub-control board counts the number of consecutive winnings in a predetermined combination based on a command transmitted from the main control board, and counts when receiving a command indicating that the predetermined combination has not been won. When the counted number of winnings reaches a predetermined value, the player is given a predetermined profit.

  For such a gaming machine or the like, an illegal act of changing a command related to winning sent from the main control board to be advantageous to the player is prevalent (see Patent Document 2). As a typical technique, an illegal act of attaching an illegal electronic component to a wire harness in which signal lines between a main control board and a sub control board are bundled is known. In such a fraudulent act, by operating a fraudulent electronic component at a required timing, the legitimate command transferred via the signal line is altered, or the fraudulent command is output to the signal line. Realize an advantageous state.

  In response to the above fraudulent acts, measures are taken to check whether illegal electronic parts are mounted inside the gaming machine by opening the front door of the gaming machine using a period in which gaming is not performed. Yes. However, in recent years, since the trick of fraud has become sophisticated, it is also assumed that the fraudulent electronic component is brought into contact with the wire harness only when the fraud is carried out and the fraudulent person takes away the fraudulent electronic component after the fraud. The When a fraudulent act is performed with such a technique, it is impossible to determine whether the fraudulent act has been performed because no fraudulent electronic components are mounted at the time of inspection.

  FIG. 16A shows an outline of a conventional control circuit related to command transfer. A command output from the main microcomputer 30 of the main control board 14 is output from the output terminal constituted by the transistor TR 0 to the data signal line 160 and received by the sub microcomputer 31 of the sub control board 15. Here, the output terminal switches the output voltage to the data signal line 160 between the L level and the H level according to the operating state of the transistor TR0. In contrast to this configuration, when the illegal electronic component 60 is brought into contact with the wire harness, as shown in FIG. 16B, a large amount of current (hereinafter referred to as illegal current) from the illegal electronic component 60 to the data signal line 160 is obtained. .)), The voltage of the data signal line 160 is set to the H level regardless of the operation state of the transistor TR0. Further, when the illegal electronic component 60 short-circuits the data signal line 160, the voltage of the data signal line 160 is set to the L level.

JP 2012-81176 A JP 2006-6852 A

  As shown in FIG. 16B, when an illegal current is supplied to the data signal line 160 to modify or insert a command, the illegal current that has flowed into the data signal line 160 flows into the output terminal of the main control board 14. Therefore, an incorrect current can be detected by measuring the value of the current flowing into the output terminal. However, in order to execute a process related to error notification or the like on the main control board 14 when an incorrect current is detected, the detection information on the incorrect current is fed back to the main microcomputer 30 that controls the main control board 14. I have to do it. As described above, it is not preferable to feed back information to the microcomputer 30 that is a command transmission source, because it becomes a hotbed for another illegal act. On the other hand, it is also proposed that when an improper current is detected, an error signal or the like is transmitted to the sub control board 15 and processing related to error notification or the like is executed by the sub control board 15. When the illegal electronic component 60 is in contact with the control board 15, it is not easy to reliably transmit an error signal from the main control board 14 to the sub control board 15.

  The present invention has been made in view of the present situation, and an object of the present invention is to provide a gaming machine that can surely prevent such an illegal act.

The present invention includes a first control board for transmitting control data, and have your a game machine and a second control board for performing control based on the control data received from the first control board, the first control board One or a plurality of data signal lines for transferring the control data output from the first control board , wherein the first control board includes a control data transmission circuit having a data signal output terminal for outputting control data to the data signal lines. The control data transmission circuit is controlled to a halt state in which normal control data cannot be output from the data signal output terminal according to a signal input from the outside, and the first control board Includes a detection circuit that detects that a current flowing from the data signal line to the data signal output terminal has reached a predetermined amount or more, and the detection circuit receives the data signal from the data signal line. When it is detected that the current flowing into the power terminal exceeds a predetermined amount, a signal for setting the control data transmission circuit to the sleep state is output to the control data transmission circuit, and the data signal is output from the data signal line. Even after the current flowing into the output terminal falls below the predetermined amount, the signal for setting the control data transmission circuit to the inactive state continues to be output for a predetermined inactive delay period. Transmits part or all of the control data to the second control board at least once in a predetermined period shorter than the pause delay period, and the second control board transmits the control data during the pause delay period. A gaming machine comprising communication error detection means for detecting an abnormal reception state of the generated control data as a communication error.
According to another aspect of the present invention, there is provided a first control board that transmits control data, a second control board that performs control based on the control data received from the first control board, and the first control board. In a gaming machine comprising a relay board for relaying control data between the second control boards, the game board comprises one or more data signal lines for transferring the control data output from the relay board, A control data transmission circuit having a data signal output terminal for outputting control data to the data signal line, and the control data transmission circuit performs normal control from the data signal output terminal in accordance with a signal input from the outside. Further, the relay board is controlled so that data cannot be output, and the relay board has a current flowing from the data signal line to the data signal output terminal exceeding a predetermined amount. And when the current flowing from the data signal line to the data signal output terminal exceeds a predetermined amount, the detection circuit sets the control data transmission circuit to the inactive state. A signal for output to the control data transmission circuit, and after the current flowing from the data signal line to the data signal output terminal falls below the predetermined amount, the control data transmission circuit is passed over a predetermined pause delay period. The first control board continuously outputs a signal for making the hibernation state at least once in a predetermined period shorter than the hibernation delay period. A communication error that is transmitted to the board, and the second control board detects an abnormal reception state of the control data that occurs during the pause delay period as a communication error. A game machine characterized by comprising a knowledge unit.

  In such a configuration, when an unauthorized current is caused to flow through the data signal line due to the above-described unauthorized act, the detection circuit detects the unauthorized current flowing into the data signal output terminal, and puts the control data transmission circuit in a dormant state. This dormant state continues for the dormant delay period even after the inflow of incorrect current has stopped. Even if a fraudulent electronic component is in contact with the wire harness, after fraud has stopped, the output of the data signal output terminal is transferred to the second control board as usual, so after fraud has stopped During the pause delay period, the output of the paused data signal output terminal is transferred to the second control board without being affected by the illegal electronic component. In this configuration, the first control board is configured to transmit part or all of the control data to the second control board at an interval shorter than the pause delay period. When the signal output terminal is in a dormant state, the second control board does not receive control data that should normally be received or receives abnormal control data that is not normal. Will occur. As described above, in the present invention, if an improper current flows into the data signal line, an abnormal reception state of the control data occurs in the second control board. As a result, it is possible to execute an appropriate process related to error notification or the like on the second control board when an improper current flows.

In the present invention, the control data transmission circuit controls the output voltage of the data signal output terminal to either the H level or the L level, and in the idle state, the output voltage of the data signal output terminal is all The abnormal reception state that is controlled to H level or all L level , and detected as the communication error by the communication error detecting means, is that the control data transmitting circuit is connected to the data signal output terminal over the pause delay period. A configuration is proposed which is a reception state when all the output voltages are controlled to all H levels or all L levels .

  That is, in such a configuration, in the operating state of the control data transmission circuit, the data signal output terminal is switched between the H level and the L level according to the control data to be output. Regardless of whether the data signal output terminal is controlled to the H level or the L level, normal control data is not output from the data signal output terminal. With this configuration, the control data transmission circuit can be easily realized using an existing circuit configuration.

A specific configuration of the present invention is configured such that abnormal control data is received by the second control board when the control data transmission circuit is in a pause state during the pause delay period. The communication error detection means is to determine at any time whether or not the control data received by the second control board is normal, the abnormal reception state detected by the communication error detection means as the communication error, A configuration is proposed in which the control data received by the second control board is abnormal .

  As in this communication error detection means, since it is also performed in the existing control board to determine whether or not the received control data is normal, in this configuration, a specially new configuration is added to the second control board. There is an advantage that the communication error detecting means can be easily realized without providing the.

As another configuration of the present invention, during the pause delay period, the control data transmission circuit is in a pause state so that the second control board cannot receive part or all of the control data. The communication error detecting means measures a reception interval at which the second control board receives a part or all of the control data , and the communication error detecting means detects the communication error. A configuration is proposed in which the abnormal reception state is a state in which the reception interval is longer than the predetermined period .

  In such a configuration, part or all of the control data to be received by the second control board is lost during the pause delay period. Here, just determining whether the control data received by the second control board is normal or not cannot be detected as a communication error when the entire control data is lost. With this communication error detection means, even if the entire control data is lost, it can be reliably detected as a communication error.

  As described above, in the present invention, when an illegal current flows into the data signal line between the first control board and the second control board, a communication error is detected by the second control board on the control data receiving side. Therefore, when a communication error is detected, by causing the second control board to execute a process related to error notification or the like, it is possible to reliably prevent an illegal act of sending an illegal current to the data signal line to alter or insert a command. It becomes possible. In particular, in the present invention, information relating to detection of unauthorized current is not fed back to the microcomputer that is the transmission source of control data, so that the configuration of the present invention is not likely to be used for other unauthorized activities.

FIG. 3 is a perspective view of the slot machine 1 according to the first embodiment. 2 is a perspective view showing an outline of the slot machine 1 with a front door 3 opened. FIG. 3 is a block diagram showing a control circuit of the slot machine 1. FIG. It is a chart explaining the contents of a command. 3 is a block diagram showing signal lines between a main control board 14 and a sub control board 15. FIG. 3 is a block diagram showing a control circuit related to communication between a main control board 14 and a sub control board 15. FIG. 3 is a conceptual diagram of a main part of a main control board 14. FIG. It is a timing chart which shows operation | movement of a detection circuit. FIG. 3 is a conceptual diagram of a main part of a sub communication relay board 17 and a sub control board 15. It is a flowchart which shows the control content of a main control process. It is a flowchart which shows the control content of a command transmission process. (A) is a flowchart which shows the control content of a sub control process, (B) is a flowchart which shows the control content of a communication error process. It is a timing chart which shows the communication mode of the command accompanying illegal current generation | occurrence | production. FIG. 6 is a block diagram illustrating a control circuit related to communication between a main control board 14 and a sub control board 15 according to a second embodiment. In Example 2, it is a timing chart which shows the communication mode of the command accompanying illegal current generation | occurrence | production. It is the schematic which shows the control circuit which concerns on command transfer in a conventional structure, (A) shows a normal state, (B) shows the state by which the unauthorized electronic component was contacted.

Embodiments of the present invention are described according to the following examples.
In the following first and second embodiments, the first control board according to the present invention corresponds to the main control board 14, and the second control board according to the present invention corresponds to the sub control board 15. The control data according to the present invention corresponds to a command transmitted from the main control board 14 to the sub control board 15.

  In this embodiment, the present invention is applied to a slot machine. As shown in FIGS. 1 and 2, the housing 2 of the slot machine 1 is opened forward and is covered by the front door 3 from the front. As shown in FIG. 1, a visual recognition window 4 for visually recognizing three reels 9 arranged inside the housing 2 is provided at the center of the front door 3. A horizontally long rectangular liquid crystal display 10 is disposed above the viewing window 4. Further, on the front side of the front door 3, various switches such as bet switches 5 a and 5 b, a start switch 6, a stop switch 7, and a checkout switch 8 used for game operation are disposed below the viewing window 4. The front door 3 is provided with a plurality of speakers 11 and effect lamps 12 at appropriate positions.

  In addition, as shown in FIG. 2, the main control board 14 and the sub control board 15 are installed inside the housing 2 in a state where the main control board 14 and the sub control board 15 are housed in the case. The main control board 14 and the sub control board 15 constitute a control device of the slot machine 1. From the main control board 14 to the sub control board 15, commands (control data) are transmitted in one direction via the wire harnesses 16 a and 16 b in which signal lines are bundled and the sub communication relay board 17. Inside the housing 2, a power box 19 including a power-on switch 18 and a hopper unit 20 are disposed below the reel 9. A front door opening detection sensor 22 that detects opening of the front door 3 is provided on the right side of the housing 2. The front door opening detection sensor 22 is disposed so as to face the reflecting plate 23 provided on the front door 3 and optically detects the opening of the front door 3.

Next, a control circuit for controlling the operation of the slot machine 1 will be described with reference to FIG.
The main control board 14 controls the progress of the game, and includes a main microcomputer 30, a random number generation circuit, a latch circuit, a command transmission circuit 32, and a detection circuit 33. The main microcomputer 30 includes a CPU, a RAM, a ROM, an I / O port, and the like, and includes the above-described start switch 6, stop switch 7, bet switches 5a and 5b, settlement switch 8, and front door opening detection sensor 22. Is input to the I / O port of the main microcomputer 30. Signals are output from the main microcomputer 30 to the motor that drives the reel 9 and the motor that drives the hopper unit 20 via the I / O port. The main microcomputer 30 transmits various commands to the sub control board 15 via the command transmission circuit 32. The command transmitted from the main control board 14 to the sub control board 15 is sent only in one direction, and no command is sent from the sub control board 15 to the main control board 14. The main microcomputer 30 generates an interrupt to the CPU at intervals of 1.8 milliseconds. A command transmission process, which will be described later, is executed every time this interrupt occurs. The RAM of the main microcomputer 30 has a storage area as a transmission buffer for temporarily storing commands to be transmitted. The CPU of the main microcomputer 30 generates a command and stores the generated command in the transmission buffer. Note that the transmission buffer can store a plurality of commands. The main microcomputer 30 outputs commands in the order stored in the transmission buffer. The main control board 14 is provided with a detection circuit 33 according to the present invention. The detection circuit 33 is for detecting an improper current flowing into the data signal output terminal of the command transmission circuit 32, and details will be described later.

  The sub communication relay board 17 relays a command data signal between the main control board 14 and the sub control board 15. The sub-communication relay board 17 is connected to the command transmission circuit 32 of the main control board 14 via the wire harness 16a, and the parallel-serial conversion circuit converts the command data signal output by the main control board 14 in the parallel communication system. In 35, the data is converted into a serial communication system and output to the sub-control board 15. The sub control board 15 is also provided with a detection circuit 36 according to the present invention. The detection circuit 36 is for detecting an improper current flowing into the data signal output terminal of the parallel-serial conversion circuit 35, and will be described in detail later.

  The sub-control board 15 controls the effects relating to the game in accordance with commands received from the main control board 14, and includes a sub-microcomputer 31, a random number generation circuit, a latch circuit, a sound control circuit, an image A control circuit and an LED drive circuit are provided. The sub microcomputer 31 includes a CPU, a RAM, a ROM, an I / O port, a command receiving circuit 37, and the like. The ROM of the sub microcomputer 31 stores fixed data relating to a wide variety of effect patterns. The RAM of the sub microcomputer 31 is provided with a buffer area for receiving a command transmitted from the main control board 14. The sub control board 15 and the sub communication relay board 17 are interconnected by a wire harness 16b, and the command output from the main control board 14 is a command of the sub control board 15 via the sub communication relay board 17 in a serial communication system. Input to the receiving circuit 37. The command input to the command receiving circuit 37 is stored in the buffer area of the RAM, and the CPU of the sub microcomputer 31 executes processing corresponding to the received command. Specifically, the audio control circuit outputs a sound from the speaker by outputting a signal from the I / O port to the audio control circuit, and the image control by outputting a signal from the I / O port to the image control circuit. The circuit outputs an image to the liquid crystal display and outputs a signal from the I / O port to the LED driving circuit, so that the LED driving circuit turns on the effect lamp.

  FIG. 4A shows a data format of a command transmitted from the main control board 14 to the sub control board 15. This command corresponds to control data according to the present invention. As shown in FIG. 4A, the command is 5-byte data in which 5 pieces of 1-byte configuration data form one set. That is, the command is meaningful by a plurality of configuration data. The configuration data constituting the command includes a communication unit for normally performing communication and a data unit for storing information of the main control board 14. Specifically, as shown in FIG. 4B, the configuration data “ST” at the head of the command constitutes a communication unit, and a fixed value indicating the head of the command is stored. The second and third configuration data “DATA1” and “DATA2” constitute a data part, and store values corresponding to the type and contents of the command. The fourth component data “CH” stores a checksum that is an error correction code. Specifically, the configuration data “CH” stores the lower 1 byte when “DATA1” and “DATA2” are added. The fifth configuration data “EN” configures the communication unit, and stores a fixed value indicating the end of the command.

  FIG. 4C shows a specific example of the data portion of the command (“DATA1” and “DATA2”). In the figure, “h” means a hexadecimal number. In this embodiment, a plurality of types of commands including an internal winning command, a left reel stop command, a middle reel stop command, a right reel stop command, a winning determination command, a power-on command, a door command, and an active command are sent from the main control board 14. Transmit to the control board 15. The internal winning command is a command that can specify the lottery result of the winning lottery process, and is transmitted when the start switch 6 is operated and the winning lottery process is executed. The left reel stop command is a command that can specify the stop position of the left reel, and is transmitted when the left reel stops. The middle reel stop command is a command that can specify the stop position of the middle reel, and is transmitted when the middle reel stops. The right reel stop command is a command that can specify the stop position of the right reel, and is transmitted when the right reel stops. The winning determination command is a command that can specify the presence / absence of a winning and the type of winning, and is transmitted when all the reels are stopped and the stop symbol determining process is performed. The power-on command is transmitted when the supply of power to the main control board 14 is started and the initial setting at the start-up in the main control board 14 is completed. The door command is a command indicating the detection state of the front door opening detection sensor 22, that is, ON (open state) / OFF (closed state), when the power is turned on, at the end of one game (after the game is over, the bet of the next game). Sent when the detection state of the front door opening detection sensor 22 changes (ON to OFF, OFF to ON) until the setting of the number can be started). The active command is a command that can specify whether or not an error has occurred in the main control board 14 and the type of error. Here, commands other than the active command are generated and transmitted according to the progress of the game and the operating state of the switch and sensor, whereas the active command is generated and transmitted regularly during the period when these commands are not transmitted. Sent.

  FIG. 5 shows signal lines included in the wire harnesses 16 a and 16 b that connect the main control board 14 and the sub control board 15. As shown in FIG. 5, the wire harness 16 a that connects the main control board 14 and the sub communication relay board 17 includes eight data signal lines 161 to 168, a strobe signal line 171, and a ground line 175. The eight data signal lines 161 to 168 are used to transfer command configuration data one by one (1 byte) in parallel communication. The strobe signal line 171 is for transferring a communication control signal. On the other hand, the wire harness 16b connecting the sub-communication relay board 17 and the sub-control board 15 has one data signal line 169, strobe signal line 172, enable signal line 173, clock signal line 174, and ground. Line 176 is included. One data signal line 169 is used to transfer command configuration data by a serial communication method, and a strobe signal line 172, an enable signal line 173, and a clock signal line 174 transfer signals for communication control. Is to do.

  FIG. 6 is a block diagram showing a control circuit related to communication between the main control board 14 and the sub control board 15. In the main control board 14, the main microcomputer 30 and the command transmission circuit 32 are connected via a data bus on the main control board 14. The main microcomputer 30 outputs a data signal of one command configuration data (1 byte) to the command transmission circuit 32 at intervals of 1.8 milliseconds. The command transmission circuit 32 holds the data signal of the configuration data using the clock signal input from the main microcomputer 30 as a trigger, and outputs it from the data signal output terminal 40. The data signal output from the data signal output terminal 40 is output to the data signal lines 161 to 168 via the connection terminal 41 and transferred to the sub communication relay board 17. The command transmission circuit 32 receives a clear signal from the outside. When the clear signal input switches from the H level (clear signal OFF) to the L level (clear signal ON), the command transmission circuit 32 switches from the operating state to the pause state. When the clear signal input is at the L level, the pause state is maintained, and when the clear signal input is switched to the H level, the operation state is restored. During the pause state, the command transmission circuit 32 sets all the voltage levels output to the data signal lines 161 to 168 to the H level regardless of the data signal input to the command transmission circuit 32. The main microcomputer 30 outputs a pulsed strobe signal at intervals of 1.8 milliseconds in accordance with the output of the data signal. The strobe signal output from the main microcomputer 30 is externally output from the connection terminal 41 and transmitted to the sub control board 15 via the sub communication relay board 17.

  As shown in FIG. 6, the data signal output from the main control board 14 is input to the parallel-serial communication circuit 35 of the sub-communication relay board 17 via the connection terminal 42. The parallel-serial conversion circuit 35 outputs the input data signal from the data signal output terminal 43 according to the clock signal and enable signal input from the sub-control board 15. Specifically, the parallel-serial conversion circuit 35 switches from the operating state to the resting state when the enable signal input is switched from the L level (enable signal ON) to the H level (enable signal OFF). Then, the pause state is maintained while the enable signal input is at the H level, and when the enable signal input is switched to the L level, the operation state is restored. The parallel-serial conversion circuit 35 outputs only the H level from the data signal output terminal 43 regardless of the input data signal during the pause state. Then, when the enable signal input is switched to the L level, the parallel-serial conversion circuit 35 takes in the data signal for one piece of configuration data (1 byte) inputted by the parallel communication method, and the taken data signal is serially communicated. The data is converted into a system and output from the data signal output terminal 43 in accordance with the clock signal input. A data signal output from the data signal output terminal 43 is output to the data signal line 169 via the connection terminal 44 and transferred to the sub-control board 15.

  As shown in FIG. 6, the sub microcomputer 31 of the sub control board 15 receives the strobe signal output from the main control board 14 via the connection terminal 45. When receiving the pulse strobe signal, the sub microcomputer 31 switches the enable signal output to the parallel-serial conversion circuit 35 of the sub communication relay board 17 from the H level to the L level. One (1 byte) data signal is received. When the sub microcomputer 31 receives a data signal for one piece of configuration data, it switches the output of the enable signal to the H level.

  In such a configuration, the main control board 14 outputs a data signal for one piece of configuration data and outputs a strobe signal for communication control at intervals of 1.8 milliseconds. The strobe signal is transferred to the sub-control board 15 without delay. The sub-control board 15 communicates with the sub-communication relay board 17 using the strobe signal as a trigger, and the data signal output from the main control board 14 is sent to the sub-communication relay board 17. It will be received via. In this embodiment, by repeating such communication between the main control board 14 and the sub control board 15, command configuration data is transferred to the sub control board 15 one by one at intervals of 1.8 milliseconds.

  Further, as shown in FIG. 6, the main control board 14 includes a detection circuit 33 according to the present invention. The detection circuit 33 is for detecting an improper current flowing into the data signal lines 161 to 168 between the main control board 14 and the sub communication relay board 17. Specifically, the detection circuit 33 is connected to a ground line 47 that connects the command transmission circuit 32 and the ground, and enters a detection state when the amount of current flowing through the ground line 47 exceeds a predetermined amount that does not occur in a normal state. Since the incorrect current flowing into the data signal lines 161 to 168 flows into the ground line 47 through the data signal output terminal 40, the incorrect current flows into the data signal lines 161 to 168, while the incorrect current flows into the data signal lines 161 to 168. This is because a large amount of current that does not occur at normal time flows. The detection circuit 33 outputs an H level clear signal to the command transmission circuit 32 in the non-detection state, and switches the clear signal to the L level that causes the command transmission circuit 32 to be in a pause state in the detection state. In other words, the L level clear signal output from the detection circuit 33 corresponds to a signal for putting the control data transmission circuit (command transmission circuit 32) according to the present invention in a dormant state. In this way, the main control board 14 is configured to detect when the improper current flows into the data signal lines 161 to 168 by the detection circuit 33 and switch the command transmission circuit 32 to the hibernation state.

  As shown in FIG. 6, the sub-communication relay board 17 also includes a detection circuit 36 according to the present invention. The detection circuit 36 is for detecting an improper current flowing into the data signal line 169 between the sub-communication relay board 17 and the sub-control board 15. Specifically, the detection circuit 36 is connected to a ground line 48 connecting the parallel-serial conversion circuit 35 and the ground, and the amount of current flowing through the ground line 48 is normal as in the detection circuit 33 of the main control board 14. When the amount exceeds a predetermined amount that does not sometimes occur, a detection state is entered. The detection circuit 36 outputs an L level enable signal to the parallel-serial conversion circuit 35 in the non-detection state, and switches the enable signal output to the H level in the detection state. . The enable signal output from the detection circuit 36 and the sub microcomputer 31 is configured to be input to the parallel-serial conversion circuit 35 through the OR circuit 50, and the detection circuit 36 outputs an H level enable signal. Regardless of the output of the enable signal of the sub microcomputer 31, the parallel-serial conversion circuit 35 is controlled to be in a pause state. In other words, the H level enable signal output from the detection circuit 36 corresponds to a signal for putting the control data transmission circuit (parallel-serial conversion circuit 35) according to the present invention in a dormant state.

  As described above, in this embodiment, a configuration (first configuration) for detecting an improper current flowing into the data signal lines 161 to 168 between the main control board 14 and the sub communication relay board 17, and the sub communication relay board 17 and a configuration (second configuration) for detecting an improper current flowing into the data signal line 169 between the sub-control board 15. These two configurations constitute the present invention separately. Specifically, in the first configuration, the main control board 14 and the sub communication relay board 17 correspond to the first board and the second board according to the present invention, respectively, and the command transmission circuit 32 according to the present invention. This corresponds to a control data transmission circuit. On the other hand, in the second configuration, the sub communication relay board 17 and the sub control board 15 correspond to the first board and the second board according to the present invention, respectively, and the parallel-serial conversion circuit 35 according to the present invention. This corresponds to a control data transmission circuit.

The main control board 14 will be described in detail below with reference to FIG.
The command transmission circuit 32 of the main control board 14 is configured by a logic IC, and constitutes latches FR1 to FR8 that hold data for one configuration data (1 byte) and a data signal output terminal 40. Transistors TR1 to TR8.

  The latches FR1 to FR8 are edge trigger type latches, a data signal input unit (D) to which a data signal is input, a clear signal input unit (R) to which a clear signal is input, and a clock to which a clock signal is input. A signal input unit (CLK) and a data signal output unit (Q) for outputting a data signal are provided. The latches FR1 to FR8 store and hold the data signal input using the clock signal input as a trigger when the input to the clear signal input unit (R) is at the L level (when the clear signal of the H level is input to the command transmission circuit 32). The retained data is output from the data signal output unit (Q). On the other hand, when the input to the clear signal input unit is at the H level (when the clear signal at the L level is input to the command transmission circuit 32), the output of the data signal output unit (Q) is always at the L level.

  The transistors TR1 to TR8 are field effect transistors and constitute a data signal output terminal 40 that outputs the outputs of the latches FR1 to FR8 to the data signal lines 161 to 168 to the outside. Specifically, the transistors TR1 to TR8 are switched ON and OFF in accordance with the output voltage level of the data signal output unit (Q) of each latch FR1 to FR8. When the transistors TR1 to TR8 are ON, the data signal The lines 161 to 168 are grounded, and the voltage of the data signal lines 161 to 168 becomes L level (0 V). When the transistors TR1 to TR8 are OFF, the voltage of the data signal lines 161 to 168 becomes H level by the pull-up resistor Rb (see FIG. 9) provided on the sub-communication relay board 17 side. Since the transistors TR1 to TR8 are general open drain type output terminals, detailed description thereof is omitted.

  As described above, the command transmission circuit 32 holds the data signal output from the main microcomputer 30 in the latches FR1 to FR8 and outputs the data signal from the data signal output terminal 40 to the data signal lines 161 to 168. Further, as described above, the clear signal input to the command transmission circuit 32 is configured to be input to the clear signal input unit (R) of each of the latches FR1 to FR8, and the clear signal input from the detection circuit 33 is performed. Is switched to the L level (clear signal ON), all the transistors TR1 to TR8 are switched to OFF, and the clear signal input is switched to the H level (clear signal OFF) regardless of the data signal input. All the data signal lines 161 to 168 are configured to be at the H level.

  As shown in FIG. 7, the detection circuit 33 of the main control board 14 includes a detection resistor Ra connected to the ground line 47 that connects the command transmission circuit 32 and the ground, and a detection resistor for detecting an inflow of an improper current. And a transistor TR9. In the detection circuit 33, when a large amount of incorrect current flowing into the data signal lines 161 to 168 flows into the ground line 47 and a voltage drop of a certain level or more occurs in the detection resistor Ra, the detection transistor TR9 is turned on. In this way, the clear signal output to the command transmission circuit 32 is switched to the L level (clear signal ON).

  Here, in the detection circuit 33, three delay circuits 46a, 46b, and 46c are provided on the base terminal side and the collector terminal side of the detection transistor TR9. The delay circuit 46a provided on the base terminal side is provided as a countermeasure against noise. When the state where the current flowing through the ground line 47 exceeds a predetermined amount continues for a certain time or longer, the operation of the detection transistor TR9 is performed. It delays the change of state. The delay circuit 46b provided on the collector terminal side is provided for adjusting the length of the pause delay period, and is cleared when the operation state of the detection transistor TR9 is switched from ON to OFF. This delays the switching of the output level of the signal. Another delay circuit 46c provided on the collector terminal side is for stably operating the delay circuit 46b, and a clear signal output to the command transmission circuit 32 is immediately after the detection transistor TR9 is turned on. This prevents the charge time of the capacitor C2 of the delay circuit 46b from being secured due to the L level. Since the delay circuits 46a, 46b, and 46c have an existing circuit configuration, detailed description thereof is omitted. The detection circuit 33 includes a switching transistor TR20. The transistor TR20 is turned off when no illegal current is detected. When the transistor TR20 is OFF, the clear signal output to the command transmission circuit 32 becomes H level by the pull-up resistor Rc.

  The operation of the detection circuit 33 when an illegal current flows will be specifically described with reference to FIG. When the fraudster starts to flow the illegal current into the data signal lines 161 to 168, the illegal current flows into the data signal output terminal 40 (Ta in FIG. 8). If the incorrect current flowing into the data signal output terminal 40 flows through the ground line 47 and a voltage drop of a certain level or more is generated in the detection resistor Ra, the detection transistor is detected at the time Tb delayed by the delay circuit 46a. TR9 switches to ON. When the detection transistor TR9 is turned on, at the time Tc delayed by the delay circuit 46c, the switching transistor TR20 is turned on, and the clear signal output to the command transmission circuit 32 is L level (clear signal ON). It becomes. Then, the command transmission circuit 32 is switched to a dormant state when an L level clear signal is input (Td in FIG. 8).

  When the inflow of the improper current is stopped (Te in FIG. 8), the detection transistor TR9 of the detection circuit 33 is turned off at the time Tf delayed by the base side delay circuit 46a. However, even after the detection transistor T9 is turned off, the detection circuit 33 sets the output state (clear signal ON) when the detection transistor TR9 is turned on by the two delay circuits 46b and 46c on the collector side. maintain. For this reason, the pause state of the command transmission circuit 32 continues until the delay time by the delay circuit 46b and the delay time by the delay circuit 46c elapse after the inflow of the improper current stops, and the clear signal is input at the time Tg. Becomes H level (clear signal OFF), the command transmission circuit 32 gradually returns to the operating state (Th in FIG. 8).

  As described above, the detection circuit 33 is configured so that the output of the clear signal continues for a certain pause delay period (Te to Tg) even after the inflow of the improper current is stopped by the internal delay circuits 46a, 46b, and 46c. Thus, the command transmission circuit 32 continues the pause state until the pause delay period elapses after the inflow of the improper current to the data signal output terminal 40 stops flowing. This pause delay period is set to 3.6 milliseconds, which is twice the transmission interval (1.8 milliseconds) of command configuration data.

  As described above, when an illegal current flows into the data signal lines 161 to 168 between the main control board 14 and the sub-communications relay board 17, the main control board 14 detects the illegal current and detects the illegal current. The transmission circuit 32 is set to a dormant state, and the dormant state is continued until the 3.6 msec pause delay period has elapsed even after the inflow of the illegal current is stopped.

The sub-communication relay board 17 will be described in detail below with reference to FIG.
The parallel-serial conversion circuit 35 of the sub-communication relay board 17 includes a serial / parallel conversion IC 51 that converts a data signal into a serial communication system, and a transistor TR10 that constitutes a data signal output terminal 43.

  The serial / parallel conversion IC 51 includes a control circuit 52, a data latch 53, and a shift register 54. A clock signal and an enable signal are input to the control circuit 52, and a data signal is input to the data latch 53 from the main control board 14 by a parallel communication method. When the enable signal input to the control circuit 52 switches from the H level to the L level, the serial / parallel conversion IC 51 causes the data latch 53 to capture the data signal, the shift register 54 converts the data signal to the serial communication system, and the clock signal. A data signal is output to the transistor TR10 in accordance with the input. When the enable signal input to the control circuit 52 is switched from the L level to the H level, the serial / parallel conversion IC 51 is switched to the stop state, and the transistor TR10 is switched to the L level until the enable signal input is switched to the H level. Continue to input the signal.

  The transistor TR10 is a field effect transistor that constitutes an open drain type output terminal, and is switched ON and OFF in accordance with the output voltage level of the serial / parallel conversion IC 51, and outputs a data signal to the data signal line 169. That is, when the transistor TR10 is ON, the data signal line 169 is grounded and becomes L level (0 V), and when the transistor TR10 is OFF, the data signal line is pulled by the pull-up resistor Rb provided on the sub-control board 15 side. The voltage at 169 becomes H level. In such a configuration, while the serial / parallel conversion IC 51 is in a stopped state, the transistor TR10 is turned off, and the voltage level of the data signal line 169 is at the H level. That is, the parallel-serial conversion circuit 35 enters a halt state when the serial / parallel conversion IC is suspended.

  The detection circuit 36 of the sub-communications relay board 17 has a basic circuit configuration that is simply changed from an L-level clear signal to an H-level enable signal in the detection state. 33 (see FIG. 7). That is, although a detailed circuit diagram is omitted, the detection circuit 36 includes a detection resistor connected to the ground line 48 and a detection transistor for detecting an inflow of an improper current, and is connected to the data signal line 169. When a large amount of improper current that has flowed into the ground line 48 flows into the ground line 48, the detection transistor is switched on, and the enable signal output is switched to the H level. As described above, the enable signal output from the detection circuit 36 and the sub-microcomputer 31 is configured to be input to the serial / parallel conversion IC 51 through the OR circuit 50, and the detection circuit 36 has an H level enable signal. Is output, the parallel-serial conversion circuit 35 enters a halt state.

  Similarly to the detection circuit 33 of the main control board 14, the detection circuit 36 of the sub-communications relay board 17 includes a delay circuit that delays switching of the output level of the enable signal with respect to the inflow / stop timing of the incorrect current. Even after the inflow of the improper current is stopped, the enable signal output is maintained at the H level (enable signal OFF) during the pause delay period of 3.6 milliseconds. The delay circuit causes the parallel-serial conversion circuit 35 to be in a dormant state after the inflow of the improper current, and the inactive delay period of 3.6 milliseconds elapses after the inflow of the improper current is stopped. Until it does, it is comprised so that a dormant state may be continued.

  As described above, in this embodiment, when an illegal current flows into the data signal line 169 that transfers a command from the sub communication relay board 17 to the sub control board 15, the detection circuit 36 detects the illegal current. Thus, the parallel-serial conversion circuit 35 is put into a hibernation state, and the hibernation state is continued until the 3.6 msec pause delay period elapses even after the inflow of illegal current is stopped.

FIG. 10 shows the control contents of the CPU of the main control board 14 and shows the control contents of the main control process constituting the main routine. Details of steps S100 to S108 executed in the main control process are as follows.
S100: Wait until a predetermined number (the number of medals required to execute one game) is set.
S101: Wait until the start switch 6 is operated.
S102: When the start switch 6 is operated, the latch circuit extracts the random number generated by the random number generation circuit. It is determined whether or not winning of the winning combination is allowed based on the extracted random number value. Further, when the start switch 6 is operated, a new bet number cannot be set.
S103: The rotation of each reel 9 is started, and when the reel 9 reaches a predetermined rotation speed, the operation of the stop switch 7 is validated.
S104: Wait until the player operates the stop switch 7.
S105: When the player operates the stop switch 7, the reel 9 corresponding to the operated stop switch 7 stops rotating.
S106: Wait until all the reels 9 stop rotating.
S107: It is determined whether or not the display result derived by the reel 9 is in a predetermined mode. Specifically, it is determined whether or not the combination of symbols displayed on the winning line matches the combination of symbols determined as a predetermined winning combination. Is determined.
S108: A process according to the determination result of the stop symbol determination process is performed. Specifically, when it is determined that a winning has occurred, the number of payouts corresponding to the winning is added to the credit, and when the credit exceeds a predetermined number (50), the surplus medal is paid out. put out. Thereafter, the setting of the bet number for the next game can be started.

  FIG. 11 shows the contents of command transmission processing executed by the CPU of the main microcomputer 30. This command transmission process is executed every time the aforementioned interrupt occurs, that is, at an interval of 1.8 milliseconds. In the command transmission process, first, it is determined whether or not all the configuration data constituting the command has been transmitted, that is, whether or not the command is being transmitted (S200). If it is determined that the command is being transmitted, the process proceeds to step S203. If it is determined that the command is not being transmitted, the process proceeds to step S201. In step S201, it is determined whether or not the transmission buffer is empty. If it is determined that the transmission buffer is empty, an active command is generated and stored in the transmission buffer (S202), and the process proceeds to step S203. If it is determined that the transmission buffer is not empty, the process directly proceeds to step S203. In step S203, one byte (configuration data) of the command stored in the transmission buffer is output to the command transmission circuit 32, and a strobe signal is output to the sub-control board 15 to complete the command transmission process. .

  Thus, the CPU of the main microcomputer 30 generates a command according to the progress of the game according to the execution state of the main control process, and stores it in the transmission buffer. Further, the CPU of the main microcomputer 30 determines whether or not the detection state of the front door opening detection sensor 22 has changed every time the above-described interruption occurs, and generates a door command and stores it in the transmission buffer. To do. Then, when the transmission buffer becomes empty, the CPU of the main microcomputer 30 generates an active command and stores it in the transmission buffer, thereby transmitting the command to the sub-control board 15 without interruption. The sub-control board 15 always receives the signal at intervals of 1.8 milliseconds.

FIG. 12A shows the control contents of the CPU of the sub-microcomputer 31 and the control contents of the sub-control processing constituting the main routine. As shown in FIG. 12A, in such sub-control processing, whether or not the CPU of the sub-microcomputer 31 stores a predetermined number (5) of configuration data in the buffer area of the RAM, that is, one It is repeatedly determined whether or not this command has been received (S301), and if it is determined that one command has been received, a received command abnormality detection process is executed (S302). In this received command abnormality detection process, the following items (i) to (c) are checked, and only when it is determined that all are normal, it is determined that the received command is normal.
B) Are the fixed values (“ST”, “EN”) stored at the front and end of the command normal?
B) Is the checksum normal?
C) Is the data part normal?

  Then, after the received command abnormality detection process is completed, it is determined whether or not the check result of the received command is normal (S303). If it is determined that the check result is normal, the process corresponding to the received command is performed. Execute (S304). For example, when an internal winning command is received, an effect based on the result of the combination lottery process is started. Specifically, the left reel corresponding image, the middle reel corresponding image, and the right reel corresponding image are displayed on the liquid crystal display 10. When a left reel stop command, middle reel stop command, and right reel stop command are received, an effect corresponding to each reel is performed. Specifically, when a left reel stop command is received, the left reel corresponding image is deleted. If the winning combination corresponding to the result of the winning lottery process is not realized based on the stop position, the effect started based on the reception of the internal winning command is stopped. When the winning determination command is received, the effect started based on the reception of the internal winning command is ended. Furthermore, when there is a prize, an effect is executed according to the type of prize. When a power-on command is received, if no communication error has occurred at the time of reception, the sub-control board 15 executes an initialization process. Further, when the door command is received and the door command indicates the release of the front door 3, it is notified that the front door 3 is open. Specifically, the fact is displayed on the liquid crystal display 10. In addition, when an active command indicating an error state is received, notification is performed in such a manner that the type of error can be specified. Specifically, an error code corresponding to the type of error is displayed on the liquid crystal display 10. On the other hand, if it is determined in step S303 that the check result of the received command is not normal, a communication error process (S305) is executed assuming that a communication error has occurred. That is, the communication error detection means according to the present invention is realized by steps S302 and S303. The communication error process will be described later.

  The sub microcomputer 31 causes the CPU to generate an interrupt each time a strobe signal is received, receives one piece of configuration data from the sub communication relay board 17 each time this interrupt occurs, and stores it in the buffer area of the RAM. To do.

  FIG. 12B shows the control contents of communication error processing executed by the CPU of the sub microcomputer 31. This communication error process is executed when it is determined that the received command is not normal as described above. Specifically, in the communication error processing, a communication error display (error notification) for notifying the occurrence of a communication error is performed on the liquid crystal display 10 (S401), and it is determined whether or not an error release condition is satisfied (S402). ). Then, the communication error display (S401) is continued until it is determined that the error cancellation condition is satisfied. While this communication error display (S401) continues, no other image is displayed on the liquid crystal display 10. In this embodiment, when the power is turned on again and the front door 3 is opened, an error cancellation condition for ending the communication error process is set. Specifically, the initialization process is executed only when the power-on command and the door command are received and the door command indicates that the front door 3 is opened, and the communication error process is completed by the initialization. To do. In other words, during the execution of the communication error process, even if only the power-on command is received, the initialization process is not performed and the communication error process is not terminated.

  A mode of detecting an illegal act on the data signal lines 161 to 169 will be described with reference to FIG. FIG. 13A is a timing chart showing a command transmission / reception mode when an illegal act is performed on the data signal lines 161 to 168 between the main control board 14 and the sub communication relay board 17. In such an example, normal communication is performed until the time T1 when the fraud is started. That is, the main control board 14 transmits configuration data (“ST”, “05”, etc.) one by one at intervals of 1.8 milliseconds, and each transmitted configuration data is delayed via the sub-communication relay board 17. Without being received by the sub-control board 15. On the other hand, in the period (T1 to T2) in which fraud is performed, the configuration data (“FF”) output from the main control board 14 does not reach the sub-communication relay board 17 and is altered by the fraudster. The configuration data (“modified”) is received by the sub-control board 15. At this time, the detection circuit 33 of the main control board 14 detects the inflow of an illegal current caused by an illegal action, switches the clear signal output to the L level, and the command transmission circuit 32 enters a dormant state. Even if the cheating is stopped at the time T2, the detection circuit 33 continues to output an L level clear signal during the pause delay period, so that the pause state continues until the time T3 when the pause delay period elapses.

  As described above, in the pause state of the command transmission circuit 32, the data signal output terminal 40 of the command transmission circuit 32 continues to output H level signals to all eight data signal lines 161-168. For this reason, during the rest state (T1 to T3), the configuration data “FF” in which all 8 bits are “1” is 1 from the main control board 14 regardless of the data signal output from the main microcomputer 30. Output at 8 millisecond intervals. This configuration data “FF” is difficult to reach the sub-control board 15 during fraud (T1 to T2), but reaches the sub-control board 15 during the pause delay period (T2 to T3) after the fraud. To do. Since the pause delay period is set to 3.6 milliseconds, which is twice the transmission interval of the configuration data, the sub control board 15 receives two pieces of configuration data “FF” during the pause delay period. After the pause delay period elapses (T3), the command transmission circuit 32 that has returned to the normal state is configured one by one at intervals of 1.8 milliseconds according to the data signal input from the main microcomputer 30. Data (“EN”, “ST”, etc.) is transmitted.

  In this way, in the example of FIG. 13A, during the fraudulent acts (T1 to T2) due to the fraudulent acts on the data signal lines 161 to 168, the sub-control board 15 changes the configuration data ( During the pause delay period after the fraud (T2 to T3), the sub-control board 15 receives the configuration data “FF” output from the command transmission circuit 32 in the pause state. Here, the command received by the sub-control board 15 in the period (T0 to T4) including the pause delay period is the command data circuit 32 in the pause state in the fourth configuration data in which the checksum “CH” should exist. Since there is configuration data “FF” output from the sub-control board 15, the sub-control board 15 determines that the received command is abnormal at the time of checking the received command (T4), and notifies the occurrence of a communication error. The communication error display is executed at the same time. In this example, it is determined that the received command is abnormal when the configuration data “CH” storing the checksum of the command is replaced with FF. However, according to the received command abnormality detection process, the checksum is The command can be determined to be abnormal not only when “FF” is replaced but also when the fixed value or two pieces of configuration data constituting the data portion are replaced with “FF”.

  As described above, in this embodiment, when an illegal act is performed on the data signal lines 161 to 168, the sub control board 15 outputs the two pieces of configuration data output from the command transmission circuit 32 during the pause delay period. Based on “FF”, it is determined that the received command is abnormal, and a communication error display is executed to notify the communication error. For this reason, even if the fraudster modifies the configuration data so that it is determined to be normal by the sub-control board 15, the slot machine 1 of the present embodiment uses a communication error based on the fraudulent act. Display will be executed.

  FIG. 13B is a timing chart when an illegal act is performed on the data signal line 169 between the sub communication relay board 17 and the sub control board 15. Although the basic flow is the same as that in FIG. 13A, in this example, if the fraudulent act is started at the time T1, the fraudulent act is performed and the detection circuit 36 of the sub-communication relay board 17 is fraudulent. The current is detected and the parallel-serial conversion circuit 35 is controlled to a halt state. Even in this example, the parallel-serial conversion circuit 35 is kept in a pause state until the time T3 when the pause delay period elapses even if the illegal act is stopped at the time T2.

  In the rest state of the parallel-serial conversion circuit 35, the data signal output terminal 43 of the parallel-serial conversion circuit 35 continues to output an H level signal to the data signal line 169. For this reason, during the rest state (T1 to T3), regardless of the data signal input from the main control board 14, the configuration data “FF” in which all 8 bits are “1” is sent to the sub control board 15. Output at 8 millisecond intervals.

  Therefore, even in such an example, as in the case of FIG. 13A, two pieces of configuration data “FF” are received by the sub-control board 15 in the pause delay period (T2 to T3) after the fraud. At time T4, the sub-control board 15 determines that the received command including the two configuration data “FF” is abnormal, and executes a communication error display to notify the communication error. It becomes.

  As described above, in this embodiment, when an illegal act is performed on the data signal lines 161 to 169 for transferring a command, the sub-control board 15 is in a pause delay period after the illegal act is stopped. Two configuration data “FF” are transmitted to the sub-control board 15, and the sub-control board 15 determines that a command including the configuration data “FF” is an abnormal command. As a result, it is possible to reliably prevent an illegal act in which an unauthorized current is supplied to the data signal lines 161 to 169 to modify or insert a command.

  In particular, in this embodiment, since the detection information of the improper current is not fed back to the main microcomputer 30 that is the command transmission source, the signals output from the detection circuits 33 and 36 are not easily used for other fraudulent acts. There is an advantage.

  In addition, as a sub-control process (see 12A) of this embodiment, a process for determining whether or not a received command is normal or an error as a communication error when it is determined that a received command is abnormal Since the process for performing the notification or the like is a process that is also executed on the sub-control board of the existing slot machine, in this embodiment, the sub-control board 15 does not perform a special process, and the data signal line has an illegal current. Can prevent fraudulent acts that cause the inflow. In this embodiment, since the detection circuit 33 is connected to the ground signal line 47 that connects the command transmission circuit 32 and the ground, the inflow of incorrect current to the plurality of data signal lines 161 to 168 is collected at one place. There is an advantage that can be detected.

  In the present embodiment, the communication method of the main control board 14 and the sub control board 15 is changed from the first embodiment. Since the communication method between the main control board 14 and the sub control board 15 is the same as that of the first embodiment, the description thereof is omitted. As shown in FIG. 14, in this embodiment, the main control board 14 and the sub control board 15 are directly connected by a single data signal line 170 without going through a relay board. A command transmitted from the main control board 14 to the sub control board 15 is transmitted in one direction by the asynchronous serial communication system via this one data signal line.

  Specifically, in this embodiment, the data signal of the configuration data output by the main microcomputer 30 every 1.8 milliseconds is transmitted to the command reception circuit 37a of the sub control board 15 by the command transmission circuit 32a by asynchronous serial communication. Transfer using the method. The command transmission circuit 32a is composed of a serial communication IC, and is in a pause state during the period when the L level clear signal is input from the detection circuit 33, and the data signal output terminal 40 is connected to the data signal line. The H level signal is continuously output to 170. The detection circuit 33 is the same as that in the first embodiment. That is, when the detection circuit 33 detects an incorrect current flowing from the data signal line 170 to the ground line 47, the detection circuit 33 outputs an L level clear signal to the command transmission circuit 32a. By maintaining the clear signal output at the L level during the millisecond pause delay period, the command transmission circuit 32a is put into a pause state until the pause delay period elapses even after the illegal current inflow is stopped.

  The command receiving circuit 37a of the sub-control board 15 is composed of a serial communication IC, and the configuration data transferred from the command transmitting circuit 32a is temporarily stored in the receiving buffer 57 of the command receiving circuit 37a. . The CPU of the sub microcomputer 31 generates an interrupt at intervals of 1.2 milliseconds, executes a configuration data check process for determining whether or not configuration data is stored in the reception buffer 57, and stores the configuration data. If so, a process of transferring to the sub microcomputer 31 is performed. When the configuration data for one command (5) is received, it is determined whether or not the received command is normal in the same manner as in the first embodiment. The processing according to the first embodiment is executed, and when it is determined that there is an abnormality, it is detected as a communication error, and the same processing as the communication error processing (FIG. 12B) of the first embodiment is executed.

  The CPU of the sub-microcomputer 31 monitors the reception interval of the configuration data by counting the number of times that the configuration data check process continuously determines that the configuration data is not stored in the reception buffer 57. Since the configuration data is always transmitted from the main control board 14 at intervals of 1.8 milliseconds, when communication is normally performed, at least two configuration data confirmation processes (2.4) are performed when an interrupt occurs. The configuration data is confirmed in the reception buffer 57 once every millisecond. In other words, when the configuration data cannot be confirmed twice or more consecutively in the configuration data confirmation process, communication is not normally performed. In the present embodiment, the CPU of the sub-microcomputer 31 detects a communication error even when the configuration data cannot be confirmed twice in the configuration data check process in this way, and the communication error process of the first embodiment (FIG. 12 ( B)) is configured to execute.

  A mode of detecting the inflow of an unauthorized current to the data signal line 170 will be described with reference to FIG. FIG. 15 is a timing chart when an illegal act is performed on the data signal line 170 between the main control board 14 and the sub control board 15. In such an example, during the period from T1 to T2 where fraudulent acts are performed, the configuration data (“modification”) modified / inserted by the unauthorized electronic component is received by the sub-control board 15. At this time, the detection circuit 33 of the main control board 14 detects the inflow of an improper current caused by an improper action, switches the clear signal output to the L level, and the command transmission circuit 32a enters a dormant state. This hibernation state continues until time T4 when the hibernation delay period elapses even if the illegal act stops at time T2.

  Here, in this embodiment, the configuration data is transferred to the sub-control board 15 by the asynchronous serial communication method via the data signal line 170, so that the command transmission circuit 32 a is in a dormant state and is transferred to the data signal line 170. When only the H level signal is output, the start bit does not exist and the configuration data is not stored in the reception buffer 57, and the configuration data is not transferred from the main control board 14 to the sub control board 15. If the fraudulent act is in progress (T1 to T2), the fraudulent configuration data inserted by the fraudulent person can be received by the sub-control board 15, but the pause delay period after the fraudulent act (T2 to T4) is 1. The configuration data that should be received at intervals of 8 milliseconds is not received by the sub-control board 15. As described above, since the sub-control board 15 is configured to detect a communication error when the configuration data is not received for 2.4 milliseconds or more, in this example, the pause delay period of 2.4 milliseconds has elapsed. At that time (T3), the sub-control board 14 detects it as a communication error, and communication error processing is executed. If the command transmission circuit 32a is configured to output only an L level signal to the data signal line 170 when the command transmission circuit 32a is in a dormant state, a stop bit does not exist, so that a framing error occurs and the reception buffer The configuration data is not stored in 57 and is detected as a communication error.

  As described above, the present invention can also be applied to the case where the main control board 14 and the sub control board 15 transfer commands by the asynchronous serial communication method. In particular, in the present embodiment, when the configuration data reception interval of the sub control board 15 is longer than the transmission interval of the configuration data of the main control board 14, it is configured to detect as a communication error. There is an advantage that even if the command output from the board 14 is not partially lost but is totally lost, it can be detected as a communication error.

  The present invention is not limited to the embodiment described above, and various modifications can be made without departing from the spirit of the present invention. For example, the command transmission method from the main control board to the sub control board is not limited to the method of the first and second embodiments, and can be changed as appropriate, such as transmitting commands directly to the sub control board by the parallel communication method. In addition, the data signal output terminal according to the present invention is not limited to an open drain type output terminal, and an output method such as a three-state method can also be adopted.

  In addition, the detection circuit according to the present invention may be any circuit as long as it can detect a large amount of unauthorized current flowing into the data signal line, and the circuit configuration is not limited to the configuration of the embodiment and can be changed as appropriate. The detection circuit can also be installed between the data signal output terminal and the connection terminal.

  In the above embodiment, the pause delay period of the detection circuit is set to be twice as long as the transmission interval of the configuration data. However, in the pause delay period according to the present invention, the sub-control board is surely regarded as a communication error. It is sufficient to continue for a period that can be detected. Further, the pause delay period according to the present invention is not limited to a period that ends with the elapse of a fixed time, but is a period that continues until a predetermined end condition is satisfied, such as a period until the power is turned on again. It does not matter.

  In the above embodiment, the command configuration data is transmitted from the main control board to the sub control board at a constant interval. However, in the present invention, the command transmission interval does not need to be constant, and the pause delay period. Any interval at which at least one piece of configuration data is transmitted is sufficient.

  In the above embodiment, the command transmission circuit and the parallel-serial conversion circuit constituting the control data transmission circuit are configured to continuously output the H level signal during the hibernation state. The transmission circuit may control the output voltage of the data signal output terminal at the L level during the sleep state. The configuration for controlling the output voltage during the hibernation state to the L level can be realized simply by providing an inverting circuit or the like in the configuration of the above embodiment and inverting the input voltage to the data signal output terminal. For example, in the case of the parallel-serial conversion circuit 35 shown in FIG. 9, by simply removing the inverting circuit 49 in front of the data signal output terminal 43, an L level signal continues to be output during the pause state.

  In the above embodiment, the unauthorized current flowing into the data signal line is detected by the detection circuit of the main control board or the sub-communication relay board. However, the detection circuit according to the present invention flows into the strobe signal line or the like. An illegal current can also be targeted for detection.

  In the above embodiment, the detection of unauthorized current by the detection circuit is notified to the sub-control board only through the data signal line. However, the gaming machine according to the present invention uses the dedicated unauthorized detection signal line. Thus, in parallel with the data signal line, the sub-control board may be notified of detection of an illegal current. With this configuration, when the fraudulent electronic component does not act on the fraud detection signal line and the fraudulent electronic component acts only on the data signal line, sub-control immediately after the detection circuit detects the fraud current. It is possible to notify the board.

  The present invention is not limited to command transmission from the main control board to the sub control board, but can be applied to command transmission between other control boards. Further, the present invention is not limited to slot machines but can be applied to gaming machines such as pachinko machines.

1 slot machine (game machine)
14 Main control board (first control board)
15 Sub control board (second control board)
16a, 16b Wire harness 17 Sub communication relay board 30 Main microcomputer 31 Sub microcomputer 32, 32a Command transmission circuit (control data transmission circuit)
33, 36 Detection circuit 35 Parallel-serial conversion circuit (control data transmission circuit)
40, 43 Data signal output terminals 46a, 46b, 46c Delay circuits 160-170 Data signal lines

Claims (5)

A first control board for transmitting control data, and have your a game machine and a second control board for performing control based on the control data received from the first control board,
Comprising one or a plurality of data signal lines for transferring the control data output by the first control board ;
The first control board includes a control data transmission circuit including a data signal output terminal for outputting control data to the data signal line,
The control data transmission circuit is controlled to a pause state in which normal control data cannot be output from the data signal output terminal in accordance with a signal input from the outside.
Furthermore, the first control board includes a detection circuit that detects that a current flowing from the data signal line to the data signal output terminal is a predetermined amount or more,
When the detection circuit detects that the current flowing from the data signal line to the data signal output terminal exceeds a predetermined amount, the detection circuit transmits a signal for setting the control data transmission circuit to the pause state. A signal for putting the control data transmission circuit in the dormant state for a predetermined pause delay period even after the current flowing into the data signal line from the data signal line to the data signal output terminal falls below the predetermined amount. Is output continuously,
The first control board transmits a part or all of the control data to the second control board at least once in a predetermined period shorter than the pause delay period,
The gaming machine according to claim 2, wherein the second control board includes a communication error detecting means for detecting an abnormal reception state of the control data generated during the pause delay period as a communication error. A first control board that transmits control data, a second control board that performs control based on the control data received from the first control board, and control data between the first control board and the second control board the and have you in a gaming machine and a relay board for relaying,
Comprising one or more data signal lines for transferring the control data output by the relay board ;
The relay board includes a control data transmission circuit including a data signal output terminal that outputs control data to the data signal line,
The control data transmission circuit is controlled to a pause state in which normal control data cannot be output from the data signal output terminal in accordance with a signal input from the outside.
Further, the relay board includes a detection circuit that detects that a current flowing from the data signal line to the data signal output terminal is a predetermined amount or more,
When the detection circuit detects that the current flowing from the data signal line to the data signal output terminal exceeds a predetermined amount, the detection circuit transmits a signal for setting the control data transmission circuit to the pause state. A signal for putting the control data transmission circuit in the dormant state for a predetermined pause delay period even after the current flowing into the data signal line from the data signal line to the data signal output terminal falls below the predetermined amount. Is output continuously,
The first control board transmits a part or all of the control data to the second control board at least once in a predetermined period shorter than the pause delay period,
The gaming machine according to claim 2, wherein the second control board includes a communication error detecting means for detecting an abnormal reception state of the control data generated during the pause delay period as a communication error. The control data transmission circuit controls the output voltage of the data signal output terminal to either H level or L level, and in the rest state, the output voltage of the data signal output terminal is all H level or all L level. is intended to control to,
In the abnormal reception state that the communication error detection means detects as the communication error, the control data transmission circuit sets the output voltages of the data signal output terminals to all H levels or all L levels over the pause delay period. The gaming machine according to claim 1 , wherein the gaming machine is in a reception state when controlled . When the control data transmission circuit is in a dormant state during the pause delay period, the second control board is configured to receive abnormal control data,
The communication error detection means determines at any time whether or not the control data received by the second control board is normal ,
Wherein said abnormal reception state of a communication error detecting means detects as said communication error is one of the claims 1 to 3 control data to which the second control board is received, characterized in that a state is abnormal The gaming machine according to claim 1 . During the pause delay period, the control data transmission circuit is in a pause state, so that the second control board is configured not to receive part or all of the control data,
The communication error detection means measures a reception interval at which the second control board receives a part or all of the control data ,
Wherein said abnormal reception state of a communication error detecting means detects as said communication error is any one of claim 1 to claim 3 wherein the reception interval is characterized in that it is a state in which longer than the predetermined time period The gaming machine described in 1.

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