JP5493684B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  According to the present invention, when a fuse element disposed in a semiconductor device is melted with a laser beam, the fuse element can be surely melted without increasing the chip area, and the reliability of circuit components disposed around the fuse element can be improved. The present invention relates to a semiconductor device that can improve performance and a method for manufacturing the same.

  Laser trimming techniques are frequently used in semiconductor devices, and it is known to adjust the characteristics of semiconductor products by fusing fuse elements formed of polysilicon or the like with laser light.

In this case, since it is necessary to melt the fine fuse element accurately, it is necessary to reliably reach the fuse element with the power of the laser beam through the interlayer insulating film.
FIG. 38 is a fragmentary plan view of the fuse element disposed in the semiconductor device of the first conventional example, and FIG. 39 is a fragmentary sectional view taken along line XX in FIG.

  Here, the fuse element 63 is formed on an insulating film 62 made of a silicon oxide film. On the fuse element 63, an interlayer insulating film 64 made of a silicon oxide film and an opening 66 made of a silicon nitride film thereon. A protective film 65 is formed. In the figure, 61 is a semiconductor substrate, and 67 is a laser beam for fusing the fuse element 63.

In the silicon nitride film (protective film 65), the protective film 65 on the fuse element 63 is removed to form an opening 66 in order to absorb the power of the laser light 67.
On the other hand, the silicon oxide film (interlayer insulating film 64) transmits the laser light 67 without absorbing the power of the laser beam 67. Therefore, the interlayer insulating film 64 on the fuse element 63 is left to protect the fuse element 63. Yes. However, the wavelength of the laser beam 67 is, for example, 1047 nm.

  However, when the thickness of the interlayer insulating film 64 is increased, as shown in FIG. 39, the heat generated by the power of the laser beam 67 instantaneously transmitted to the fuse element 63 cannot be diffused and accumulated. Stress is accumulated in the region 69 around the fuse element 63 due to the internal stress generated by the accumulated heat, and the stress is propagated to generate a crack 71 in the interlayer insulating film 64. The stress propagation direction 70 is radially centered on the fuse element 63, and the stress propagates not only in the direction of the opening 66 but also in the lateral direction. Furthermore, since the upper part of the fuse element 63 is covered with the thick interlayer insulating film 64, the impact when the fuse element 63 is blown spreads radially in the interlayer insulating film 64 (same as the stress propagation direction 70). Cracks 71 are generated and propagated.

  Therefore, the crack 71 propagates not only to the interlayer insulating film 64 above the fuse element 63 but also to the interlayer insulating film 64 covering the circuit component element 73 around the fused fuse element 63 and the adjacent unfused fuse element 63a. . The reliability of the circuit constituent element 73 adjacent to the fuse element 63 and the adjacent unfused fuse element 63a is reduced by moisture or the like that has entered from the crack 71.

  As the number of metal wiring layers increases, the interlayer insulating film that electrically insulates the metal wiring layers becomes thicker, the accumulation of internal stress increases, and cracks in the lateral direction tend to enlarge. As a measure for solving this, a second conventional example will be described.

In Patent Document 1, which is a second conventional example, a manufacturing method for solving the above-described problems according to the first conventional example is disclosed.
FIG. 40 is a fragmentary cross-sectional view of the fuse element region for each process in the second conventional example. A fuse element 77 is formed on an insulating film 76 formed on a semiconductor substrate (not shown). Further, on the fuse element 77, a lowermost first interlayer insulating film 78 (for example, a BPSG film), A first metal wiring layer 79 and a second interlayer insulating film 80 (for example, a TEOS film) are formed (FIG. 40A).

  Next, at the same time as opening the through hole 81 for electrical connection with the first metal wiring layer 79, the second interlayer insulating film 80 (for example, TEOS film) in the fuse element region is also opened. 82 is formed. At this time, the surface layer of the first interlayer insulating film 78 under the opening 82 is also removed (FIG. 40B).

  Next, a second metal wiring layer 83 (for example, a pad electrode) is formed, electrically connected to the first metal wiring layer 79 through the through hole 81, and a protective film 84 (in detail) is formed on the entire surface. Is formed of a silicon oxide film on the lower side and a silicon nitride film on the upper side), and openings 85 and 86 are formed on the second metal wiring layer 83 (pad electrode) and the fuse element 77. A resist pattern 92 is formed (FIG. 40C).

Next, using the resist pattern 92 as a mask, openings 93 and 94 are formed in the protective film 84 on the second metal wiring layer 83 (pad electrode) and the fuse element 77 (FIG. 40D).
Normally, as the number of metal wiring layers increases, the number of interlayer insulating films also increases. In this example, each time the interlayer insulating film is formed, the interlayer on the fuse element 77 is formed in the same manner as the through-hole formation. By opening the insulating film (described in claim 2 of Patent Document 1), the thickness of the remaining film of the interlayer insulating film formed on the fuse element 77 (the thickness of the interlayer insulating film 78) is constant. Therefore, it is described that the fuse element 77 can be blown out without generating cracks with an appropriate power of laser light.

  In this case, it is considered that the interlayer insulating film on the fuse element 77 is formed thin, and that the thin part can be prevented from being propagated to other parts by scattering due to the fusing impact of the fuse element. In addition, it is considered that heat generation is easily diffused due to the thin remaining film, and generation of cracks is avoided. However, this conventional example has the following problems.

  First, in order to blow the fuse element 77 so that cracks do not occur at an appropriate laser intensity, the interlayer insulating film on the fuse element 77 is removed every time a through hole is formed, and the thickness of the remaining film of the interlayer insulating film is removed. The thickness is reduced to a certain thickness, and as a result, the depth of the recess (indentation) of the interlayer insulating film on the fuse element 77 is increased.

  When this dent becomes large, in the manufacturing process after the dent is formed, the resist is absorbed into the deepened dent, and the resist film thickness on the circuit component adjacent to the fuse element 77 is locally reduced. In this case, variations in processing dimensions increase, and circuit design restrictions such as the inability to miniaturize circuit constituent elements adjacent to the fuse element 77 occur.

  Further, when the depth of the recess of the interlayer insulating film on the fuse element 77 is remarkably large, the resist film thickness around the recess becomes insufficient, and as a result of no resist during dry etching, the circuit configuration formed around the recess There is also a problem that the element disappears.

  In general, a coating material such as SOG (spin-on-glass) is used as a planarizing material for leveling reduction of a metal wiring layer or the like. Then, like the resist, the planarizing material is absorbed in the recess, and the planarization of the interlayer insulating film and the protective film on the circuit constituent element adjacent to the fuse element 77 is deteriorated. This phenomenon becomes more prominent as the thickness of the interlayer insulating film that electrically insulates and separates the metal wiring layers increases as the number of metal wiring layers increases. In this case, circuit constituent elements around the fuse element are arranged avoiding the area where the flattening is deteriorated (dented area), which is not preferable because the chip area increases.

  Further, when the interlayer insulating film becomes thicker, the depth of the recess becomes larger. A metal residue remains along the ridge (outer peripheral portion) at the bottom of the dent in the formation of the metal film to be the metal wiring layer performed after the formation of the through hole. As a result, the metal residue is exposed to heat treatment or chemical cleaning in a subsequent process, and peeled off in the middle of the process to become a foreign substance, which may cause a problem such as an electrical short circuit between the metal wiring layers.

  Further, in this method, since the sidewall of the opening 82 of the interlayer insulating film 80, which is a silicon oxide film on the fuse element 77 region, is exposed, moisture or the like infiltrates from the sidewall to peel off the multilayer interlayer insulating film. Or a characteristic variation in the long-term reliability of the circuit component adjacent to the fuse element 77 is generated. As a third conventional example, Patent Document 2 and Patent Document 3 disclose a manufacturing method for solving this problem.

FIG. 41 is a fragmentary cross-sectional view of the fuse element for each process in the third conventional example (Patent Document 2).
In this example, in the second conventional example, a protective film 84 is formed on the entire surface, and then a resist pattern 87 having an opening on the fuse element 97 is formed (FIG. 41A). At this time, the opening 88 of the resist pattern 87 for opening the protective film 84 on the fuse element 97 is formed inside the concave opening 89 of the protective film 84.

  Next, the protective film 84 on the fuse element 97 is opened with a resist pattern 87, and an opening 84a of the protective film 84 is formed on the fuse element 97 (FIG. 41B). At this time, the opening 84a of the protective film 84 made of the silicon nitride film on the fuse element 97 opens inside the opening 99a of the interlayer insulating film 99 made of the silicon oxide film, so that the protective film 84 is formed. A silicon nitride film is formed on the sidewall of the interlayer insulating film 99 made of a silicon oxide film. Since the opening side wall of the interlayer insulating film made of the silicon oxide film is covered with the silicon nitride film, it is possible to prevent intrusion of moisture and the like.

However, this third conventional example has the following problems.
First, when the opening 84a of the protective film 84 of the fuse element 97 is formed inside the opening 99a of the interlayer insulating film 99 and the opening 99a is deep, the opening 84a of the protective film 84 is formed with high accuracy. Therefore, it is necessary to enlarge the opening 99a of the interlayer insulating film 99 with a margin. Normally, the fuse element 97 is rarely used alone (single) and is composed of a large number of elements, so that a large number of openings 99a of the interlayer insulating film 99 are formed, increasing the chip area. It will be.

  Second, the opening area of the opening 84a of the protective film 84 on the fuse element 97 is typically as small as about 10 μm □, and the thickness of the interlayer insulating film is increased as the number of metal wiring layers increases. . Therefore, the depth of the opening 84a of the protective film 84 is increased, and the aspect ratio of this opening is increased. By increasing the aspect ratio, it becomes more difficult to stably process the bottom of the opening (dent). In the figure, 95 is an insulating film, 96 is a lower interlayer insulating film, 98 is a lower metal wiring layer, 100 is an upper metal wiring layer, and 101 is a stopper film.

Further, Patent Document 4 discloses that the sidewall is covered with a silicon nitride film in order to prevent moisture from entering from the sidewall of the opening of the interlayer insulating film, which is a silicon oxide film on the fuse element.
JP 2001-135792 A JP-A-8-46048 JP-A-8-288394 JP-A-7-130845

  As described above, in the first conventional example, the increase in the thickness of the interlayer insulating film (silicon oxide film) accompanying the increase in the number of metal layers results in the divergence of thermal energy generated during laser trimming (blowout) of the fuse element. Since it becomes difficult to perform instantaneously, internal stress is accumulated. Further, the fusing impact of the fuse element propagates in all directions in the interlayer insulating film. This accumulated internal stress and propagation of impact cause crack propagation not only to the upper interlayer insulating film but also to the interlayer insulating film around the fuse element. Propagation of this crack causes destruction of adjacent fuse elements, failure of circuit constituent elements, moisture intrusion, and the like from this crack, leading to a decrease in reliability of the semiconductor device.

  In the second conventional example, the thickness of the remaining film of the interlayer insulating film on the fuse element can be reduced. However, when the number of metal wiring layers increases, the opening of the interlayer insulating film on the fuse element is increased. As a result of the remarkably large depth (depth of the dent), a problem in processing a circuit pattern adjacent to the fuse element (circuit pattern of circuit constituent elements such as electrodes and wiring) occurs. There is a restriction on the pattern arrangement, which increases the chip area.

  In addition, in the recess of the interlayer insulating film on the fuse element, metal wiring residue is likely to be generated along the bottom of the recess. If this metal residue is peeled off during the process and becomes a foreign substance, an electrical short circuit between metal wiring layers or a defect in the circuit pattern occurs.

  Further, in the opening of the interlayer insulating film on the fuse element, the side wall of the opening is exposed. Intrusion of moisture or the like from this exposed part causes peeling of the interlayer insulating film or a circuit adjacent to the fuse element. This causes a problem that the long-term reliability of the component is lowered.

  In the third conventional example, since a protective film made of a silicon nitride film is formed on the side wall of the opening, entry of moisture and the like is prevented, and the circuit component element adjacent to the peeling of the interlayer insulating film and the fuse element The problem of lowering long-term reliability is avoided. However, since the opening of the protective film is disposed inside the opening of the interlayer insulating film on the fuse element, if an attempt is made to secure the opening size of the protective film to a required size, the opening of the interlayer insulating film The size of the part becomes larger than necessary, causing an increase in chip area.

  Furthermore, as the number of metal wiring layers increases, the interlayer insulating film becomes thicker, the depth of the opening of the interlayer insulating film on the fuse element increases, and the aspect ratio increases, so the bottom of the opening is precisely It becomes difficult to process.

  Further, in Patent Document 4, the introduction of moisture is prevented by covering the sidewall of the opening of the interlayer insulating film, which is a silicon oxide film on the fuse element, with a protective film that is a silicon nitride film that hardly absorbs moisture. . However, since the side wall of the opening of the interlayer insulating film is covered with the protective film, the opening of the interlayer insulating film needs to be larger than the opening of the protective film, and the chip area is large as in Patent Document 3. Become.

  The object of the present invention is to solve the above-mentioned problems, and when fusing a fuse element arranged in a semiconductor device with a laser beam, the fuse element can be surely blown without increasing the chip area. An object of the present invention is to provide a semiconductor device capable of improving the reliability of circuit components and the like disposed in the semiconductor device and a method for manufacturing the same.

In order to achieve the above object, according to the first aspect of the present invention, a step of forming a fuse element on a semiconductor substrate via an insulating film, and the fuse element and the insulating film are formed. Forming a lowermost interlayer insulating film on the lowermost layer, forming a lowermost wiring layer on the lowermost interlayer insulating film, on the lowermost interlayer insulating film and on the lowermost wiring layer A step of forming at least one stacked layer in which an interlayer insulating film and a wiring layer are sequentially stacked ; and a step of connecting the uppermost wiring layer and the lower wiring layer disposed above and below the uppermost interlayer insulating film. Forming a second opening in at least the uppermost interlayer insulating film on the fuse element simultaneously with forming the first opening, and electrically connecting the lower wiring layer to the first opening through the first opening; Forming the uppermost wiring layer, and the uppermost layer A step of covering a protective film over the interlayer insulating film, the uppermost wiring layer, and the second opening, and a third opening reaching the uppermost wiring layer on the protective film by dry etching and simultaneously forming said fuse element and said protective film in the second opening of the bottom portion and the second you adjacent opening the reach uppermost interlayer insulating film and the second opening is larger than the fourth opening on the Forming a part of the protective film on the side wall of the second opening, and a method of manufacturing a semiconductor device.

  According to the second aspect of the present invention, in the first aspect, the size of the fourth opening is the size of the opening of the mask pattern for forming the second opening. 1 μm or more is preferable.

According to a third aspect of the present invention, in the first aspect, the fuse element may be formed of polysilicon.
According to the fourth aspect of the present invention, in the first aspect, the interlayer insulating film from the lowermost layer to the uppermost layer may be a silicon oxide film.

According to the invention described in claim 5 of the claims, in the invention described in claim 1, the protective film may be a silicon nitride film.
According to the sixth aspect of the present invention, in the invention according to any one of the first to fifth aspects, the lower wiring layer may be the lowermost wiring layer.
According to a seventh aspect of the present invention, in the invention according to any one of the first to sixth aspects, in the step of covering the protective film, the protective film is the second opening. It is good to coat | cover so that it may have a recessed part on it.
According to invention of Claim 8, the fuse element arrange | positioned on the insulating film on a semiconductor substrate, The lowermost interlayer insulating film arrange | positioned on this fuse element and the said insulating film, A lowermost wiring layer disposed on the lowermost interlayer insulating film; an uppermost interlayer insulating film disposed on the lowermost wiring layer and on the lowermost interlayer insulating film; and A first opening in the uppermost layer that is disposed in the upper interlayer insulating film and reaches a lower wiring layer disposed immediately below the uppermost interlayer insulating film; and the uppermost interlayer insulating on the fuse element A second opening disposed in the film; an uppermost wiring layer disposed on the uppermost interlayer insulating film and electrically connected to the lower wiring layer through the first opening; A protective film disposed on the uppermost wiring layer and on the uppermost interlayer insulating film; An opening reaching the uppermost metal wiring layer; an opening reaching the second opening on the fuse element and reaching the uppermost interlayer insulating film adjacent to the second opening; A semiconductor device having a configuration in which a spacer-like protective film separated from the protective film on the uppermost interlayer insulating film by a part of the protective film is provided on a side wall of the two openings.

  According to the present invention, first, an opening (through hole) is formed in the uppermost interlayer insulating film, and at the same time, the uppermost interlayer insulating film on the fuse element is opened. A recess structure is formed in the interlayer insulating film. As a result, since the interlayer insulating film on the fuse element is partially thinned, the thermal energy generated during laser trimming is preferentially dissipated through this recessed region, and propagation to other regions in the lateral direction is reduced. . As a result, the propagation of cracks in the lateral direction in the peripheral area of the dent is reduced.

  Also, by forming an opening in the uppermost interlayer insulating film on the fuse element, the thickness of the interlayer insulating film on the fuse element is reduced, and the impact due to fusing of the fuse element that occurs during trimming is reduced. It is possible to suppress the phenomenon in which cracks propagate to the peripheral region by concentrating on the portion of the interlayer insulating film. By these, the unfused fuse element adjacent to the fused fuse element will not be destroyed, the crack will not propagate to the interlayer insulating film around the fuse element region, and moisture intrusion is prevented, The reliability of the circuit components in the peripheral region can be improved.

  Second, the fabrication of processing the circuit pattern adjacent to the fuse element region by setting the depth of the opening of the interlayer insulating film on the fuse element to the thickness of the uppermost interlayer insulating film (1 μm to 2 μm). The above problems can be reduced.

  Third, when the uppermost wiring pattern is formed, the metal residue remaining along the bottom (periphery) of the recess (opening) where the interlayer insulating film in the fuse element region is opened is separated from the spacer on the side wall of the opening. Since the structure is covered with the protective film remaining in the shape and the metal residue is confined by the protective film, there is no problem that it is peeled off in the subsequent process and becomes a foreign substance. Further, since the spacer-like protective film remains at the time of anisotropic etching of the protective film covering the surface, no special additional process is required, and therefore the manufacturing cost does not increase.

  Fourth, since a spacer-like protective film made of a silicon nitride film remains on the side wall of the opened interlayer insulating film on the fuse element, it is possible to prevent intrusion of moisture and the like. As a result, the circuit components around the fuse element region can improve long-term reliability.

Further, since the spacer-like protective film is thin and remains on the side wall of the interlayer insulating film, it is not necessary to widen the opening of the interlayer insulating film, and the chip area is not increased.
Fifth, since the opening of the protective film on the fuse element is made larger than the opening of the interlayer insulating film (preferably 1 μm or more), the protective film can be opened at a flat portion of the interlayer insulating film. The opening can be processed stably.

It is principal part manufacturing process sectional drawing of 1st Example of this invention. FIG. 2 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 1; FIG. 3 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 2; FIG. 4 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the first embodiment of the invention, following FIG. 3; FIG. 5 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 4. FIG. 6 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 5. FIG. 7 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 6; FIG. 8 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 7. FIG. 9 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 8; FIG. 10 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 9; FIG. 11 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 10; FIG. 12 is a main-portion manufacturing process sectional view of the semiconductor device according to the first embodiment of the invention, following FIG. 11; FIG. 13 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 12; FIG. 14 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 13; FIG. 15 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 14; It is principal part manufacturing process sectional drawing of the semiconductor device of 2nd Example of this invention. FIG. 17 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 16; FIG. 18 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 17; FIG. 19 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 18; FIG. 20 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 19; FIG. 21 is a main-portion manufacturing process sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 20; FIG. 22 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 21. FIG. 23 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 22; FIG. 24 is a main-portion manufacturing step cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 23; FIG. 25 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 24; FIG. 26 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 25; FIG. 27 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 26; FIG. 28 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 27; FIG. 29 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 28; FIG. 29 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 29. 30 is a fragmentary manufacturing process sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 30; FIG. 32 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 31; FIG. 33 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 32; FIG. 34 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 33; Cross-sectional view of relevant parts showing how a spacer-like protective film is formed The figure explaining the effect of this invention Cross-sectional view of the main part of another part where the three-layer metal wiring layer is formed It is a principal part top view of the fuse element arrange | positioned at the semiconductor device which is a 1st prior art example. It is principal part sectional drawing cut | disconnected by the XX line of FIG. 38, and is a figure explaining a subject. It is principal part sectional drawing of the fuse element area | region for every process in a 2nd prior art example. It is principal part sectional drawing of the fuse element for every process in a 3rd prior art example (patent document 2).

  Embodiments will be described in the following examples.

  FIG. 1 to FIG. 15 are cross-sectional views showing a main part manufacturing process showing the semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps. This embodiment is a case where there are two metal wiring layers, and this figure is a cross-sectional view of an essential part of a portion where a fuse element and a pad electrode (bonding pad) are formed.

An insulating film 2 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1, and a fuse element 3 made of, for example, polysilicon is further formed thereon (FIG. 1).
Next, a first interlayer insulating film 4 made of, for example, a silicon oxide film is formed over the entire surface (FIG. 2).

  Next, a contact hole electrically connected to the semiconductor substrate 1 is formed at a location (not shown) of the first interlayer insulating film 4, and then a first metal wiring layer 5 made of, for example, an aluminum wiring layer is formed. (Figure 3).

Next, for example, a second interlayer insulating film 6 made of a silicon oxide film is formed over the entire surface (FIG. 4).
Next, a resist pattern 7 having an opening 8 on the first metal wiring layer 5 and an opening 9 on the fuse element 3 is formed on the second interlayer insulating film 6 (FIG. 5).

  Next, using the resist pattern 7 as a mask, for example, dry etching is performed to form a through hole 10 that is electrically connected to the first metal wiring layer 5. At this time, an opening 11 is formed in the second interlayer insulating film 6 on the fuse element 3 simultaneously with the formation of the through hole 10 (FIG. 6). Thereby, since the interlayer insulating film of the opening 11 becomes thinner than the peripheral portion, the heat energy generated at the time of fusing of the fuse element is preferentially dissipated through the opening 11 to the peripheral region of the fuse element 3. Propagation of thermal energy is suppressed. In addition, an impact generated when the fuse element 3 is blown by the power of the laser beam is also preferentially released by the opening 11 having a thin and fragile interlayer insulating film, thereby suppressing crack propagation to the peripheral region. be able to. That is, by forming the opening 11, thermal energy and impact can be concentrated on the opening 11. The opening 11 penetrates through the second interlayer insulating film 6 and reaches the first interlayer insulating film 4. The opening 11 forms an interlayer insulating film 6 a that is a combination of the first interlayer insulating film 4 and the second interlayer insulating film 6. A recess 12 is formed. A bottom portion 13 of the recess 12 is formed in the first interlayer insulating film 4. The bottom 13 may be positioned at the interface 14 between the first interlayer insulating film 4 and the second interlayer insulating film 6. Further, the bottom 13 may be positioned in the middle of the second interlayer insulating film 6.

Next, the resist pattern 7 is removed (FIG. 7).
Next, for example, a metal film 15 such as an aluminum film is formed on the entire surface by sputtering or the like, and is electrically connected to the lower first metal wiring layer 5 through the through hole 10 (FIG. 8). At this time, the metal film 15 may be electrically connected to the lower first metal wiring layer 5 through the through hole 10, or may be connected to the first metal wiring layer 5 through the through hole at a location not shown. You may connect.

Next, a resist pattern 16 is formed on the metal film 15 (FIG. 9).
Next, using the resist pattern 16 as a mask, for example, by dry etching, the metal film 15 is processed to form second metal wiring layers 17 and 18 (FIG. 10). At this time, the metal film 15 in the opening 11 on the fuse element 3 is preferably completely removed by etching, but the metal residue 19 remains along the flange 20 (outer edge of the bottom) of the bottom 13 of the opening 11. Sometimes.

Next, the resist pattern 16 is removed (FIG. 11).
Next, a protective film 21 made of, for example, a silicon nitride film is formed over the entire surface (FIG. 12). As a result, the metal residue 19 is covered with the protective film 21.

  Next, a resist pattern 22 is formed on the protective film 21, and an opening 23 and an opening 24 are formed in the resist pattern 22 on the second metal wiring layer 17 and the fuse element 3. The opening of the protective film 21 on the second metal wiring layer 17 is made through the opening 23 of the resist pattern 22, and the opening of the protective film 21 on the fuse element 3 is made through the opening 24 of the resist pattern 22 (FIG. 13). At this time, the size W2 of the opening 24 is made larger than the size W1 of the opening of the recess 12 (the size of the opening 11 of the second interlayer insulating film 6). W1 is preferably set to 1 μm or more from W2 in consideration of processing variations and the like.

  Next, using the resist pattern 22 as a mask, for example, dry etching is performed to form openings 25 and 26 in the protective film 21 (FIG. 14). As a result, the second metal wiring layer 18 is exposed in the opening 25 of the resist pattern 22 to form a bonding pad region (pad electrode).

  On the other hand, the protective film 21 on the fuse element 3 is also removed in this process, but as a result of performing dry etching in a state where the opening 24 of the resist 22 is opened larger than the opening 11, the side wall 27 of the recess 12 is obtained. A spacer-like protective film 28 is formed (a part of the protective film 21 remains in a spacer shape). In this dry etching, anisotropic etching is more preferable than isotropic etching in order to leave the spacer-like protective film 28. Wet etching is not preferable because it is difficult to leave the spacer-like protective film 28.

  FIG. 35 shows how the spacer-like protective film 28 is formed on the side wall of the recess by dry etching. In the case of a dent, the thickness of the protective film is thicker than the flat part due to the geometric shape. In addition, in the case of dry etching, the etching gas is difficult to enter into the dent, so that the protective film 21 remains on the side wall of the dent (particularly the ridge of the dent) to form a spacer-like protective film 28. In forming the spacer-like protective film 28, a resist pattern is not necessary.

Finally, the resist pattern 22 is removed to complete a semiconductor device having the fuse element 3 and the metal wiring layers 5, 17, and 18 (FIG. 15).
With respect to the semiconductor device thus manufactured, the points of the invention will be described with reference to FIG.

FIG. 36 is an enlarged view of the vicinity of the fuse element 3 of the semiconductor device (FIG. 15) of the present invention.
The thickness T1 of the interlayer insulating film 4 below the recess 12 formed on the fuse element 3 is equal to the thickness T2 of the interlayer insulating film 4 where the recess 12 is not formed in the area around the fuse element 3 (first and second interlayers). Since the thickness of the interlayer insulating film 6a including the insulating films 4 and 6 is smaller than the thickness T2), the thermal energy generated when the fuse element is blown preferentially dissipates through the opening 11, and the peripheral area of the fuse element 3 Propagation of thermal energy to is suppressed.

  Further, in the interlayer insulating film 4 on the fuse element 3, the thickness of the interlayer insulating film 4 above the fuse element 3 is reduced by forming the opening 11 (recess 12). The impact 29 generated when the fuse element 3 is melted by the power of the laser light is preferentially released at the dent 12 portion, so that crack propagation to the peripheral region is suppressed. That is, by forming the opening 11, thermal energy and impact 29 can be concentrated on the opening 11.

  As a result, the crack 30 generated in the interlayer insulating film 4 is suppressed from propagating to the peripheral region of the fuse element 3, an adjacent fuse element (not shown) is destroyed, or moisture enters from the crack 30 of the interlayer insulating film 4. Is prevented from occurring. As a result, it is possible to improve the reliability of the circuit constituent element formed in the peripheral region of the blown fuse element and the reliability of the adjacent unfused fuse element.

  Further, by forming the spacer-like protective film 28 on the side wall 27 of the recess 12, moisture can be prevented from entering from the side wall 27 of the interlayer insulating film 6, and the circuit constituent element formed in the peripheral region of the fuse element 3 It is possible to improve the reliability.

  Further, since the metal residue 19 is covered with the spacer-like protective film 28, the metal residue 19 remains covered with the protective film 21 without being exposed during the dry etching process. It is not exposed and the generation of foreign matter due to peeling or the like can be avoided. In addition, since the metal residue 19 is confined by the spacer-like protective film 28, even when heat treatment is performed in a later process, it is possible to avoid a problem that is caused by peeling due to stress or the like and resulting in generation of foreign matter. .

Further, the spacer-like protective film 28 is formed at the same time when the opening 26 is formed in the protective film 21, and no additional process is required, so that the manufacturing cost does not increase.
In the formation of the spacer-like protective film 28, when a resist pattern is used, it is necessary to make an opening at the bottom surface of the opening 11 of the interlayer insulating film 6 where the resist film thickness variation due to the step is reduced. Since the position of the spacer-like protective film 28 is determined by the resist pattern at the bottom of the part 11, dimensional accuracy is required.

  However, in the present invention, if the protective film 21 is opened larger than the opening 11 of the interlayer insulating film 6, the spacer-shaped protective film 28 remains without being affected by the resist pattern, and the interlayer insulating film 6. Protect the side wall 27. That is, since a resist pattern for forming the spacer-like protective film 28 is not necessary, the resist pattern is not subjected to layout restrictions.

  In the present invention, the formation of the spacer-like protective film 28 does not use a resist pattern. Therefore, the thickness from the side wall 27 is smaller than that when the resist pattern is used, and the opening 28a of the spacer-like protective film 28 is It becomes larger than the case where it is formed using a resist pattern.

  Therefore, in the case where the openings 28a of the spacer-like protective film 28 are made the same size, compared with the case where the spacer-like protective film 28 is formed using a resist pattern, the present invention is formed without a resist pattern. In this case, the opening 11 of the interlayer insulating film 6 can be made smaller.

  From the above, in the semiconductor device of the present invention, the fuse element can be surely blown without increasing the chip area, and the reliability of the circuit components disposed around the fuse element can be improved.

  The present invention can also be applied to highly accurate trimming of a thin film resistor formed of CrSi, and the effect is the same as that of the fuse element 3.

  16 to 34 are cross-sectional views showing a main part manufacturing process showing the semiconductor device manufacturing method according to the second embodiment of the present invention in the order of processes. This is a case where there are three metal wiring layers. Here, description of the same steps (FIGS. 1 to 4) as those of the first embodiment is omitted, and steps different from those of the first embodiment following FIG. 4 will be described.

Subsequent to the step of FIG. 4, a resist pattern 7 having an opening 8 is formed on the second interlayer insulating film 24 (FIG. 16).
Next, through holes 10 are formed on the first metal wiring layer 5 by performing, for example, dry etching using the resist pattern 7 as a mask (FIG. 17).

Next, the resist pattern 7 is removed (FIG. 18).
Next, a metal film 15 to be the second metal wiring layer 17 is formed on the entire surface by, for example, sputtering, and is electrically connected to the lower first metal wiring layer 5 through the through hole 10. (FIG. 19). At this time, the metal film 15 may be connected to the first metal wiring layer 5 through a through hole at a location not shown.

Next, a resist pattern 16 is formed on the metal film 15 (FIG. 20).
Next, using the resist pattern 16 as a mask, for example, dry etching is performed to form the second metal wiring layer 17 (FIG. 21).

Next, the resist pattern 16 is removed (FIG. 22).
Next, a third interlayer insulating film 31 is formed over the entire surface (FIG. 23).
Next, a resist pattern 32 having an opening 33 and an opening 34 is formed on the third interlayer insulating film 31 (FIG. 24).

  Next, through holes 35 are formed in the second interlayer insulating film 31 on the second metal wiring layer 17 by performing dry etching using the resist pattern 32 as a mask. At this time, an opening 36 is formed in the second interlayer insulating film 31 on the fuse element 3 simultaneously with the formation of the through hole 35 (FIG. 25).

Next, the resist pattern 32 is removed (FIG. 26).
Next, a metal film 40 to be a third metal wiring layer is formed on the entire surface by, for example, sputtering, and is electrically connected to the lower second metal wiring layer 17 through the through hole 35 ( FIG. 27).

Next, a resist pattern 41 is formed on the metal film 40 (FIG. 28).
Next, using the resist pattern 41 as a mask, for example, by dry etching, the metal film 41 is processed to form third metal wiring layers 42 and 43 (the second metal wiring layer 43 serves as a pad electrode). Then, the metal film 41 on the fuse element 3 is removed (FIG. 29). At this time, the metal film 41 in the opening 36 on the fuse element 3 is preferably completely removed by etching, but the metal residue 44 often remains along the ridge 45 (outer periphery) of the bottom of the recess 37. . The third metal wiring layer 42 is electrically connected to the lower second metal wiring layer 17 through the through hole 35.

Next, the resist pattern 41 is removed (FIG. 30).
Next, a protective film 46 mainly made of a silicon nitride film is formed over the entire surface (FIG. 31). As a result, the metal residue 44 is covered with the protective film 46.

  Next, a resist pattern 47 having an opening 48 and an opening 49 is formed on the protective film 46 (FIG. 32). At this time, the size W2 of the opening 49 of the resist pattern 47 is processed larger than the size W1 of the opening 36 of the third interlayer insulating film 31 (the uppermost interlayer insulating film). The size W2 is preferably larger than W1 by 1 μm or more in consideration of processing variations and the like.

  Next, using the resist pattern 47 as a mask, for example, dry etching is performed to form the opening 50 and the opening 51 in the protective film 46 (FIG. 33). As a result, the surface of the third metal wiring layer 43 (pad electrode) is exposed under the opening 48 of the resist pattern 47, and a bonding pad region is formed.

  On the other hand, although the protective film 47 on the fuse element 3 is also removed at the same time, dry etching is performed in a state where the opening 49 of the resist pattern 47 is larger than the opening 36 of the third interlayer insulating film 31. A spacer-like protective film 52 is formed on the side wall 37 a of the 36 (dent 37) to cover the metal residue 44.

Next, the resist pattern 47 is removed to complete a semiconductor device having the fuse element 3 and the metal wiring layers 5, 17, 42, and 43 (FIG. 34).
This is a case of three layers. Even when the number of layers is further increased, an opening is simultaneously formed in the uppermost interlayer insulating film on the fuse element in the step of forming a through hole in the uppermost interlayer insulating film. Thus, the same effect as in the first embodiment can be obtained.

  In the first embodiment and the second embodiment, the depth of the opening (dent) of the interlayer insulating film on the fuse element is set to the thickness of the uppermost interlayer insulating film (usually 1 μm to 2 μm). By doing so, the depth of the dent can be made shallower, and it is possible to reduce problems in forming a circuit component element adjacent to the fuse element. This defect is that the resist enters the opening and the resist thickness around the opening is reduced.

The uppermost interlayer insulating film is the second interlayer insulating film in the first embodiment, the third interlayer insulating film in the second embodiment, and the uppermost interlayer insulating film in the case of multiple layers. It is a membrane.
That is, in the present invention, the recess of the interlayer insulating film on the fuse element 21 is performed only when a through hole is formed in the uppermost interlayer insulating film, so that the step of the recess is small, which gives workability in the photolithography process. The impact is small.

  On the other hand, as described in Patent Document 1 of the second conventional example, every time the through hole is formed, when the opening on the fuse element is formed in the through hole forming process every time the interlayer insulating film is formed. In addition, workability such as a photolithography process is affected, and design restrictions are imposed. Furthermore, every time a through hole is opened in the interlayer insulating film, the concave steps are integrated and the steps become large, so that the processing such as the photolithography process in the final process becomes very difficult.

  Usually, silicon oxide film-based materials are mainly used as the material constituting the interlayer insulating film, and since this material is optically transparent, the openings on the fuse elements are passed through as in the conventional example. It is not necessary to make the interlayer insulating film thin by performing each time a hole is formed.

  According to the present invention, when a silicon oxide film-based material is used as the interlayer insulating film, the thickness is not limited because it is optically transparent. The thickness restriction is rather from the viewpoint of heat dissipation and from the viewpoint of releasing the impact when the fuse element is blown. Therefore, it is only necessary to suppress the propagation in the lateral direction by releasing the impact from the thin portion above the interlayer insulating film so that the uppermost interlayer insulating film on the fuse element is slightly thinner than the peripheral interlayer insulating film. .

Therefore, as in the present invention, by providing an opening (dent) in the uppermost interlayer insulating film on the fuse element, the impact can be released from a thin portion above the interlayer insulating film.
Further, by forming a recess of about 1 μm to 2 μm in the interlayer insulating film on the fuse element, it is possible to release the impact caused by the fusing of the fuse element from the position of the recess. By releasing the impact from the recess, the propagation of cracks to the circuit components around the fuse element can be prevented, and the reliability can be improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Fuse element 4 1st interlayer insulating film 5 1st metal wiring layer 6 2nd interlayer insulating film 7 Resist pattern 8, 9, 11, 23, 24, 25, 26 Opening 10 Through Hole 12 Depression 13 Bottom 14 Boundary 15 Metal film 16 Resist pattern 17, 18 Second metal wiring layer 19 Metal residue 20 Bottom ridge 21 Protective film 22 Resist pattern 27 Side wall 28 Spacer-shaped protective film

Claims (9)

Forming a fuse element on a semiconductor substrate via an insulating film; forming a lowermost interlayer insulating film on the fuse element and on the insulating film; and forming a lowermost layer on the lowermost interlayer insulating film Forming a wiring layer on the lowermost layer, forming a laminated layer in which an interlayer insulating film and a wiring layer are sequentially laminated on the lowermost interlayer insulating film and the lowermost wiring layer; and A first opening is formed to connect the uppermost wiring layer disposed above and below the interlayer insulating film and a lower wiring layer, and at the same time, a second opening is formed in at least the uppermost interlayer insulating film on the fuse element. Forming a top portion, forming a top wiring layer electrically connected to the lower wiring layer through the first opening, over the top interlayer insulating film, and A protective film is applied over the upper wiring layer and the second opening. Forming a third opening reaching the uppermost wiring layer in the protective film by dry etching, and simultaneously forming a bottom of the second opening and the second opening in the protective film on the fuse element. step to leave a portion of said second opening is larger than the fourth openings are formed in the dry etching, the protective film on the sidewall of the second opening reaching said uppermost interlayer insulating film you adjacent A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the size of the fourth opening is 1 μm or more larger than the size of the opening of the mask pattern for forming the second opening. The method for manufacturing a semiconductor device according to claim 1, wherein the fuse element is formed of polysilicon. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film from the lowermost layer to the uppermost layer is a silicon oxide film. The method of manufacturing a semiconductor device according to claim 1, wherein the protective film is a silicon nitride film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the lower wiring layer is the lowermost wiring layer. 7. The semiconductor device according to claim 1, wherein in the step of covering the protective film, the protective film is covered so as to have a recess on the second opening. Production method. A fuse element disposed on an insulating film on a semiconductor substrate; a lowermost interlayer insulating film disposed on the fuse element and on the insulating film; and a lowermost layer disposed on the lowermost interlayer insulating film A wiring layer, an uppermost interlayer insulating film disposed on the lowermost wiring layer and the lowermost interlayer insulating film, and an uppermost interlayer insulating film disposed on the uppermost interlayer insulating film. A first opening reaching a lower wiring layer disposed below the film; a second opening disposed in the uppermost interlayer insulating film on the fuse element; and the uppermost interlayer insulating film An uppermost wiring layer disposed on and electrically connected to the lower wiring layer through the first opening, and disposed on the uppermost wiring layer and on the uppermost interlayer insulating film; And a protective film
  An opening where the protective film reaches the uppermost metal wiring layer; and an opening which reaches the second opening on the fuse element and reaches the uppermost interlayer insulating film adjacent to the second opening. And a spacer-like protective film separated from the protective film on the uppermost interlayer insulating film by a part of the protective film on a side wall of the second opening. 9. The semiconductor device according to claim 8, wherein a lower wiring layer disposed below the uppermost interlayer insulating film is the lowermost wiring layer.

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