JPH0350756A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH0350756A JPH0350756A JP1186721A JP18672189A JPH0350756A JP H0350756 A JPH0350756 A JP H0350756A JP 1186721 A JP1186721 A JP 1186721A JP 18672189 A JP18672189 A JP 18672189A JP H0350756 A JPH0350756 A JP H0350756A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- fuse
- barrier metal
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 27
- 229920005591 polysilicon Polymers 0.000 abstract description 27
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010936 titanium Substances 0.000 abstract description 8
- 229910052719 titanium Inorganic materials 0.000 abstract description 8
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract description 5
- 238000002844 melting Methods 0.000 abstract description 5
- 230000008018 melting Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は冗長回路を有する半導体集積回路の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit having a redundant circuit.
近年ますます半導体集積回路の微細化、高集積化が進み
歩留りに与える欠陥密度の影響が無視できなくなってき
ている。In recent years, semiconductor integrated circuits have become increasingly finer and more highly integrated, and the influence of defect density on yield cannot be ignored.
そのためＬＭ−ＤＲＡＭなどで、メモリセルの行列にス
ペアの行や列を準備して置き替える冗長回路が搭載され
ている。For this reason, LM-DRAMs and the like are equipped with a redundant circuit that prepares and replaces spare rows and columns in the matrix of memory cells.
スペアの行や列の置き替えは、ポリシリコン膜などで形
成したヒユーズをレーザーで切断する方法が一最的であ
る。The best way to replace spare rows and columns is to cut fuses made of polysilicon film or the like using a laser.
従来技術における冗長回路用ヒユーズの製造方法につい
て、第３図（ａ）〜（０）を参照して説明する。A conventional method of manufacturing a redundant circuit fuse will be described with reference to FIGS. 3(a) to 3(0).
はじめに第３図（ａ＞に示すように、半導体基板１の表
面に素子領域２を形成し、全面に第１の絶縁膜３を堆積
してから、第１の開口窓を形成して素子領域２の一部を
露出させる。First, as shown in FIG. 3 (a), an element region 2 is formed on the surface of a semiconductor substrate 1, a first insulating film 3 is deposited on the entire surface, and a first opening window is formed to form an element region 2. Expose part of 2.
つぎに第３図（ｂ）に示すように、選択的にポリシリコ
ン膜を堆積してから全面に第゛２の絶縁膜６を堆積し、
選択的に第２の開口窓を設け、ポリシリコン電極４とポ
リシリコンヒユーズ５の両端部の表面を露出させる。Next, as shown in FIG. 3(b), after selectively depositing a polysilicon film, a second insulating film 6 is deposited on the entire surface.
A second opening window is selectively provided to expose the surfaces of both ends of polysilicon electrode 4 and polysilicon fuse 5.
さらに白金などの金属を被着させてから、約５００℃で
熱処理して第２の開口窓のポリシリコン表面に白金シリ
サイド層７を形成する。Furthermore, after depositing a metal such as platinum, heat treatment is performed at approximately 500° C. to form a platinum silicide layer 7 on the polysilicon surface of the second opening window.
そのあと第３図（ｃ）に示すように、第２の開口窓を覆
うようにチタンなどの高融点金属を選択的に形成して、
バリア金属膜８とする。Thereafter, as shown in FIG. 3(c), a high melting point metal such as titanium is selectively formed to cover the second opening window.
A barrier metal film 8 is used.
つぎにアルミニウムからなる電極または配線９を形成し
てから全面に第３の絶縁膜１０を形成する。Next, an electrode or wiring 9 made of aluminum is formed, and then a third insulating film 10 is formed on the entire surface.
最後に第３の絶縁膜１０に第３の開口窓を設けて完成す
る。Finally, a third opening window is provided in the third insulating film 10 to complete the process.
従来の半導体集積回路では、第３図（ｃ）に示すように
、ポリシリコンヒユーズ５の直上には第２の絶縁膜６と
第３の絶縁膜１０とが堆積されている。In a conventional semiconductor integrated circuit, a second insulating film 6 and a third insulating film 10 are deposited directly above the polysilicon fuse 5, as shown in FIG. 3(c).
第２の絶縁膜の膜厚は１．０μｍ、第３の絶縁膜の膜圧
は１．５μｍあるので、ポリシリコンヒユーズ直上には
合せて２．５μｍの絶縁膜が堆積されていることになる
。The thickness of the second insulating film is 1.0 μm, and the thickness of the third insulating film is 1.5 μm, so a total of 2.5 μm of insulating film is deposited directly above the polysilicon fuse. .
冗長回路を使用するときはレーザービームにより、選択
的に第３の絶縁膜１０、第２の絶縁膜６およびポリシリ
コンヒユーズ５を溶断して冗長回路を動作させる。When the redundant circuit is used, the third insulating film 10, the second insulating film 6, and the polysilicon fuse 5 are selectively fused with a laser beam to operate the redundant circuit.
このときポリシリコンヒユーズ直上の絶縁膜の膜厚が厚
いため、溶断てきないで冗長回路が動作しないことが多
く、半導体集積回路の歩留り低下の原因となっていた。At this time, since the insulating film directly above the polysilicon fuse is thick, the redundant circuit often does not operate because it does not blow out, which causes a decrease in the yield of semiconductor integrated circuits.
その対策として第４図に示すように、ポリシリコンヒユ
ーズ直上の絶縁膜の一部を除去して薄くする方法がある
。As a countermeasure to this problem, as shown in FIG. 4, there is a method of removing a portion of the insulating film directly above the polysilicon fuse to make it thinner.
こうすればレーザービームで正確に溶断てきるようにな
るが、ポリシリコンヒユーズ直上の絶縁膜のエツチング
の制御が困難で、ポリシリコンヒユーズ表面が露出して
破損することがあった。This allows for accurate fusing with a laser beam, but it is difficult to control the etching of the insulating film directly above the polysilicon fuse, and the surface of the polysilicon fuse may be exposed and damaged.
いずれにしても冗長回路が半導体集積回路の歩留り低下
の大きな原因となっていた。In any case, redundant circuits have been a major cause of lower yields of semiconductor integrated circuits.
本発明の半導体集積回路の製造方法は、半導体基板表面
に第１の絶縁膜を形成したのち、冗長回路のヒユーズと
して半導体または金属からなる導電体膜を選択的に形成
する工程、前記ヒユーズを含む前記半導体基板全面に第
２の絶縁膜を形成してから選択的に第１の開口窓を設け
、前記ヒユーズの一部を露出させる工程、前記開口窓お
よびその近傍を被覆するバリア金属膜を形成する工程、
半導体基板全面を覆う第３の絶縁膜を設けてから選択的
に第２の開口窓を設ける工程を有する半導体集積回路の
製造方法において、
前記バリア金属がヒユーズの両端の開口窓を覆う第１の
パターンとヒユーズ切断個所直上の第２の絶縁膜上を選
択的に覆う第２のパターンとを有していて、第３の絶縁
膜に第２の開口窓を形成する際に、前記第２のパターン
上にも開口窓を形成してバリア金属膜からなる第２のパ
ターンを除去するものである。The method for manufacturing a semiconductor integrated circuit of the present invention includes the step of forming a first insulating film on the surface of a semiconductor substrate, and then selectively forming a conductive film made of a semiconductor or metal as a fuse of a redundant circuit; forming a second insulating film over the entire surface of the semiconductor substrate, selectively providing a first opening window to expose a part of the fuse; forming a barrier metal film covering the opening window and its vicinity; The process of
A method for manufacturing a semiconductor integrated circuit comprising the steps of providing a third insulating film covering the entire surface of the semiconductor substrate and then selectively providing a second opening window, wherein the barrier metal covers the first opening window at both ends of the fuse. pattern and a second pattern that selectively covers the second insulating film directly above the fuse cutting point, and when forming the second opening window in the third insulating film, the second pattern An opening window is also formed on the pattern and the second pattern made of the barrier metal film is removed.
本発明の第１の実施例について、第１図（ａ）〜（ｃ）
を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (c)
Explain with reference to.
第３図（ｂ）のところまでは、従来の製造方法と同様で
ある。The process up to FIG. 3(b) is the same as the conventional manufacturing method.
そのあと第１図（ａ＞に示すように、第２の絶縁膜６の
第２の開口窓近傍とポリシリコンヒユーズ５の直上の第
２の絶縁膜６の上にバリア金属膜８を形成する。Thereafter, as shown in FIG. 1(a), a barrier metal film 8 is formed near the second opening window of the second insulating film 6 and on the second insulating film 6 directly above the polysilicon fuse 5. .
バリア金属膜８はチタンなどの高融点金属を用い、膜厚
は５００〜２０００μｍとした。The barrier metal film 8 was made of a high melting point metal such as titanium, and had a film thickness of 500 to 2000 μm.
つぎにアルミニウムなどの高導電率の金属膜を被着して
、電極または配線９を形成する。Next, a highly conductive metal film such as aluminum is deposited to form electrodes or wiring 9.
そのあと第１図（ｂ）に示すように、全面に第３の絶縁
膜１０を形成して、アルミニウム配線９の終端部および
ポリシリコンヒユーズ直上に設けたバリア金属上に開口
窓を設ける。Thereafter, as shown in FIG. 1(b), a third insulating film 10 is formed on the entire surface, and an opening window is provided on the barrier metal provided directly above the terminal end of the aluminum wiring 9 and the polysilicon fuse.
つぎに第１図（ｃ）に示すように、第３の絶縁膜をマス
クとして、過酸化水素水などを用いて、ポリシリコンヒ
ユーズ直上のチタンからなるバリア金属膜８を除去する
。Next, as shown in FIG. 1C, using the third insulating film as a mask, the barrier metal film 8 made of titanium directly above the polysilicon fuse is removed using hydrogen peroxide or the like.
つぎに本発明の第２の実施例について、第２図（ａ）〜
（ｃ）を参照して説明する。Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (c).
第３図（ｂ）のところまでは、従来の製造方法と同様で
ある。The process up to FIG. 3(b) is the same as the conventional manufacturing method.
そのあと第２図（ａ＞に示すように、第２の絶縁膜６の
第２の開口窓とポリシリコンヒユーズ５直上の第２の絶
縁膜上に、バリア金属膜８とアルミニウムからなる電極
または配線を形成する。Thereafter, as shown in FIG. 2(a), a barrier metal film 8 and an electrode made of aluminum or Form wiring.
そのあと第２図（ｂ）に示すように、第３の絶縁膜１０
を堆積し、配線コンタクトおよびポリシリコンヒユーズ
直上に開口窓を設けてから、全面にアルミニウムなどの
高導電率の金属膜を被着して、選択エツチングすること
により、第２のアルミニウム配線１１を形成する。Thereafter, as shown in FIG. 2(b), a third insulating film 10 is formed.
After forming an opening window directly above the wiring contact and the polysilicon fuse, a high conductivity metal film such as aluminum is deposited on the entire surface and selectively etched to form the second aluminum wiring 11. do.
このときポリシリコンヒユーズ５直上のアルミニウム膜
９も同時に除去でき、チタンからなるバリア金属ｙｌＡ
８が露出する。At this time, the aluminum film 9 directly above the polysilicon fuse 5 can also be removed at the same time, and the barrier metal ylA made of titanium can be removed.
8 is exposed.
最後に第２図（ｃ）に示すように、表面保護膜１２を形
成してから、表面保護膜１２をマスクとして過酸化水素
水に浸し、ポリシリコンヒユーズ直上のバリア金属膜８
を除去して完成する。Finally, as shown in FIG. 2(c), after forming the surface protective film 12, the barrier metal film 8 directly above the polysilicon fuse is immersed in hydrogen peroxide solution using the surface protective film 12 as a mask.
Complete by removing.
（発明の効果〕
本発明においては、ポリシリコンヒユーズ直上の絶縁膜
の上のチタンなどの高融点金属膜をエツチングのストッ
パーとしている。(Effects of the Invention) In the present invention, a high melting point metal film such as titanium on the insulating film directly above the polysilicon fuse is used as an etching stopper.
そのためポリシリコンヒユーズ直上の絶縁膜の膜厚を均
一に保つことができ、レーザービームによるヒユーズ切
断の制御が容易になり、半導体集積回路の歩留りの向上
が可能になった。As a result, the thickness of the insulating film directly above the polysilicon fuse can be kept uniform, making it easier to control fuse cutting with a laser beam, and making it possible to improve the yield of semiconductor integrated circuits.
第１図（ａ）〜（Ｃ）は本発明の第１の実施例の製造方
法を工程順に示す断面図、第２図（ａ）〜（ｃ）は本発
明の第２の実施例の製造方法を工程順に示す断面図、第
３図（ａ）〜（ｃ）は従来の製造方法を工程順に説明す
る断面図、第４図は従来の製造方法の他の例を示す断面
図である。
１・・・半導体基板、２・・・素子領域、３・・・第１
の絶縁膜、４・・・ポリシリコン電極、５・・・ポリシ
リコンヒユーズ、６・・・第２の絶縁膜、７・・・白金
シリサイド層、８・・・バリア金属膜、９・・・アルミ
ニウムからなる電極または配線、１０・・・第３の絶縁
膜、１１・・・第２のアルミニウム配線、１２・・・表
面保護膜。FIGS. 1(a) to (C) are cross-sectional views showing the manufacturing method of the first embodiment of the present invention in order of steps, and FIGS. 2(a) to (c) are sectional views showing the manufacturing method of the second embodiment of the present invention. 3(a) to 3(c) are sectional views illustrating a conventional manufacturing method in the order of steps, and FIG. 4 is a sectional view showing another example of the conventional manufacturing method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Element region, 3... First
4... Polysilicon electrode, 5... Polysilicon fuse, 6... Second insulating film, 7... Platinum silicide layer, 8... Barrier metal film, 9... Electrode or wiring made of aluminum, 10... Third insulating film, 11... Second aluminum wiring, 12... Surface protective film.
Claims (1)
路のヒューズとして半導体または金属からなる導電体膜
を選択的に形成する工程、前記ヒューズを含む前記半導
体基板全面に第２の絶縁膜を形成してから選択的に第１
の開口窓を設け、前記ヒューズの一部を露出させる工程
、前記開口窓およびその近傍を被覆するバリア金属膜を
形成する工程、半導体基板全面を覆う第３の絶縁膜を設
けてから選択的に第２の開口窓を設ける工程を有する半
導体集積回路の製造方法において、前記バリア金属がヒ
ューズの両端の開口窓を覆う第１のパターンとヒューズ
切断個所直上の第２の絶縁膜上を選択的に覆う第２のパ
ターンとを有していて、第３の絶縁膜に第２の開口窓を
形成する際に、前記第２のパターン上にも開口窓を形成
してバリア金属膜からなる第２のパターンを除去するこ
とを特徴とする半導体集積回路の製造方法。After forming a first insulating film on the surface of the semiconductor substrate, a step of selectively forming a conductive film made of semiconductor or metal as a fuse of a redundant circuit, and forming a second insulating film on the entire surface of the semiconductor substrate including the fuse. selectively after forming the first
a step of providing an opening window and exposing a part of the fuse; a step of forming a barrier metal film covering the opening window and its vicinity; and a step of forming a third insulating film covering the entire surface of the semiconductor substrate, and then selectively In the method of manufacturing a semiconductor integrated circuit, the method includes the step of providing a second opening window, wherein the barrier metal selectively covers the first pattern covering the opening windows at both ends of the fuse and the second insulating film immediately above the fuse cutting point. When forming a second opening window in the third insulating film, an opening window is also formed on the second pattern and a second pattern made of a barrier metal film is formed. 1. A method for manufacturing a semiconductor integrated circuit, comprising removing a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1186721A JPH0350756A (en) | 1989-07-18 | 1989-07-18 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1186721A JPH0350756A (en) | 1989-07-18 | 1989-07-18 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350756A true JPH0350756A (en) | 1991-03-05 |
Family
ID=16193475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1186721A Pending JPH0350756A (en) | 1989-07-18 | 1989-07-18 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350756A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0581867A1 (en) * | 1991-04-23 | 1994-02-09 | Harris Corporation | Method of laser trimming and resulting ic |
| WO1999019905A1 (en) * | 1997-10-13 | 1999-04-22 | Fujitsu Limited | Semiconductor device having fuse and fabrication method thereof |
| JP2011086863A (en) * | 2009-10-19 | 2011-04-28 | Fuji Electric Systems Co Ltd | Semiconductor device, and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6084838A (en) * | 1983-10-17 | 1985-05-14 | Hitachi Ltd | Manufacture of semiconductor device |
-
1989
- 1989-07-18 JP JP1186721A patent/JPH0350756A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6084838A (en) * | 1983-10-17 | 1985-05-14 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0581867A1 (en) * | 1991-04-23 | 1994-02-09 | Harris Corporation | Method of laser trimming and resulting ic |
| EP0581867A4 (en) * | 1991-04-23 | 1994-03-09 | Harris Corporation | |
| WO1999019905A1 (en) * | 1997-10-13 | 1999-04-22 | Fujitsu Limited | Semiconductor device having fuse and fabrication method thereof |
| US6399472B1 (en) | 1997-10-13 | 2002-06-04 | Fujitsu Limited | Semiconductor device having a fuse and a fabrication method thereof |
| US6617664B2 (en) | 1997-10-13 | 2003-09-09 | Fujitsu Limited | Semiconductor device having a fuse and a fabrication process thereof |
| JP2011086863A (en) * | 2009-10-19 | 2011-04-28 | Fuji Electric Systems Co Ltd | Semiconductor device, and method of manufacturing the same |
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