JP5464722B2 - Embedded copper foil for microcircuit formation - Google Patents

Description

  The present invention relates to an embedded copper foil for forming a fine circuit, and more particularly to an embedded copper foil having a barrier layer.

  In response to the high integration, miniaturization, and weight reduction of electronic components, circuit miniaturization and resin thickness reduction are being promoted. As one technique related to this, an embedded type fine circuit pattern technique for embedding a circuit in a resin, which is not the formation of a circuit by existing etching, has been developed.

  In order to manufacture an embedded wiring board having such a fine circuit pattern, an attempt was made to use an ultra-thin copper foil having an existing physically peelable release layer. However, there are problems such as generation of wrinkles and penetration of chemicals into the peeling layer during the removal, which makes it difficult to put into practical use. Also, in the case of the embedded method, when the seed layer has a high roughness, the adhesion with the plating resist layer is lowered, and the electrolytic layer is formed between the seed layer and the plating resist pattern portion during electrolytic copper plating for circuit formation. Copper plating is also formed at the edge between them, causing a problem that the interval between the wirings of the fine pattern becomes narrow. In addition, when the carrier copper foil layer, the barrier layer, and the seed layer are completely etched sequentially, a portion having a high roughness of the seed layer is excessively etched, thereby causing a problem of short circuit.

  Therefore, there is a need for an embedded pattern copper foil that improves the adhesion between the seed layer and the plating resist layer so that the spacing between fine pattern wirings can be obtained uniformly.

  One aspect of the present invention is to provide a new copper foil for an embedded pattern.

  According to one aspect of the present invention, a carrier copper foil layer, a barrier layer formed on one surface of the carrier copper foil layer, and a seed layer formed on the surface of the barrier layer, the barrier layer comprises: An embedded pattern copper foil, which is a nickel or nickel alloy layer, the seed layer is a copper layer, and the average roughness of the surface of the seed layer is Rz: less than 1.5 μm and Rmax: less than 2.5 μm. provide.

  According to one aspect of the present invention, by using a copper foil including a seed layer with a low surface roughness, there is no short circuit or reduction in circuit width when forming a fine pattern, and the seed layer is physically peeled off. Since there is no chemical penetration of the wrinkles and the release layer, an embedded wiring board having a high-density circuit pattern can be obtained.

It is a schematic diagram of the manufacturing process of the embedded wiring board manufactured using copper foil provided with a seed layer with low surface roughness. It is a schematic diagram of the manufacturing process of the embedded wiring board manufactured using copper foil provided with a seed layer with high surface roughness. 2 is a scanning electron microscope photograph of the surface of a copper foil for embedded pattern manufactured in Example 1. FIG. 4 is a scanning electron microscope photograph of the surface of the embedded pattern copper foil produced in Comparative Example 1. FIG. It is a schematic diagram of a surface treatment device that can continuously electrodeposit each barrier layer, seed layer, and rust prevention layer on the surface of a carrier copper foil layer.

  Hereinafter, a copper foil for an embedded pattern, a method of manufacturing an embedded wiring board, and an embedded wiring board manufactured by the method according to an embodiment of the present invention will be described in more detail.

  An embedded pattern copper foil according to an exemplary embodiment includes a carrier copper foil layer, a barrier layer formed on one surface of the carrier copper foil layer, and a seed layer (circuit formation) formed on the surface of the barrier layer. The barrier layer is a nickel or nickel alloy layer, the seed layer is a copper layer, and the average roughness of the surface of the seed layer is Rz: less than 1.5 μm, Rmax : Less than 2.5 μm.

  If the average roughness of the surface of the seed layer exceeds the range of Rz: less than 1.5 μm and Rmax: less than 2.5 μm, the adhesion between the portion having a high surface roughness of the seed layer and the plating resist layer An air gap may be generated at the edge portion due to the decrease in. Therefore, in the step of forming a copper plating layer having a fine circuit pattern, a copper plating layer is formed in the gap, so that the circuit width is reduced and the circuit width becomes non-uniform. In addition, in order to manufacture the final embedded substrate, a portion having high roughness is relatively excessively etched while the carrier copper foil layer, the barrier layer, and the seed layer are sequentially removed, so that a circuit is obtained. Defects such as short circuit may occur.

  In the embedded pattern copper foil, the barrier layer is a nickel or nickel alloy layer. The nickel or nickel alloy layer is stable without dissolving in the copper etchant in the copper carrier copper foil layer and seed layer etching step, and is completely etched without residue in the barrier layer etching step. The

  In the embedded pattern copper foil, the carrier copper foil layer has a thickness of 18 to 70 μm. More preferably, the thickness of the carrier copper foil layer is 18 to 35 μm. If the thickness of the carrier copper foil layer is too thick, after the embedded pattern is formed, the removal time of the carrier copper foil layer becomes long and the life of the etching solution is shortened. If the thickness of the carrier copper foil layer is too thin, the role of the support of the carrier copper foil layer is lowered during the work process, and many wrinkles may occur. Further, in the process of forming the copper circuit pattern, the carrier copper foil layer is quickly etched, so that the nickel barrier layer is relatively excessively etched.

  In the embedded pattern copper foil, the barrier layer has a thickness of 0.1 to 10 μm. More preferably, the barrier layer has a thickness of 0.3 to 3 μm. If the barrier layer is too thick, the surface of the plating becomes rough, resulting in a problem that the surface roughness becomes high when the seed layer is plated, and the etching time becomes longer and the life of the etching solution is shortened. Productivity decreases. If the barrier layer is too thin, the fine copper circuit layer is also etched through the pinhole in the process of removing the carrier copper foil due to plating defects such as pinholes in the plating layer. The barrier layer has a low surface roughness.

  In the embedded pattern copper foil, the barrier layer is inactive to the seed layer etchant. That is, the barrier layer may not be etched with an etchant used for etching the seed layer. Since the barrier layer is inactive to the seed layer etchant, a stable barrier layer can be formed.

  In the embedded pattern copper foil, the seed layer has a thickness of 0.1 to 10 μm. More preferably, the seed layer has a thickness of 2 to 5 μm. If the thickness of the seed layer is too thick, the etching time for removing the seed layer after the formation of the embedded pattern becomes long, and the productivity of the etching solution decreases, for example, the life of the etching solution is shortened. If the thickness of the seed layer is too thin, the development process for forming the plating resist and the formation of the fine pattern is insufficient for the surface modification step of the seed layer and other cleaning process time, and the copper of the fine circuit pattern. Pin holes and other plating defects may occur during the plating process.

  In the embedded pattern copper foil, the plating solution used to form the barrier layer includes nickel sulfamate, nickel sulfate, nickel chloride and the like as a nickel supply source. The plating solution contains nickel carbonate and sulfuric acid as pH adjusting agents. The plating solution contains citric acid, glycolic acid, lactic acid and the like as complexing agents for controlling plating rate and preventing plating decomposition, and sodium allyl sulfonate, benzene sulfonic acid, lauryl sulfone as wetting agents to improve the properties of the plating film. Contains sodium acid. The plating solution may include a brightener.

  In the embedded pattern copper foil, the seed layer is formed by gloss plating. The seed layer formed by bright plating has a low surface roughness.

The plating solution used for the bright plating includes copper cyanide, copper sulfate and the like. For example, the plating solution used for the bright plating is copper sulfate pentahydrate (CuSO ₄ 5H ₂ O) 80 to 400 g / L, sulfuric acid (H ₂ SO ₄ ) 10 to 250 g / L, chlorine ion (Cl ⁻ ). 1 to 100 ppm, gloss accelerator 1 to 100 ppm, carrier agent 1 to 100 ppm and electrodeposition inhibitor 1 to 100 ppm, and if necessary, to further increase the strength of the electrolytic copper foil, a nitrogen-containing compound or the like may be further included. Good.

The gloss accelerator is a sulfur compound. Sulfur contained in the sulfur compound has a high affinity for copper. Therefore, the sulfur is well adsorbed on the negative electrode and prevents metal ions from moving to the active site, thereby promoting the miniaturization of the particles to be plated. For example, including one or more selected from the group consisting of bis- (3-sulfopropyl) -disulfide disodium salt (SPS), mercaptopropanesulfonic acid (MPS), N, N-dimethyldithiocarbamic acid, Without limitation, any gloss accelerator used in the art can be used.

  The carrier agent is adsorbed on the surface of the negative electrode and extends the diffusion distance of metal ions, thereby suppressing rapid precipitation of copper. In addition, the carrier agent is adsorbed on the surface of the negative electrode and changes the diffusion path of metal ions, thereby expanding the activation polarization and consequently improving the uniformity of copper electrodeposition. . For example, a carrier having a high affinity with a negative electrode having a C—O bond, such as polyethylene glycol and polypropylene glycol, and hydroxyethyl cellulose (HEC) or a mixture thereof, but is not limited thereto, and is a carrier used in the art. Any agent is used.

  The electrodeposition inhibitor is well adsorbed at a portion having a relatively high current density, and plays a role of delaying copper deposition by expanding activation polarization. Examples of electrodeposition inhibitors used in the art include, but are not limited to, surfactants having nitrogen-containing bonds, such as amines in polyamine forms such as gelatin and glue, amides, or mixtures thereof. Both are used.

  In the embedded pattern copper foil, a rust prevention layer may be further formed on the seed layer. The rust preventive layer includes one or more components of Zn, Ni, Cr, Mo, Fe, and Sn.

  According to another exemplary embodiment, a copper foil for an embedded pattern is manufactured by continuously electrodepositing a barrier layer and a seed layer on a carrier copper foil layer. The embedded pattern copper foil is manufactured by continuously electrodepositing a barrier copper layer, a seed layer, and a rust preventive layer on a carrier copper foil layer. For example, as shown in FIG. 5, the embedded pattern copper foil is formed in each electrolytic cell, negative electrode, to which different electrolytes are continuously supplied in order to continuously plate the barrier layer and the seed layer. A barrier layer, a seed layer, and a rust preventive layer are continuously electrodeposited on one surface of the carrier copper foil layer using each energizing roll to which potential is applied and a surface treatment device equipped with an anode in each electrolytic cell. Manufactured.

  An embedded wiring board manufacturing method according to another exemplary embodiment includes a step of preparing a copper foil for an embedded pattern including a carrier copper foil layer, a barrier layer, and a seed layer, and a surface of the seed layer of the copper foil for embedded pattern In addition, a step of forming a plating resist layer, a plating step of a fine copper plating layer for forming a fine pattern in a region where the plating resist layer is not formed, and completely removing the plating resist layer, Preparing a copper foil for an embedded pattern in which a copper plating layer having a fine pattern is formed; impregnating the copper plating layer having the fine pattern into an insulating layer to produce a copper clad laminate; and Removing the carrier copper foil layer present on the opposite side of the layer to expose the barrier layer; and By removing the layer includes exposing a seed layer, and a step of removing the seed layer.

  The manufacturing method will be described more specifically with reference to FIG. As shown in the first step of FIG. 1, an embedded pattern copper foil comprising a carrier copper foil layer, a barrier layer formed on one surface of the carrier copper foil layer, and a seed layer formed on the barrier layer is provided. Be prepared.

  As the prepared embedded pattern copper foil, the aforementioned embedded pattern copper foil is used. That is, since the surface roughness of the seed layer of the copper foil for embedded patterns used in the manufacturing method is low, the adhesion between the plating resist layer and the seed layer is improved. Therefore, the generation of voids between the seed layer and the plating resist layer is suppressed at the edge of the pattern obtained after the plating resist layer is partially developed.

  Next, a plating resist layer is formed on the surface of the seed layer, and after forming a fine copper plating layer using the seed layer as an electrode in an area where the plating resist layer is not formed, the plating resist is completely removed. Finally, a fine pattern is formed. The kind of plating resist used for forming the plating resist layer is not particularly limited, and is not particularly limited as long as it is used in the technical field. Development of the plating resist layer is also performed using conventional techniques known in the art.

  Next, a copper plating layer is electrolytically plated using the seed layer as an electrode in a region where the plating resist layer is not formed, and the plating resist is completely removed. As a plating solution used for forming the copper plating layer, a copper plating solution usually used for electrolytic plating is used.

  And the copper plating layer which has the said fine pattern is impregnated in an insulating layer like a prepreg, and a copper clad laminated board is manufactured. Finally, a carrier copper foil layer, a barrier layer, and a seed layer are sequentially etched with the copper clad laminate, and a fine embedded wiring board is finally obtained. The prepreg may be an epoxy resin, polyimide, phenol, bismaleimide triazine resin (BT) or the like that is commonly used in the technical field, and is not particularly limited.

  On the other hand, as shown in FIG. 2, in the copper foil in which the seed layer having a high surface roughness exists, the surface of the seed layer is non-uniform, so that the adhesion between the plating resist layer and the seed layer is lowered. Therefore, a gap between the seed layer and the plating resist layer is generated at the edge of the pattern obtained after the plating resist layer is partially developed, and the copper plating layer penetrates into the gap, thereby reducing the circuit width. Therefore, it is difficult to implement a uniform fine circuit pattern because the entire circuit interval becomes non-uniform.

  In the manufacturing method, the etching solution for selectively removing the carrier copper foil layer and the seed layer is selected from the group consisting of sulfuric acid, hydrogen peroxide, and nitric acid.

  In the manufacturing method, the etching solution for selectively removing the barrier layer is selected from the group consisting of a special grade sulfuric acid solution having a concentration of 550 ml / L to 650 ml / L, and a mixed solution of sulfuric acid / nitric acid and an additive. For example, by using a sulfuric acid solution having a concentration of 600 to 620 ml / L, a nickel layer or a nickel alloy layer as a barrier layer can be selectively etched in the solution.

  An embedded wiring board according to still another exemplary embodiment is manufactured by the method for manufacturing an embedded wiring board. A wiring board manufactured by the method of manufacturing an embedded wiring board has a low defect rate and excellent productivity because the distance between the fine wirings is uniform.

  Hereinafter, the present invention will be described in more detail with reference to preferred examples, but the present invention is not limited thereto.

(Manufacture of copper foil for embedded wiring boards)
Example 1
1. Preparation of Carrier Foil An electrolytic copper foil having a thickness of 20 μm was immersed in 100 g / L sulfuric acid for 5 seconds, pickled, and then washed with pure water.

2. Formation of Barrier Layer A barrier layer was formed by Ni plating in a plating bath under the following conditions.
Nickel sulfamate: 350-600 g / L
Boric acid (H ₃ BO ₃ ): 15-40 g / L
Plating bath temperature: 40-60 ° C
Current density: 20 A / dm ²
The thickness of the formed barrier layer was 2 μm.

3. Formation of seed layer (pre-fine circuit layer) A bright plating layer was formed under the following conditions using a copper plating bath having the following composition.
Plating bath temperature: 25-30 ° C
Current density: 10-20 A / dm ²
Composition of copper sulfate bright plating bath CuSO ₄ 5H ₂ O: (200) g / L, H ₂ SO ₄ : 100 g / L
Chlorine ion (Cl ⁻ ): 5 to 30 ppm
Mercaptopropanesulfonic acid (MPS, gloss accelerator): 5-10 ppm
Hydroxyethyl cellulose (carrier agent): 1 to 5 ppm
Gelatin (electrodeposition inhibitor): 10 to 20 ppm
The seed layer formed as described above had a thickness of 4 μm.

Example 3
A barrier layer and a seed layer were formed by the same method as in Example 1, and a rust preventive layer was formed on the seed layer by the following method.

4). Formation of antirust layer Plating bath temperature: 25-30 ° C
Current density: 0.5-1 A / dm ²
Chromic acid (CrO ₃ ): 1.5 g / L
Treatment time: 4 seconds A rust prevention layer was formed under the above conditions.

Comparative Example 1
Example 1 is the same as Example 1 except that, in the seed layer formation step, a general electrolytic plating layer having the following composition is used instead of the bright plating, and a general electrolytic plating layer is formed. The copper foil for embedded patterns was manufactured by the same method.
Plating bath temperature: 40-60 ° C
Current density: 10-20 A / dm ²
Composition of copper sulfate plating bath CuSO ₄ 5H ₂ O: 200 g / L, H ₂ SO ₄ : 100 g / L
Chlorine ion (Cl ⁻ ): 5 to 30 ppm
At this time, the thickness of the formed seed layer was 4 μm.

(Manufacture of embedded wiring boards)
Example 2
A plating resist layer was formed on the surface of the seed layer of the embedded copper foil manufactured in Example 1. A dry film made by GMP Corporation was used for forming the plating resist layer. The plating resist layer was partially developed to form a fine pattern. Next, a fine pattern copper plating layer was formed using a copper plating solution. Next, the plating resist layer was completely removed using a cleaning solution. Next, the copper foil on which the fine pattern was formed was disposed so as to be in contact with the prepreg, and was laminated and hot pressed to produce a copper clad laminate. Next, the carrier copper foil layer, the barrier layer, and the seed layer were sequentially etched using an etching solution to manufacture an embedded wiring board.

  The fine pattern copper plating layer was formed with a plating thickness of 35 μm under the same plating solution conditions as the seed layer.

  Etching solutions and etching conditions used for etching the carrier copper foil layer and seed layer (bright plated copper layer) are as follows.

  The carrier copper foil was completely etched under the conditions of an etching solution of 600 ml / L sulfuric acid, 60 ml / L hydrogen peroxide, and 60 ml / L additive.

  Etching solutions and etching conditions used for etching the barrier layer (nickel layer) are as follows.

  Only a barrier layer was selectively etched with a 650 ml / L sulfuric acid solution without etching of the carrier copper foil layer and the seed layer.

  An embedded substrate was manufactured under the above conditions.

Comparative Example 2
An embedded substrate was manufactured by the same method as in Example 2 using the embedded copper foil manufactured in Comparative Example 1.

Evaluation Example 1: Evaluation of Surface Roughness of Embedded Pattern Copper Foil A scanning electron micrograph of the copper foil surface (seed layer) produced in Example 1 and Comparative Example 1 was measured, and FIG. 3 and FIG. The surface roughness Rz and Rmax were measured by the IPC TM 650 2.2 17A method. The measurement results are shown in Table 1 below.

  As shown in FIGS. 3 and 4, the copper foil manufactured in Example 1 exhibited a flat surface with a very low surface roughness, but the copper foil manufactured in Comparative Example 1 had a surface roughness. It represents a highly irregular surface.

Evaluation Example 2: Evaluation of Uniformity of Embedded Fine Pattern After using the copper foil produced in Example 1 and Comparative Example 1 to produce an embedded substrate in the order of FIG. 1 and FIG. 2, the cross section of the embedded fine pattern The measurement result of the scanning electron microscope was evaluated according to the following criteria. The evaluation results are shown in Table 1 below.

<Reduction in circuit width>
X: A point where the circuit width decreases is not found △: A point where the circuit width decreases is partially found O: Many points where the circuit width decreases are found

<Short circuit>
X: Circuit short-circuit point is not found Δ: Circuit short-circuit point is partially found O: Many circuit short-circuit points are found

  As shown in Table 1, when the copper foil according to the exemplary embodiment of the present invention produces an embedded fine pattern as compared with the copper foil of the comparative example, the defect rate of the fine pattern is remarkably improved.

  According to one aspect of the present invention, by using a copper foil having a seed layer with a low surface roughness, there is no short circuit or reduction in circuit width when forming a fine pattern, and the wrinkle of the seed layer due to physical peeling is eliminated. Since there is no chemical penetration of the release layer, an embedded wiring board having a high-density circuit pattern can be obtained.

Claims (10)

A carrier copper foil layer;
A barrier layer formed on one surface of the carrier copper foil layer;
A seed layer formed on the surface of the barrier layer,
The barrier layer is a nickel or nickel alloy layer, the seed layer is a copper layer;
The average roughness of the surface of the seed layer is Rz: less than 1.5 μm and Rmax: less than 2.5 μm.   The copper foil for embedded patterns according to claim 1, wherein the barrier layer has a thickness of 0.1 to 10 µm.   The copper foil for an embedded pattern according to claim 1, wherein the barrier layer is inactive with respect to the etching solution for the seed layer.   The embedded pattern copper foil according to claim 1, wherein the seed layer has a thickness of 0.1 to 10 μm.   The embedded pattern copper foil according to claim 1, wherein the seed layer is formed by gloss plating. The plating solution used for the bright plating is copper sulfate pentahydrate (CuSO ₄ 5H ₂ O) 10 to 400 g / L, sulfuric acid (H ₂ SO ₄ ) 10 to 400 g / L, chlorine ion (Cl ⁻ ) 1 to The copper foil for embedded patterns according to claim 5, comprising 100 ppm, a gloss accelerator, a carrier agent and an electrodeposition inhibitor. The gloss accelerator is selected from the group consisting of disulfide bis- (3-sulfopropyl) -disulfide disodium salt (SPS), mercaptopropanesulfonic acid (MPS), N, N-dimethyldithiocarbamic acid. The copper foil for embedded patterns according to claim 6, which is one or more.   The copper foil for embedded patterns according to claim 6, wherein the carrier agent is one or more selected from the group consisting of polyethylene glycol, polypropylene glycol, and hydroxyethyl cellulose (HEC).   The copper foil for embedded patterns according to claim 6, wherein the electrodeposition inhibitor is one or more selected from the group consisting of gelatin and glue.   The copper foil for embedded patterns according to claim 1, wherein a rust prevention layer is further formed on the seed layer.