JP5456652B2 - Solid-state imaging device, imaging method, and biped robot - Google Patents

Description

  The present invention relates to a solid-state imaging device that captures an image, an imaging method, and a biped robot.

A CCD (Charge Coupled Device) is used as a solid-state imaging device used in an imaging apparatus. However, due to the problem of power consumption, it has become difficult to answer the recent demand for rapid increase in the number of pixels and improvement in readout speed.
On the other hand, as a solid-state imaging device corresponding to low power consumption, there is a CMOS (Complementary Metal-Oxide Semiconductor, hereinafter referred to as a CMOS sensor), and it is possible to increase the number of pixels and improve the reading speed. Since it is advantageous for miniaturization, the CMOS sensor is attracting attention as a high-performance image sensor that replaces the CCD for a digital camera or a video camera.

An image pickup apparatus using a CMOS sensor picks up an image by a rolling shutter method (see, for example, Patent Document 1).
FIG. 16 is a diagram illustrating a configuration of the CMOS sensor 100 corresponding to one pixel described in Patent Document 1. In FIG. The CMOS sensor 100 includes a photodiode (PD) 101, MOS transistors 102, 103, and 104, and a floating diffusion (FD) 105.
The PD 101 photoelectrically converts the subject image to generate a charge corresponding to the amount of light. MOS transistors 102 and 103 are used as switching elements. The MOS transistor 104 is used as an amplifying transistor. The FD 105 is a capacitance component of the gate electrode of the MOS transistor 104 and accumulates charges read from the PD 101. MOS transistors 102 to 104 are N-channel MOS transistors.

Further, the CMOS sensor of FIG. 16 is a three-transistor type, and the cell size in pixel units is being reduced.
When the cell size is reduced in this way, the area of the gate electrode of the MOS transistor 104 is also reduced, and the capacity of the FD 105 is correspondingly reduced.
The amount of charge accumulated in the FD 105 is determined by the capacitance of the FD 105 and the potential difference between both ends of the FD 105.
Therefore, when the voltage across the FD 105 does not change and the capacitance of the FD 105 decreases, the amount of charge accumulated in the FD 105 decreases.

For this reason, the charge generated in the PD 101 cannot be reflected. For example, for a certain brightness or more, a current having a constant current value is supplied from the MOS transistor 104, and the dynamic range is lowered. .
In order to solve this problem, in Patent Document 1, the voltage of the FD 105 is boosted, the voltage value is increased, and the amount of charge accumulated in the FD 105 is increased, thereby expanding the dynamic range.

Next, the boosting operation of the FD 105 in the CMOS sensor shown in FIG. 16 will be described with reference to FIG. FIG. 17 is a timing chart of the boosting operation of the FD 105 in the CMOS sensor of FIG. The control of the signals TX, R, and VL and the voltages VDD and VV below is performed by a control circuit (not shown).
At time _{t 101} previously, the control circuit, signals TX, R, and VL is "L" level, the voltage VDD is set to "H" level, and the voltage VV and "L" level.
At time t ₁₀₁ , the control circuit changes the signals TX and R from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 102 and 103, and the MOS transistors 102 and 103 are turned on. As a result, the charge generated in the PD 101 is transferred to the power supply VDD via the MOS transistors 102 and 103, whereby the PD 101 is reset.

At time _{t 102,} the control circuit changes the signal TX and the voltage VDD from the "H" level to the "L" level. As a result, the MOS transistor 102 is turned off because the “L” level is applied to the gate.
Then, the MOS transistor 103 reduces the voltage of the FD 105 from the “H” level to the “L” level.
The PD 101 generates charges when irradiated with light from the time when the reset process is completed, and accumulates the generated charges in itself.

At time _t103 , the control circuit changes the signal R from the “H” level to the “L” level, and changes the voltage VDD from the “L” level to the “H” level. As a result, the “L” level is applied to the gate of the MOS transistor 103 and the MOS transistor 103 is turned off.

At time _t104 , the control circuit changes the signals R and VL from the “L” level to the “H” level. Thus, since the “H” level is applied to the gate of the MOS transistor 103, the MOS transistor 103 is turned on and the voltage of the FD 105 is set to the “H” level. As a result, the voltage between the terminals of the FD 105 becomes “H” level, and a reset state in which no charge is accumulated is entered. At this time, the “H” level is applied to the gate of the MOS transistor 106 to turn on, and the connection point A is set to the “L” level.

At time t ₁₀₅ , the control circuit changes the signals R and VL from the “H” level to the “L” level, and the voltage VV from the “L” level to the “H” level.
Thereby, each of the MOS transistors 103 and 106 is turned off because the “L” level is applied to the gate.
At this time, when the voltage VV changes from the “L” level to the “H” level, the voltage between the terminals of the FD 105 is boosted from VDD (“H” level voltage) to become a voltage of VDD + α.

At time t _106, the control circuit detects the current flowing from the voltage VV to the connection point A, the voltage between the terminals of FD105 boosted detects the current flowing through the MOS transistor 104 is applied to the gate, a current to voltage Converted and stored as reference data at reset.

At time _t107 , the control circuit changes the signal TX from the “L” level to the “H” level.
As a result, the MOS transistor 102 is turned on by applying the “H” level to the gate. Then, the electric charge generated and accumulated by the PD 101 moves to the FD 105 having a higher potential than the cathode of the PD 101 via the MOS transistor 102. From the time t ₁₀₂ to time t ₁₀₇ the current that causes the movement of the charge occurs a charge corresponding to light PD is irradiated, the time for accumulating the generated electric charges, that is, exposure time.
As a result, charges generated in the PD 101 within the exposure time are transferred via the MOS transistor 102 and accumulated in the FD 105.

At time _t108 , the control circuit changes the signal TX from the “H” level to the “L” level.
As a result, the “L” level is applied to the gate of the MOS transistor 102 and the MOS transistor 102 is turned off. At this timing, the control circuit finishes transferring charges from the PD 101 to the FD 105.
Then, the control circuit starts reading the information on the charges accumulated in the FD 105. In other words, the control circuit detects the current flowing through the MOS transistor 104 corresponding to the voltage between the terminals of the FD 105, converts the current into a voltage value, and sets it as exposure data at the time of exposure. The control circuit subtracts the reference data from the exposure data to generate image data corresponding to the amount of light received by the CMOS sensor.

At time _t109 , the control circuit changes the voltage VV from the “H” level to the “L” level. As a result, the control circuit finishes reading the information on the charges accumulated in the FD 105. At this time, the step-up process for the voltage between the terminals of the FD 105 ends, and the voltage between the terminals of the FD ₁₀₅ returns to the voltage level at time t104.

At time t _110, the control circuit changes the signal R and the signal TX from the "L" level to the "H" level.
As a result, the MOS transistor 103 is turned on because the “H” level is applied to the gate. Further, since the MOS transistor 102 is turned on because the “H” level is applied to the gate, the charge existing in the PD 101 moves to the power supply VDD via the MOS transistors 102 and 103, whereby the PD 101 The reset process is performed.

At time _t111 , the control circuit changes the signal TX and the voltage VDD from the “H” level to the “L” level. As a result, the MOS transistor 102 is turned off because the “L” level is applied to the gate.
Then, the MOS transistor 103 reduces the voltage of the FD 105 from the “H” level to the “L” level.
As a result, the control circuit sets the output OFF state in which the CMOS sensor does not output charge data.
The control circuit sequentially performs the above-described reading process on the CMOS sensors arranged in a matrix.

For example, FIG. 18 is a diagram illustrating a configuration of a solid-state imaging device having a solid-state imaging device in which the CMOS sensor of FIG. 16 is one pixel and the CMOS sensors are arranged in a 2 × 2 matrix. This individual imaging device is provided with MOS transistors 1011 and 1012 for selecting each column in which CMOS sensors are arranged in a matrix. In this figure, MOS transistors 1013 and 1014 are N-channel MOS transistors.
The timing generation circuit 200 is controlled by the control circuit and outputs timing signals VV1 and VV2, timing signals ST1 and ST2 for reading exposure data from each CMOS sensor, and a signal VL to each of the vertical register 201 and the horizontal register 202. Output.
That is, before reading the exposure data, the vertical register 201 sets the signal VL to “H” level, turns on the MOS transistors 1013 and 1014, and connects the signal lines connected to the MOS transistors 104 in the CMOS sensors P11 to P22. Perform a reset operation with the ground potential. The timing generation circuit 200 sets the signal VL to the “L” level and turns off the MOS transistors 1013 and 1014 at the timing of reading the exposure data. This reset process is performed every period to be described later for reading exposure data.

Further, the vertical register 201 sequentially supplies the timing signals VV1 and VV2 to the MOS transistors 104 of the CMOS sensors in the rows in the matrix in the periods T1 and T2 (T1 = T2). In addition, the horizontal register 202 applies timing signals ST1 and ST2 for controlling which column is selected to the MOS transistors 1011 and 1012 in each column in the periods T11 and T21 which are ½ of the period T1 (T2). Output for.
Therefore, the timing signal VV1 is output in the cycle T1, the CMOS sensor P11 is selected in the cycle T12 in the cycle T1, the CMOS sensor P21 is selected in the cycle T12, and data is read out.
Similarly, the timing signal VV2 is output in the cycle T2, the CMOS sensor P12 is selected in the cycle T12 in the cycle T2, the CMOS sensor P22 is selected in the cycle T22, and data is read out.

JP 2010-68433 A

As already described, even when the gate area of the MOS transistor 104 is reduced and the capacitance of the FD 105 is reduced, the voltage between the terminals of the FD 105 of each CMOS sensor is boosted when accumulating charges.
For this reason, the amount of accumulated charge can be increased, the dynamic range of the exposure data is expanded, and the deterioration of the image data, which is the difference between the exposure data and the reference data, is suppressed.

The above-described rolling shutter can realize high-speed readout with low power and low cost by using a CMOS sensor as compared with a global shutter when capturing a still image.
However, in the rolling shutter, when capturing a moving image, the exposure timing is shifted for each row because the shutter is opened for each row as described above. For this reason, the rolling shutter has drawbacks such as when the subject is quickly captured or the imaging apparatus is panned, the moving subject is distorted or the screen is distorted.

In order to prevent this phenomenon, an imaging apparatus that uses a global shutter, saves power, and reduces defects in capturing a moving image has come to be used for CMOS sensors.
However, the configuration in which the image pickup apparatus performs voltage boosting in units of rows shown in FIG. 18 cannot cope with a global shutter that needs to boost the voltage between terminals of the FD 105 of all pixels simultaneously. That is, if the timing signals VV1 and VV2 for selecting the output are simultaneously changed to the “H” level, the exposure data signal to be output for each row is synthesized.

  The present invention has been made in view of such circumstances, and its purpose is to increase the dynamic range by boosting the voltage between the terminals of a floating diffusion that is composed of a CMOS sensor and performs charge accumulation in this CMOS sensor. An object of the present invention is to provide a global shutter type solid-state imaging device, an imaging method, and a biped robot equipped with the solid-state imaging device.

The present invention has been made to solve the above-described problems, and a solid-state imaging device according to the present invention includes a plurality of CMOS sensors (for example, CMOS sensors 1, 2, 3, 4, S11, S12, S21 in the embodiments). In the solid-state imaging device having S22) arranged in a matrix and having a global shutter function, the CMOS sensor photoelectrically converts incident light to generate charges and stores the generated charges as signal charges (for example, implementation) PD11) in the form, a floating diffusion portion (for example, FD15 in the embodiment) for accumulating the signal charge transferred from the photodiode, and the photodiode and the floating diffusion portion. A transfer transistor for transferring the signal charge (for example, real And an amplification MOS transistor (for example, the MOS transistor 14 in the embodiment) that outputs a signal current corresponding to the signal charge accumulated in the floating diffusion portion, and the solid-state imaging device In all the CMOS sensors, a power supply line for supplying power for signal current is connected in common to a power supply terminal of the amplification MOS transistor, and a gate electrode of the transfer transistor is connected in common, and the signal from the photodiode Before the charge is read, the terminal voltage of the floating diffusion part is set to a predetermined voltage, and then a power is applied to the power supply line, and the terminal voltage of the floating diffusion part of each of the CMOS sensors is changed to the amplification MOS transistor. The gate electrode and the The capacity of the source terminal, characterized in that at the same time boosting from the predetermined voltage.
With this configuration, the voltage between the terminals of the floating diffusion portion in all the CMOS sensors of the solid-state imaging device is boosted at the same time, and after the floating diffusion portion is boosted in a batch, in all the CMOS sensors of the individual imaging device, The signal charges can be transferred simultaneously from the photodiode to the floating diffusion portion at the same time, thereby providing a global shutter function.
For this reason, according to the present invention, it is possible to increase the voltage of the floating diffusion unit in a global shutter type solid-state imaging device composed of a CMOS sensor, and the dynamic range of the exposed image data can be changed to the conventional global shutter type imaging. It becomes possible to extend to the device.

  The solid-state imaging device of the present invention includes the floating diffusion portion (for example, FD15 in the embodiment) in all CMOS sensors (for example, CMOS sensors 1, 2, 3, 4, S11, S12, S21, and S22 in the embodiment). The inter-terminal voltage is simultaneously boosted, the signal current is sequentially detected as a reference current at the timing when the inter-terminal voltage is saturated by boosting, and after the reading of the reference current is completed, the transfer transistors (for example, all the CMOS sensors) The MOS transistor 12 in the embodiment is turned on to transfer the signal charge from the photodiode (for example, PD11 in the embodiment) to the floating diffusion portion (for example, FD15 in the embodiment), and after the signal charge transfer Of the signal Control unit for sequentially detecting the exposure current (e.g., control unit 30 in the embodiment), characterized in that it further comprises a.

In the solid-state imaging device of the present invention, the capacitance value of the ground capacitance of the gate electrode of the amplification MOS transistor (for example, the MOS transistor 14 in the embodiment) is CFD, and the gate electrode of the amplification MOS transistor and the power are supplied. The amplification MOS transistor is formed so that CVV> CFD when the capacitance value with the terminal is CVV.
With this configuration, the capacitance value CVV is set larger than the capacitance value CFd. Therefore, when the power supply changes from the “L” level to the “H” level, the capacitance value CVV is the same as the capacitance value CFd or the capacitance value. Compared with the case where CVV is smaller than the capacitance value CFd, the voltage between the terminals of the floating diffusion portion can be boosted higher.
For this reason, according to the present invention, compared with the case where the capacitance value CVV is the same as the capacitance value CFd or the capacitance value CVV is smaller than the capacitance value CFd, the voltage between the terminals of the floating diffusion portion is increased, so The dynamic range of data can be expanded.

  The solid-state imaging device of the present invention further includes a reset transistor (for example, a MOS transistor 13) interposed between the floating diffusion unit (for example, FD15 in the embodiment) and a power source, and the control unit (for example, for example) Further, before the control unit 30) in the embodiment boosts the voltage, the reset is performed with the voltage between the terminals of the floating diffusion unit as the voltage of the power supply.

  The solid-state imaging device according to the present invention includes a drain provided between the photodiode and the power source that controls accumulation of the signal charge generated when the photodiode (for example, the PD 11 in the embodiment) is exposed. When the transistor (for example, the MOS transistor 21 in the embodiment) is further included and the control unit (for example, the control unit 30 in the embodiment) does not accumulate the signal charge generated by exposure in the photodiode, the drain transistor is The signal charge generated in the power supply is transferred in an ON state.

In the imaging method of the solid-state imaging device according to the present invention, a plurality of CMOS sensors (for example, CMOS sensors 1, 2, 3, 4, S11, S12, S21, and S22 in the embodiment) are arranged in a matrix and have a global shutter function. In the imaging method of the solid-state imaging device, a photodiode (for example, the PD 11 in the embodiment) photoelectrically converts incident light to generate charges in the CMOS sensor, and the generated charges are accumulated as signal charges. The signal charge transferred from the photodiode is transferred to the floating diffusion portion via a transfer transistor (for example, the MOS transistor 12) interposed between the floating diffusion portion (for example, the FD 15 in the embodiment). Accumulate and amplify MOS transistor in front And outputs a signal current corresponding to the signal charges accumulated in the floating di Fusion unit, for all the CMOS sensor in front of the solid-state imaging device at the time of boosting reading out the signal charge from the photodiode, said floating de Fusion After the terminal voltage of the unit is set to a predetermined voltage, a power supply voltage is simultaneously supplied to a terminal to which the power of the amplification MOS transistor is supplied, and the terminal voltage of the floating diffusion unit of each of the CMOS sensors is changed to the amplification MOS transistor. Simultaneously boosting from the predetermined voltage by the capacitance of the gate electrode and the power supply terminal, and applying a signal for transferring the signal charge to the gate electrodes of all the transfer transistors of the solid-state imaging device at the time of shuttering It is characterized by.

The biped walking robot of the present invention (for example, the biped walking robot 500 in the embodiment) includes any one of the solid-state imaging devices (for example, 50L and 50R in the embodiment).
With this configuration, it is possible to realize a bipedal walking robot equipped with a step-up global shutter type solid-state imaging device including a CMOS sensor having a function of stepping up the voltage of the floating diffusion portion.
For this reason, according to the present invention, by using a solid-state imaging device capable of acquiring image data with a wide dynamic range with an inexpensive CMOS sensor, the amount of information of the image data can be increased as compared with the conventional case. This makes it possible to provide a biped walking robot with better controllability and lower cost.

According to the first and sixth aspects of the present invention, the inter-terminal voltages of the floating diffusion portions in all the CMOS sensors of the solid-state imaging device are boosted simultaneously and the floating diffusion portions are boosted collectively. Later, in all the CMOS sensors of the solid-state imaging device, signal charges can be transferred simultaneously from the photodiode to the floating diffusion portion so as to have a global shutter function.
For this reason, the invention according to claim 1 and claim 5 enables the voltage boosting operation of the floating diffusion portion in the global shutter type solid-state imaging device composed of the CMOS sensor, and the dynamic range of the exposed image data is It becomes possible to expand to a conventional global shutter type imaging apparatus.

According to the second aspect of the present invention, since the signal charge is transferred from the photodiode to the floating diffusion at the same time, the transfer time of the signal charge is shortened compared with the rolling shutter method, and this shortened time is reduced. It can be used as the time required for boosting the voltage between the terminals of the floating diffusion.
For this reason, the invention according to claim 2 boosts the voltage between the terminals of the floating diffusion portion in all the CMOSs of the solid-state imaging device, so that the load becomes large and the boosting takes time. Therefore, it is possible to realize a frame period similar to the frame period of the rolling shutter system having the boosting function.

According to the third aspect of the present invention, since the capacitance value CVV is set to be larger than the capacitance value CFd, the capacitance value CVV is the capacitance when the power supply changes from the “L” level to the “H” level. Compared with the case where the value is the same as the value CFd or the capacitance value CVV is smaller than the capacitance value CFd, the voltage across the terminals of the floating diffusion section can be boosted higher.
For this reason, the invention according to claim 3 is to increase the voltage between the terminals of the floating diffusion portion as compared with the case where the capacitance value CVV is the same as the capacitance value CFd or the capacitance value CVV is smaller than the capacitance value CFd. , The dynamic range of image data can be further expanded.

According to the fourth aspect of the present invention, the voltage before the transfer of the signal charge from the photodiode is always set to the same voltage level by setting the voltage between the terminals of the floating diffusion portion as the power supply voltage. it can.
For this reason, the invention according to claim 4 can always use the same voltage as the reference data when acquiring the reference data in the reset state after boosting the voltage between the terminals of the floating diffusion portion as one power supply voltage. From the difference from the exposure data obtained from the level change caused by the signal charge, it is possible to always obtain highly accurate image data.

According to the fifth aspect of the present invention, when the drain transistor is on, the charge generated by the phototransistor can be transferred to the power supply.
For this reason, in the invention according to claim 5, the drain transistor is turned off for a period other than the exposure period, so that the charge generated by the phototransistor is not accumulated, that is, the exposure period can be easily and arbitrarily controlled. it can.

According to the seventh aspect of the present invention, it is possible to realize a biped walking robot equipped with a step-up global shutter type solid-state imaging device composed of a CMOS sensor having a function of stepping up the voltage of the floating diffusion portion.
For this reason, the invention described in claim 7 uses a solid-state imaging device capable of acquiring image data with a wide dynamic range by an inexpensive CMOS sensor, thereby increasing the amount of information of the image data as compared with the conventional case. Therefore, it is possible to provide a biped walking robot with better controllability and lower cost.

It is a figure which shows the structural example of the CMOS sensor in the solid-state image sensor of the solid-state imaging device by one Embodiment of this invention. FIG. 2 is a diagram showing potential energy levels of PD11, the gate of a MOS transistor 12, the FD15, and the gate of a MOS transistor 13 in each operation when signal charges are transferred in the CMOS sensor 1 shown in FIG. 3 is a timing chart showing an operation example of outputting data from the CMOS sensor 1 shown in FIG. 1. It is a figure which shows the structural example of the global shutter type solid-state image sensor using the CMOS sensor 1 of FIG. 5 is a timing chart illustrating an operation example of acquiring data from the global shutter type solid-state imaging device of FIG. 4. The horizontal axis indicates the illuminance (lx) of the captured image, the vertical axis indicates the voltage value of the image data (estimated output voltage difference) obtained by subtracting the exposure data from the reference data, and the voltage VV in the electric wire LVV is changed from “L” level to “ It is a figure which shows the change of the dynamic range of FD15 by changing to H "level. It is a schematic block diagram which shows the structural example of the CMOS sensor 2 in the solid-state image sensor of the solid-state imaging device by 2nd Embodiment of this invention. It is a timing chart which shows the operation example which outputs data from the CMOS sensor 2 shown in FIG. It is a schematic block diagram which shows the structural example of the CMOS sensor 3 in the solid-state image sensor of the solid-state imaging device by 3rd Embodiment of this invention. 10 is a timing chart showing an operation example of outputting data from the CMOS sensor 3 shown in FIG. 9. It is a schematic block diagram which shows the structural example of the CMOS sensor 4 in the solid-state image sensor of the solid-state imaging device by 4th Embodiment of this invention. 12 is a timing chart illustrating an operation example of outputting data from the CMOS sensor 4 illustrated in FIG. 11. It is a figure which shows the external appearance of the biped walking robot 500 in this embodiment. It is a figure which shows the structural example of ECU70 which controls the drive of the biped walking robot 500 provided in the storage part 506 of the biped walking robot 500 of FIG. It is a figure which shows the structural example of the solid-state imaging device 50L or 50R shown in FIG. It is a figure which shows the structure of the CMOS sensor 100 corresponding to 1 pixel described in patent document 1. FIG. 17 is a timing chart of the boosting operation of the FD 105 in the CMOS sensor of FIG. It is a figure which shows the structure of the solid-state imaging device which has the CMOS sensor of FIG. 16 as 1 pixel, and has a solid-state image sensor by which a CMOS sensor is arrange | positioned at 2x2.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration example of a global shutter type CMOS sensor 1 according to a first embodiment of the present invention. In the present embodiment, the CMOS sensor 1 is configured as a solid-state imaging device including imaging portions arranged in a matrix as rows and columns, a control circuit for driving the imaging portions, and the like.
The CMOS sensor 1 is a basic unit of one pixel of the solid-state imaging device, and includes a PD 11, MOS transistors 12, 13, 14, 17, and an FD 15. The MOS transistors 12, 13, 14, and 17 are, for example, n-channel MOS transistors.

  The PD 11 has an anode connected to the ground and a cathode connected to the source of the MOS transistor 12, and performs photoelectric conversion during a period of light irradiation, that is, a signal charge generated corresponding to the amount of light irradiation during the exposure period. Is stored in the cathode.

  The floating diffusion (FD) 15 is formed by a grounding capacitance of the gate of the MOS transistor 14.

  The MOS transistor 12 has a gate connected to the signal TX line and a drain connected to the gate of the MOS transistor 14. The MOS transistor 12 is turned on when the signal TX applied to the gate becomes the “H” level (power supply voltage), and transfers the signal charge stored in the PD 11 to the FD 15.

  The MOS transistor 13 has a gate connected to the signal R line, a drain connected to the power supply line LVDD, and a source connected to the gate of the MOS transistor 14. The MOS transistor 13 is turned on when the signal R becomes “H” level, and the gate voltage of the MOS transistor 14, that is, the voltage across the terminals of the FD 15 is made the same as the voltage of the power supply line LVDD.

The MOS transistor 14 is an amplification MOS transistor that has a drain connected to the power supply line LVV and a source connected to the drain of the MOS transistor 17 and outputs a signal current corresponding to the signal charge stored in the FD 15.
That is, in the MOS transistor 14, a voltage determined by the electric charge accumulated in the FD 15 is applied to the gate, and a current corresponding to the voltage applied to the gate flows as a signal current.
The MOS transistor 14 is used for boosting the voltage between the terminals of the FD 15, and the gate voltage is increased by increasing the drain voltage by the capacitance (coupling capacitance 18) between the drain and the gate (gate electrode). Is boosted.

Here, when the capacitance value of the FD 15 (that is, the capacitance to the ground of the gate of the MOS transistor 14) is CFD and the capacitance value of the coupling capacitor 18 is CVV, the terminal of the FD 15 when the voltage of the power source VV increases by ΔVVV. The inter-voltage boost amount ΔVFD is obtained by the following equation (1).
ΔVFD = ΔVVV · CVV / (CFD + CVV) (1)
The MOS transistor 17 has a gate connected to the signal SL wiring and a source serving as an output terminal for signal current.
Here, the MOS transistor 14 is formed so that CVV> CFD.

The MOS transistor 17 has a drain connected to the source of the MOS transistor 14, a source connected to a terminal that outputs exposure data and the like from the CMOS sensor to the outside, and corresponds to the signal charge stored in the FD 15 by being selected. This is an amplification MOS transistor that outputs a signal current to be output.
That is, when the MOS transistor 17 selects the voltage VV of the wiring LVV to read the exposure data, the current due to the charge accumulated in the FD 15 at the time of selection is output as Vout.

Next, FIG. 2 is a diagram showing potential energy levels of the PD 11, the gate of the MOS transistor 12, the FD 15, and the gate of the MOS transistor 13 in each operation when signal charges are transferred in the CMOS sensor 1 shown in FIG. It is.
FIG. 2A shows the respective potential energy levels when the signal TX and the signal R are at the “L” level and the MOS transistors 12 and 13 are in the OFF state (the potential energy of the gate is low). Yes. At this time, charges corresponding to the amount of light irradiation are generated and stored in the PD 11.

FIG. 2B shows a case where the PD 11 is reset. The signal TX and the signal R are set to the “H” level, and the MOS transistors 12 and 13 are turned on (the potential energy of the gate is high). Yes. For this reason, the electric charge accumulated in the PD 11 passes through the gates of the MOS transistors 12 and 13 and is transferred to the power supply line LVDD.
As a result, the charge accumulated in the PD 11 is lost and the PD 11 is reset.

  FIG. 2C shows an exposure state in which signal charges generated corresponding to the amount of incident light are accumulated after the PD 11 is reset. The signal TX and the signal R are at the “L” level, and the MOS transistor 12 and 13 are off. For this reason, the signal charge generated in the PD 11 cannot move because the potential energy of the cathode of the PD 11 located is higher than the gates of the MOS transistors 12 and 13, and is accumulated in the cathode of the PD 11.

  FIG. 2D shows a case where the voltage between terminals of the PD 15 is boosted. At this time, the voltage VV of the power supply line LVV is at the “L” level (a predetermined voltage value lower than the voltage at the “H” level). Has changed from “H” level to “H” level. As described above, as the voltage of the power supply line LVV increases from the ground voltage (“L” level) to the power supply voltage (“H” level), the potential of the FD 15 corresponds to ΔVFD as shown in (1). Energy increases. As a result, the fluctuation amount of the voltage across the terminals of the FD 15 due to the signal charge from the PD 11 can be widened. Here, as will be described later, voltage VV is set to a voltage lower than the “H” level by the amount that contributes to boosting before reference data is read, that is, before boosting. The difference between the predetermined low voltage set in advance and the “H” level voltage contributes to ΔVVV as a boosted voltage. Similarly, in the embodiments described later, before the voltage VV is boosted, the voltage to be boosted is controlled by the control unit to a value lower than the “H” level voltage.

  FIG. 2E shows a case where the signal charge accumulated in the PD 11 is transferred to the FD 15 in the global shutter process. At this time, the signal TX becomes “H” level, the MOS transistor 12 is in the on state, the signal R becomes “L” level, and the MOS transistor 13 is in the off state. For this reason, the signal charge accumulated in the PD 11 passes through the gate of the MOS transistor 12 and moves to the FD 15 to be accumulated. Then, the MOS transistor 14 supplies a signal current corresponding to the voltage across the terminals of the FD 15 that has fluctuated due to this signal charge to a control circuit (described later).

Next, FIG. 3 is a timing chart showing an operation example of outputting data from the CMOS sensor 1 shown in FIG. The level control of the signals TX, R, SL and the power supply line LVV is performed by a control unit (not shown) as in the conventional example.
At time _{t 1} earlier, the control circuit, signals TX, R, and SL is "L" level, and the potential of the power supply line LVV to "L" level. The power source line LVDD is always at the “H” level, that is, the voltage VDD. Further, as described later, the voltage value of the voltage VV of the wiring LVV is set to a value (α) lower than the “H” level voltage value in advance for the boosting process.
At time t _1, the control circuit changes the signal TX and R from the "L" level to the "H" level. Further, the control circuit changes the voltage value of the gates of the MOS transistors 12 and 13 from the voltage “L” level at the time of reset to the “H” level, and the MOS transistors 12 and 13 are turned on. As a result, the charge generated in the PD 11 moves to the power supply line LVDD via the MOS transistors 12 and 13, thereby resetting the PD 11 (the PD 11 terminal voltage is set to the “H” level voltage). Done.

In time t _2, the control circuit to end the reset process, changes the signal TX and R from the "H" level to the "L" level (ground potential). As a result, the “L” level is applied to the gate of the MOS transistor 12, and the MOS transistor 12 is turned off. The MOS transistor 13 is turned off because the “L” level is applied to the gate.
The PD 11 generates charges by being irradiated with light from the time when the reset process is completed, and accumulates the generated charges in itself. From this point, exposure, that is, accumulation of signal charges corresponding to the amount of light irradiated is started.

At time t ₃ , the control circuit changes the signal R from the “L” level to the “H” level. As a result, the MOS transistor 13 is turned on by applying the “H” level to the gate.
Then, charges move from the FD 15 to the power supply line LVDD via the MOS transistor 13, and the voltage of the FD 15 becomes the “H” level (voltage VDD) similarly to the power supply line LVDD. As a result, the FD 15 is in a state where no signal charge is accumulated, that is, in a reset state.

At time t _4, the control circuit causes changes the signal R from the "H" level to the "L" level, and changes the voltage of the power line LVV from the "L" level to the "H" level.
As a result, the “L” level is applied to the gate of the MOS transistor 13, and the MOS transistor 13 is turned off.
Further, the voltage between terminals of the FD 15 increases, for example, when the power supply line LVV rises to the voltage VDD, for example, the boost amount ΔVFD obtained from the equation (1) described above from the voltage VDD.
As a result, the capacity of the FD 15 with respect to the accumulated signal charge is increased, the width of the amount of change due to the signal charge in the voltage between the terminals of the FD 15 is increased, and the dynamic range of the signal current obtained from the MOS transistor 14 is increased (increased). Will be).

At time t _5, the control circuit does not not perform any processing.
From time t ₄ to time t _5, the voltage VV of the power supply line LVV is provided as a delay time until changes from "L" level to the "H" level. That is, this delay time is a time until the voltage between the terminals of the FDD 15 is boosted and saturated.
As will be described later, since the solid-state imaging device according to the present embodiment is a global shutter type, the voltage of the power supply line LVV connected to the drain of the MOS transistor 14 of the CMOS sensor 1 in the solid-state imaging device is set to the “L” level ( It is necessary to raise the voltage from a preset “H” level to a “H” level from a voltage that is lower than the voltage that contributes to boosting.
However, since the capacity of power supply line LVV is large, it does not rise to “H” level in a short time. Since the signal current at the reset level in which no signal charge is transferred cannot be read out until the voltage VDD is saturated, the voltage VV of the power supply line LVV is changed from the voltage lower than the preset “H” level voltage to “H”. It will be in a standby state until it reaches a level (power supply voltage VDD).

At time t _6, the control circuit, after the voltage VDD becomes "H" level and changes the signal SL from the "L" level to the "H" level. As a result, the MOS transistor 17 is turned on by applying the “H” level to the gate. The MOS transistor 14 applies a signal current corresponding to the voltage across the terminals of the reset level FD 15 applied to the gate.
At this timing, the control circuit detects the signal current at the reset level of the CMOS sensor 1 via the MOS transistor 17.

That is, the control circuit detects a signal current flowing through the MOS transistor 14 to which the boosted inter-terminal voltage of the FD 15 is applied to the gate, converts this signal current into a voltage value, and uses the external current as reference data at the reset level. Write to the storage device and store.
Here, the time from time t ₄ to time t ₆ is the power line LVV already mentioned the time of total wait state until the voltage VDD. The total time is set, for example, by measuring the time until the voltage VV of the power supply line LVV actually rises to the voltage VDD.

At time t _7, the control circuit changes the signal SL from the "H" level to the "L" level. As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off.

At time t _8, the control circuit changes the signal TX from the "L" level to the "H" level. As a result, the MOS transistor 12 is turned on by applying the “H” level to the gate.
Then, the charge generated and accumulated by the PD 11 is transferred via the MOS transistor 12 to the FD 15 having a higher potential than the cathode of the PD 11. For this reason, the time corresponding to the light irradiated by the PD 11 is generated from the time t ₂ to the current time t ₈ when the charge is moved, and this is the time for accumulating the generated charge, that is, the exposure time.
As a result, the charge generated and accumulated by the PD 11 within the exposure time is transferred via the MOS transistor 12 and accumulated in the FD 15.
That is, the signal charge accumulated in the PD 11 is transferred from the PD 11 to the FD 15, and the voltage between the terminals of the FD 15 changes according to the charge amount of the signal charge.
Further, the period from time t ₇ to the time t _8, the control unit is the time to read the other reference data of the CMOS sensor 1 of the solid-state imaging device.

At time t _9, the control circuit changes the signal TX from the "H" level to the "L" level.
As a result, the “L” level is applied to the gate of the MOS transistor 12 and the MOS transistor 12 is turned off. At this timing, the control circuit ends the transfer of charge from the PD 11 to the FD 15.

At time t _10, the control circuit changes the signal SL from the "L" level to the "H" level.
As a result, the MOS transistor 17 is turned on because the “H” level is applied to the gate. At this time, the MOS transistor 17 enters a state in which the signal current flowing from the MOS transistor 14 to the drain flows out from the source.
Then, the control circuit starts reading the information on the charges accumulated in the FD 15. That is, the control circuit detects the signal current flowing through the MOS transistor 14 corresponding to the voltage between the terminals of the FD 15 via the MOS transistor 17 and converts this signal current into a voltage value to obtain exposure data at the time of exposure. . Further, the control circuit subtracts the reference data stored corresponding to the CMOS sensor 1 from the exposure data, and generates image data corresponding to the amount of light received by the CMOS sensor 1.

At time t _11, the control circuit changes the signal SL from the "H" level to the "L" level.
As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off.
As a result, the control circuit finishes reading the exposure data from the CMOS sensor 1. Further, the control circuit maintains the voltage level of the power supply line LVV at the “H” level until reading of exposure data from other CMOS sensors in the solid-state imaging device is completed.
Then, the control circuit changes the voltage level of the power supply line VLL from the “H” level to the “L” level at the timing when reading of exposure data from all the CMOS sensors 1 in the solid-state imaging device is completed.
During the period from time t ₉ to the time t _11, the control circuit performs processing of reading the exposure data from all the CMOS sensor 1 in the solid-state imaging device. Controller, by repeating the process from time t ₁ described above until time t _11, and generates the image data of the moving image.

Next, FIG. 4 is a diagram showing a configuration example of a global shutter type solid-state imaging device using the CMOS sensor 1 of FIG. 1 in the present embodiment. This solid-state imaging device is configured by arranging a plurality of CMOS sensors (the above-described CMOS sensor 1) in a matrix of vertical n × horizontal m. In the present embodiment, as an example, as shown in FIG. 4, a solid-state imaging device composed of four CMOS sensors arranged in a matrix of 2 × 2 in a matrix will be described below as an example.
The solid-state imaging device of this embodiment includes CMOS sensors S11, S12, S21 and S22, MOS transistors 181, 182, timing generation circuit 20, vertical register 21, horizontal example register 22, and control circuit 30 (control circuit (not shown). As well as). Here, each of the CMOS sensors S11, S12, S21, and S22 has the same configuration as the CMOS sensor 1 of FIG.

The drain of the MOS transistor 181 is connected to the source of the MOS transistor 17 in the CMOS sensors S11 and S12.
The drain of the MOS transistor 182 is connected to the source of the MOS transistor 17 in the CMOS sensors S21 and S22.
Each of these MOS transistors 181 and 182 has a source connected in common, and is used to select any column output (Out, exposure data or reference data) in the CMOS sensor matrix.

The timing generation circuit 20 is controlled by the control circuit 30 and outputs timing signals SL1 and SL2 and timing signals ST1 and ST2 to the vertical register 21 and the horizontal register 22, respectively, when outputting image data from the solid-state imaging device. Let
The vertical register 21 outputs a signal SL1 to the gate of the MOS transistor 17 in the CMOS sensors S11 and S21, and outputs a signal SL2 to the gate of the MOS transistor 17 in the CMOS sensors S12 and S22.
The horizontal register 22 supplies the signal ST1 to the gate of the MOS transistor 181 and supplies the signal ST2 to the gate of the MOS transistor 182.

The power supply line LVDD is a wiring that supplies the voltage VDD (“H” level voltage), and is connected in common to the drains of the MOS transistors 13 in all the CMOS sensors of the solid-state imaging device.
The power supply line LVV is a wiring for supplying a voltage VV (either “H” level or “L” level lower than a preset voltage of the “H” level). The drains of the MOS transistors 14 are commonly connected.
The signal line LR is a wiring for supplying the signal R, and is connected in common to the gates of the MOS transistors 13 in all the CMOS sensors of the solid-state imaging device.
The signal line LTX is a wiring for supplying the signal TX, and is connected in common to the gates of the MOS transistors 12 in all the CMOS sensors of the solid-state imaging device.

Next, FIG. 5 is a timing chart showing an operation example of the global shutter type solid-state imaging device of FIG.
The control circuit 30 (not shown) controls the timing generation circuit 20, the signal R, the signal TX, and the voltage VV. At time _{t 21} Previously, a previous reading of the image data, the control circuit 30 is the signal R, TX, power VV and timing signals SL1, SL2, ST1, ST2 and as "L" level.
Hereinafter, the operation of the solid-state imaging device of FIG. 4 will be described with reference to the timing chart of FIG.

At time t _21, the control circuit 30 changes the signal TX and R from the "L" level to the "H" level. Thereby, the MOS transistor 12 and the MOS transistor 13 in all the CMOS sensors of the solid-state imaging device are simultaneously turned on.
As a result, the PD 11 and the FD 15 in all the CMOS sensors of the solid-state imaging device are reset, and an initial state (voltage VDD) in which signal charges are not accumulated is obtained. That is, all the MOS sensors in the solid-state image sensor are reset simultaneously.

At time t _22, the control circuit 30 changes the signal TX and R from the "H" level to the "L" level. As a result, the “L” level is applied to the gates of the MOS transistors 12 and 13 in all the CMOS sensors of the solid-state imaging device, and the transistors are turned off. The control circuit 30 ends the reset process of the CMOS sensor in the solid-state image sensor.
Further, the control circuit 30 changes the voltage VV of the power supply line LVV from the “L” level to the “H” level, and starts boosting the voltage between the terminals of the FD 15. As already described, the power supply line LVV is connected to the drain of the MOS transistor 14 in all the CMOS sensors of the solid-state imaging device. Therefore, the control circuit 30 needs to supply a current to a large capacity, and a long time is required to set the voltage VV of the power supply line VLL to the “H” level.

At time t _23, the control circuit 30 to the timing generating circuit 20, the timing generating circuit 20 outputs a timing control signal for instructing to start the control for the vertical register 21 and horizontal register 22. Time from time t ₂₂ to time t _23, the voltage of the power supply line LVV is set as a boost time to reach (saturated) to the "H" level. The control circuit 30 measures that the boosting time has elapsed with an internal timer, and after the boosting time has elapsed, the control circuit 30 outputs a signal current at the reset level (current flowing through the MOS transistor 14 corresponding to the voltage across the FD 15 after boosting). ) Reading process is started.

When the timing control signal is input, the timing generation circuit 20 outputs a control signal for setting the signal SL1 to the “H” level to the vertical register 21. Then, the vertical register 21 changes the signal SL1 from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 17 in the CMOS sensors S11 and S21, and the MOS transistors 17 in the CMOS sensors S11 and S21 are turned on.
That is, in the CMOS sensor matrix of the solid-state imaging device, the rows of the CMOS sensors S11 and S21 are selected as targets for reading the reference data by the signal SL1.
Here, the timing generation circuit 20 outputs a control signal for setting the signal SL1 to the “H” level, and then starts counting time by an internal timer.

At time t ₂₄ , the timing generation circuit 20 outputs a control signal for setting the signal ST 1 to the “H” level to the horizontal register 22 when the counting time reaches T 11. Then, the horizontal register 22 changes the signal ST1 from “L” level to “H” level. As a result, the MOS transistor 181 is turned on by applying the “H” level to the gate.
As a result, both the signal SL1 and the signal ST1 are set to the “H” level, and the MOS transistors 17 and 181 of the CMOS sensor S11 are turned on. Is selected.
Then, the control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S11 via the MOS transistors 17 and 181. After the detection, the control circuit 30 converts the signal current into reference data, and writes and stores the reference data of the CMOS sensor S11 in an external storage device at an address for setting the reference data of the CMOS sensor S11.

At time t ₂₅ , when the counting time reaches T 21, the timing generation circuit 20 outputs a control signal for setting the signal ST 1 to “L” level and the signal ST 2 to “H” level to the horizontal register 22. . Then, the horizontal register 22 changes the signal ST1 from “H” level to “L” level, and changes the signal ST2 from “L” level to “H” level. As a result, the “L” level is applied to the gate of the MOS transistor 181 and the MOS transistor 181 is turned off. In addition, the MOS transistor 182 is turned on when the “H” level is applied to the gate.
As a result, both the signal SL1 and the signal ST2 are set to the “H” level, and the MOS transistors 17 and 182 in the CMOS sensor S21 are turned on. Is selected.
The control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S21 via the MOS transistors 17 and 182. After the detection, the control circuit 30 converts the signal current (Out in FIG. 4) into reference data, and writes it as reference data for the CMOS sensor S21 in an external storage device at an address for setting the reference data for the CMOS sensor S21. Let

At time t ₂₆ , the timing generation circuit 20 sets the signal SL 1 to the “L” level for the vertical register 21 and sets the signal ST 2 to the “L” level for the horizontal register 22 when the counting time reaches T 2. Output a control signal. As a result, the MOS transistor 182 and the MOS transistors 17 in the CMOS sensors S11 and S21 are turned off by applying the “L” level to the gates.
The timing generation circuit 20 outputs a control signal for setting the signal SL1 to the “H” level to the vertical register 21.

Then, the vertical register 21 changes the signal SL1 from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 17 in the CMOS sensors S12 and S22, and the MOS transistors 17 in the CMOS sensors S12 and S22 are turned on.
That is, in the CMOS sensor matrix of the solid-state imaging device, the rows of the CMOS sensors S12 and S22 are selected by the signal SL2 as targets for reading the reference data.

At time t ₂₇ , the timing generation circuit 20 outputs a control signal for setting the signal ST 1 to the “H” level to the horizontal register 22 when the counting time reaches T 12. Then, the horizontal register 22 changes the signal ST1 from “L” level to “H” level. As a result, the MOS transistor 181 is turned on by applying the “H” level to the gate.
As a result, when both the signal SL2 and the signal ST1 are set to the “H” level, and the MOS transistors 17 and 181 of the CMOS sensor S12 are turned on, the CMOS sensor S12 is detected as a pixel to be detected as a signal current at the reset level. Is selected.
Then, the control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S12 via the MOS transistors 17 and 181. After the detection, the control circuit 30 converts the signal current into reference data, and writes and stores the reference current of the CMOS sensor S12 at the address for setting the reference data of the CMOS sensor S12 in the external storage device.

At time t ₂₈ , when the counting time reaches T 22, the timing generation circuit 20 outputs a control signal that sets the signal ST 1 to “L” level and the signal ST 2 to “H” level to the horizontal register 22. . Then, the horizontal register 22 changes the signal ST1 from “H” level to “L” level, and changes the signal ST2 from “L” level to “H” level. As a result, the “L” level is applied to the gate of the MOS transistor 181 and the MOS transistor 181 is turned off. In addition, the MOS transistor 182 is turned on when the “H” level is applied to the gate.
As a result, when both the signal SL2 and the signal ST2 are set to the “H” level, and the MOS transistors 17 and 182 in the CMOS sensor S22 are turned on, the CMOS sensor S22 is used as a pixel to be detected as a reset level signal current. Is selected.
Then, the control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S22 via the MOS transistors 17 and 182. After the detection, the control circuit 30 converts the signal current into reference data, and writes and stores the reference data of the CMOS sensor S22 in an external storage device at an address for setting the reference data of the CMOS sensor S22.

At time t ₂₉ , when the counting time reaches T 3, the timing generation circuit 20 outputs a control signal for setting the signal SL 2 to the “L” level to the vertical register 21 and also outputs a signal to the horizontal register 22. A control signal for setting ST2 to “L” level is output. The vertical register 21 changes the signal SL2 from “H” level to “L” level, and the horizontal register 22 changes the signal ST2 from “H” level to “L” level. As a result, the MOS transistors 17 in the CMOS sensors S12 and S22 are turned off by applying the “L” level to the gates. In addition, the MOS transistor 182 is turned off when the “L” level is applied to the gate.
In addition, the timing generation circuit 20 outputs an end signal indicating that reading of all the CMOS sensors of the solid-state image sensor has been completed to the control circuit 30.
Then, when the end signal is supplied, the control circuit 30 transfers the signal charge from the PD 11 to the FD 15 in all the CMOS sensors of the solid-state imaging device, so that the signal TX is changed from the “L” level to the “H” level. To change. As a result, the MOS transistors 12 in the CMOS sensors S11, S21, S12, and S22 are simultaneously turned on by applying the “H” level to the gates.
In the CMOS sensors S11, S21, S12, and S22, the signal charges generated and accumulated corresponding to the amount of light irradiated on the PD 11 are transferred to the FD 15 through the MOS transistor 12, and the signal charges are accumulated in the FD 15. The

At time t ₃₀ , the control circuit 30 outputs a timing control signal that instructs the timing generation circuit 20 to start control of the vertical register 21 and the horizontal register 22.
That is, the control circuit 30 corresponds to the signal current (corresponding to the voltage across the terminals of the FD 15 after the signal charge transfer) corresponding to the signal charge obtained by the exposure in the time from the time t ₂₂ to the time t ₂₉ , accumulated in the FD 15. Then, the reading process of the current flowing in the MOS transistor 14 is started.

When the timing control signal is input, the timing generation circuit 20 outputs a control signal for setting the signal SL1 to the “H” level to the vertical register 21. Then, the vertical register 21 changes the signal SL1 from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 17 in the CMOS sensors S11 and S21, and the MOS transistors 17 in the CMOS sensors S11 and S21 are turned on.
That is, in the CMOS sensor matrix of the solid-state imaging device, the rows of the CMOS sensors S11 and S21 are selected as targets for reading exposure data by the signal SL1.
Here, the timing generation circuit 20 outputs a control signal for setting the signal SL1 to the “H” level, and then starts counting time by an internal timer.

At time t _31, the timing generating circuit 20, the time during which the count reaches T11, to the horizontal register 22, and outputs a control signal to a signal ST1 and "H" level. Then, the horizontal register 22 changes the signal ST1 from “L” level to “H” level. As a result, the MOS transistor 181 is turned on by applying the “H” level to the gate.
As a result, when both the signal SL1 and the signal ST1 are set to the “H” level, and the MOS transistors 17 and 181 of the CMOS sensor S11 are turned on, the signal current detection target corresponding to the signal charge generated by the exposure is detected. As a result, the CMOS sensor S11 is selected.
Then, the control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S11 via the MOS transistors 17 and 181. After the detection, the control circuit 30 converts the signal current into exposure data, reads the reference data of the CMOS sensor S11 from the external storage device, subtracts the reference data from the exposure data, and uses the subtraction result as image data as an external storage device. Then, the image data of the CMOS sensor S11 is written and stored at the set address.

At time t _32, the timing generating circuit 20, the time during which the count reaches T21, to the horizontal register 22, a signal ST1 is "L" level, and outputs a control signal to the signal ST2 to "H" level . Then, the horizontal register 22 changes the signal ST1 from “H” level to “L” level, and changes the signal ST2 from “L” level to “H” level. As a result, the “L” level is applied to the gate of the MOS transistor 181 and the MOS transistor 181 is turned off. In addition, the MOS transistor 182 is turned on when the “H” level is applied to the gate.
As a result, when both the signal SL1 and the signal ST2 are set to the “H” level, and the MOS transistors 17 and 182 in the CMOS sensor S21 are turned on, the signal current detection target corresponding to the signal charge generated by the exposure is detected. As a result, the CMOS sensor S21 is selected.
The control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S21 via the MOS transistors 17 and 182. After the detection, the control circuit 30 converts the signal current into exposure data, reads the reference data of the CMOS sensor S21 from the external storage device, subtracts the reference data from the exposure data, and uses the subtraction result as image data as an external storage device. Then, the image data of the CMOS sensor S21 is written and stored in the set address.

At time t ₃₃ , when the counting time reaches T 2, the timing generation circuit 20 sets the signal SL 1 to the “L” level for the vertical register 21 and sets the signal ST 2 to the “L” level for the horizontal register 22. Output a control signal. As a result, the MOS transistor 182 and the MOS transistors 17 in the CMOS sensors S11 and S21 are turned off by applying the “L” level to the gates.
The timing generation circuit 20 outputs a control signal for setting the signal SL1 to the “H” level to the vertical register 21.

Then, the vertical register 21 changes the signal SL1 from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 17 in the CMOS sensors S12 and S22, and the MOS transistors 17 in the CMOS sensors S12 and S22 are turned on.
That is, in the CMOS sensor matrix of the solid-state imaging device, the rows of the CMOS sensors S12 and S22 are selected by the signal SL2 as the target for reading the exposure data.

At time t ₃₄ , the timing generation circuit 20 outputs a control signal for setting the signal ST 1 to “H” level to the horizontal register 22 when the counting time reaches T 12. Then, the horizontal register 22 changes the signal ST1 from “L” level to “H” level. As a result, the MOS transistor 181 is turned on by applying the “H” level to the gate.
As a result, when both the signal SL2 and the signal ST1 are set to the “H” level, and the MOS transistors 17 and 181 of the CMOS sensor S12 are turned on, the signal current detection target corresponding to the signal charge generated by the exposure is detected. As a result, the CMOS sensor S12 is selected.
Then, the control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S12 via the MOS transistors 17 and 181. After the detection, the control circuit 30 converts the signal current into exposure data, reads the reference data of the CMOS sensor S12 from the external storage device, subtracts the reference data from the exposure data, and uses the subtraction result as image data as an external storage device. Then, the image data of the CMOS sensor S12 is written and stored at the set address.

At time t ₃₅ , when the counting time reaches T 22, the timing generation circuit 20 outputs a control signal for setting the signal ST 1 to “L” level and the signal ST 2 to “H” level to the horizontal register 22. . Then, the horizontal register 22 changes the signal ST1 from “H” level to “L” level, and changes the signal ST2 from “L” level to “H” level. As a result, the “L” level is applied to the gate of the MOS transistor 181 and the MOS transistor 181 is turned off. In addition, the MOS transistor 182 is turned on when the “H” level is applied to the gate.
As a result, when both the signal SL2 and the signal ST2 are set to the “H” level, and the MOS transistors 17 and 182 in the CMOS sensor S22 are turned on, the signal current detection target corresponding to the signal charge generated by the exposure is detected. As a result, the CMOS sensor S22 is selected.
Then, the control circuit 30 detects the signal current flowing through the MOS transistor 14 in the CMOS sensor S22 via the MOS transistors 17 and 182. After detection, the control circuit 30 converts the signal current into exposure data, reads out the reference data of the CMOS sensor S22 from the external storage device, subtracts the reference data from the exposure data, and uses the subtraction result as image data as an external storage device. Then, the image data of the CMOS sensor S22 is written and stored at the set address.
From time t ₂₁ to time t ₄₁ described above is one frame, that is, image data acquisition processing for all CMOS sensors of the solid-state imaging device.

At time t ₄₁ , when the counting time reaches T 3, the timing generation circuit 20 outputs a control signal for setting the signal SL 2 to “L” level to the vertical register 21 and also outputs a signal to the horizontal register 22. A control signal for setting ST2 to “L” level is output. The vertical register 21 changes the signal SL2 from “H” level to “L” level, and the horizontal register 22 changes the signal ST2 from “H” level to “L” level. As a result, the MOS transistors 17 in the CMOS sensors S12 and S22 are turned off by applying the “L” level to the gates. In addition, the MOS transistor 182 is turned off when the “L” level is applied to the gate.
Further, the timing generation circuit 20 outputs to the control circuit 30 a read end signal indicating that exposure data has been read from all CMOS sensors of the solid-state imaging device.
When the readout end signal is supplied, the control circuit 30 resets the PD 11 and the FD 15 in all the CMOS sensors of the solid-state imaging device. Change to “H” level. Thereby, the MOS transistor 12 and the MOS transistor 13 in all the CMOS sensors of the solid-state imaging device are simultaneously turned on.
As a result, the PD 11 and the FD 15 in all the CMOS sensors of the solid-state imaging device are reset, and an initial state in which signal charges are not accumulated is obtained.

From the time _{t 42} to time _{t 61} is the same as the processing time _{t 41} from the time _{t 22} already described. Thereafter, the processes from time t ₄₁ to time t ₅₅ is repeated, the image data of each frame of the moving image is acquired by the solid-state imaging device. In the present embodiment, the description has been given with the individual imaging device in which the CMOS sensors are arranged in a 2 × 2 matrix. It is natural.

  According to the present embodiment described above, in the global shutter type solid-state imaging device, the FD 15 in all CMOS sensors is boosted at the same time, and the signal charge is transferred from the PD 11 to the FD 15 at the same time. The amount can be increased, and image data with a wider dynamic range can be obtained as compared with a conventional global shutter type solid-state imaging device.

In the global shutter process, the voltage across the terminals of the FD 15 in all CMOS sensors of the solid-state imaging device is boosted from VDD to VDD + α (ΔVFD).
For this reason, since the global shutter process boosts the voltage of the power supply line LVV connected to the drains of the MOS transistors 14 of all the CMOS sensors of the solid-state imaging device, the load to be boosted becomes large. As compared with a rolling shutter type solid-state imaging device that performs boosting in units of rows in the arrangement, it takes time to boost.

However, in this embodiment, since all the CMOS sensors of the solid-state imaging device perform the boosting process in a synchronized manner, they are compared with a rolling shutter type solid-state imaging device that performs signal charge movement of each CMOS sensor in time series. As a result, the number of times of boosting can be reduced, and as a result, the imaging frame period can be made the same as that of a rolling shutter type solid-state imaging device.
As described above, according to the present invention, a solid-state image sensor using a CMOS sensor has a frame period similar to that of a rolling shutter type solid-state image sensor, and the dynamic range of acquired image data is the conventional global shutter system. Thus, it is possible to provide a global shutter type solid-state imaging device that is wider than the solid-state imaging device.

In FIG. 6, the horizontal axis represents the illuminance (lx) of the imaging surface, and the vertical axis represents the voltage value of image data (estimated output voltage difference) obtained by subtracting the exposure data from the reference data. This image data voltage value indicates a result of conversion to a digital voltage value by an A / D (analog / digital) conversion circuit (not shown) connected to the next stage. Here, as described above, in order to perform correction by the gain of the source follower of the MOS transistor 14, the exposure data is divided by the reference data to obtain image data. The exposure time is 10 μ (micro) seconds.
In this figure, the voltages before boosting are 3.3V (◇: dashed line) when there is no boosting, and 2V (◆: solid line wavy), 1.8V (◆: wavy line) when boosting, 1 This shows changes in the voltage value of the exposure data with respect to the brightness value of the captured image at four types of voltages of .6 V (♦: dotted line).

As can be seen from FIG. 6, the voltage VV of the electric wire LVV is set lower than the “H” level voltage before the exposure data is transferred from the PD 11 to the FD 15. When the voltage value set lower than the “level” is changed to the voltage value of the “H” level, the voltage change of the voltage VV is increased and the voltage across the terminals of the FD 15 is further boosted. The lower the voltage, the wider the dynamic range of the image data with respect to no boost.
However, if the voltage before reading the exposure data is reduced too much, for example, in the case of 1.6 in FIG. 9, the voltage value read as the reference data in the MOS transistor 14 will have non-linearity. The linearity between the illuminance and the image data at the time is reduced.

<Second Embodiment>
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 7 is a schematic block diagram showing a configuration example of the CMOS sensor 2 according to the second embodiment of the present invention.
The CMOS sensor 2 is a basic unit of one pixel of a global shutter type solid-state imaging device, and includes a PD 11, MOS transistors 12, 13, 14, 17, 19, FD 15, and a capacitor 40. The MOS transistors 12, 13, 14, 17 and 19 are, for example, n-channel MOS transistors. In FIG. 7, the same components as those of the CMOS sensor 1 of FIG. Only the configuration and operation different from those of the first embodiment will be described below.

PD 11 has an anode grounded and a cathode connected to the source of MOS transistor 19.
The capacitor 40 is connected to the source of the MOS transistor 19 as a storage capacitor for once storing the signal charge generated by the PD 11.
The MOS transistor 12 has a gate connected to the wiring of the signal TR and a drain connected to the gate of the MOS transistor 14. The MOS transistor 12 is turned on when the signal TX applied to the gate becomes “H” level, and transfers the signal charge accumulated in the capacitor 40 to the FD 15.
Since the subsequent configuration is the same as that of the first embodiment, description thereof is omitted.

That is, in the second embodiment, when the exposure time ends, the MOS transistor 19 is turned on, and the signal charge generated and accumulated by the PD 11 is temporarily accumulated in the capacitor 40.
Since the capacitor 40 is less affected by external disturbances such as noise than the FD 15, the probability that the accumulated amount of signal charges fluctuates is low. The global shutter operation is realized by transferring the signal charge from the PD 11 to the capacitor 40 by all the CMOS sensors 2 in the solid-state imaging device. This CMOS sensor 2 can be used as the CMOS sensors S11, S12, S13 and S14 of FIG.

Next, FIG. 8 is a timing chart showing an operation example of outputting data from the CMOS sensor 2 shown in FIG. The level control of the signals TR, TX, R, SL and the power supply line LVV is performed by a control unit (not shown) (for example, the control unit 30 in FIG. 4, but the control of the signal TR is added) as in the conventional example.
Prior to time t ₂₀₁ , the control circuit sets the signals TR, TX, R, and SL to the “L” level and sets the potential of the power supply line LVV to the “L” level. The power source line LVDD is always at the “H” level, that is, the voltage VDD.
At time _t201 , the control circuit changes the signals TR, TX, and R from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 19, 12 and 13, and the MOS transistors 19, 12 and 13 are turned on. As a result, the charge generated in the PD 11 is transferred to the power supply line LVDD via the MOS transistors 19, 12 and 13, whereby the PD 11 is reset. At this time, the reset process is also performed on the capacitor 40, and the voltage between the terminals of the capacitor 40 becomes the voltage VDD.

At time _t202 , the control circuit changes the signals TR, TX, and R from the “H” level to the “L” level in order to end the reset process. As a result, the “L” level is applied to the gate of the MOS transistor 19, so that the MOS transistor 19 is turned off. Further, since the “L” level is applied to the gate, the MOS transistor 12 is turned off. The MOS transistor 13 is turned off because the “L” level is applied to the gate.
The PD 11 generates charges by being irradiated with light from the time when the reset process is completed, and accumulates the generated charges in itself. From this point, exposure, that is, accumulation of signal charges corresponding to the amount of light irradiated is started.

At time t ₂₀₃ , the control circuit changes the signal TR from the “H” level to the “L” level in order to transfer the signal charge generated in the PD 11 and accumulated in the cathode from the PD 11 to the capacitor 40. As a result, the MOS transistor 19 is turned on because the “H” level is applied to the gate.
As a result, the signal charge accumulated at the cathode of the PD 11 moves to the capacitor 40 via the MOS transistor 19.
That is, in this embodiment, the time from time t ₂₀₂ to time t ₂₀₃ is the exposure time.

At time t _204, the control circuit is to terminate the transfer of the signal charge for the capacitor 40 from the PD 11, changes the signal TR from the "H" level to the "L" level. As a result, the “L” level is applied to the gate of the MOS transistor 19, so that the MOS transistor 19 is turned off.
As a result, the transfer of the signal charge from the PD 11 to the capacitor 40 is completed, and the signal charge generated by the PD 11 is accumulated in the capacitor 40.
At this time, the transfer of the signal charges accumulated in the PD 11 to the capacitor 40 is performed simultaneously in synchronism with all the CMOS sensors of the solid-state imaging device (global shutter processing).

At time t _205, the control circuit, for performing a reset process of the FD15, changes the signal R from the "L" level to the "H" level. As a result, the MOS transistor 13 is turned on since the “H” level is applied to the gate.
When the MOS transistor 13 is turned on, the electric charge present in the FD 15 moves to the power supply line LVDD, so that the voltage between the terminals of the FD 15 becomes the voltage VDD, and reset processing of the FD 15 is performed.

At time t ₂₀₆ , the control circuit ends the reset process of the FD 15 and changes the signal R from the “H” level to the “L” level and increases the voltage of the power supply line LVV in order to boost the voltage across the terminals of the FD 15. The “L” level (voltage that is lower than the preset “H” level by a voltage that contributes to boosting) is changed to the “H” level (voltage VDD).
As a result, the “L” level is applied to the gate of the MOS transistor 13, and the MOS transistor 13 is turned off. And the reset process of FD15 is complete | finished.
Further, the voltage between the terminals of the FD 15 corresponds to the voltage of the power supply line LVV, and the voltage corresponding to the boost amount ΔVFD obtained from the expression (1) is increased from the voltage VDD. As a result, as described above, the width of the amount of change due to the signal charge in the voltage between the terminals of the FD 15 can be increased, and the dynamic range of the image data can be expanded.

At time t ₂₀₇ , the control circuit changes the signal SL from the “L” level to the “H” level in order to read the reset level of the voltage across the terminals of the FD 15. As a result, the MOS transistor 17 is turned on when the “H” level of the gate is applied.
As a result, the MOS transistor 14 causes the signal current corresponding to the voltage across the terminals of the reset level FD 15 applied to the gate to flow to the control circuit via the MOS transistor 17.
Then, at this timing, the control circuit detects a signal current corresponding to the reset level of the voltage between the terminals of the FD 15 and writes and stores it as reference data in a storage unit inside one end.
Also, from time t ₂₀₆ to time t ₂₀₇ is a time until the voltage VV of the power supply line LVV becomes the voltage VDD, that is, a time until the voltage between the terminals of the FDD 15 is boosted and saturated.

At time t ₂₀₈ , the control circuit changes the signal SL from the “H” level to the “L” level and transfers the signal TX from the “L” level to “ Change to “H” level.
As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off. As a result, the control circuit ends the detection of the signal current corresponding to the voltage (reset level) between the terminals of the FD 15 via the MOS transistor 17.
Further, the MOS transistor 12 is turned on because the “H” level is applied to the gate. As a result, the signal charge accumulated in the capacitor 40 is transferred from the capacitor 40 to the FD 15, and the voltage between the terminals of the FD 15 changes according to the amount of signal charge.

At time _t209 , the control circuit ends the transfer of charges and changes the signal TX from the “H” level to the “L” level and also changes the signal SL to the “L” level in order to read out the signal current as the exposure data. To “H” level.
As a result, the “L” level is applied to the gate of the MOS transistor 12, and the MOS transistor 12 is turned off. As a result, the transfer of signal charges from the capacitor 40 to the FD 15 is completed.
Then, the control circuit starts reading the information on the charges accumulated in the FD 15. That is, the MOS transistor 17 is turned on because the “H” level is applied to the gate. As a result, the MOS transistor 14 supplies a signal current corresponding to the voltage across the terminals of the FD 15 that has been applied to the gate and changed according to the signal charge, to the control circuit via the MOS transistor 17. Then, at this timing, the control circuit detects a signal current flowing through the MOS transistor 14 that has changed in accordance with the signal charge with respect to the reset level, sets it as exposure data, and performs processing for calculating image data from this exposure data.
At this time, the control circuit subtracts the reference data stored in the internal storage unit corresponding to the CMOS sensor 2 from the exposure data, and image data based on the signal charge corresponding to the amount of light received by the CMOS sensor 2. Is written and stored in an external storage device.

At time _t210 , the control circuit changes the signal SL from the “H” level to the “L” level in order to finish reading the exposure data from the CMOS sensor 2. As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off.
Further, after time t ₂₁₀ , the control circuit sequentially turns on the MOS transistors 17 of the other CMOS sensors 2 in the solid-state imaging device and reads exposure data from the other CMOS sensors 2 in time series. That is, the control circuit sequentially performs processing for obtaining image data from reset level reading to signal level reading for all the CMOS sensors 2 of the solid-state imaging device.

The present embodiment can be used as a pixel of the solid-state imaging device of FIG. 4 as in the first embodiment of FIG.
In the present embodiment, as described above, the charge generated by the exposure of the PD 11 during the period of increasing the voltage between the terminals of the FD 15 and reading the reset level of the voltage between the terminals of the FD 15 in all the CMOS sensors 2 of the solid-state imaging device. Once stored in the capacitor 40.
For this reason, according to the present embodiment, in addition to the effect of the global shutter type solid-state imaging device with the expanded dynamic range in the first embodiment, the signal charges to be accumulated are compared with those of the FD 15 connected to a plurality of wirings. The fluctuation of the charge amount can be suppressed, and stable exposure data can be detected.

Further, according to the present embodiment, since the capacitor 40 and the FD 15 exist as the two charge storage units, the reset level is held in the FD 15 and the signal charge can be transferred from the PD 11 to the capacitor 40.
For this reason, in this embodiment, when obtaining image data from the signal current of the CMOS sensor, the reset level is sequentially read out, and after obtaining the reference data, the signal charge is transferred from the capacitor 40 to the FD 15, and the MOS transistor based on this signal charge Exposure data is obtained from the signal current of 14, and reference data is subtracted from the exposure data to obtain image data. As a result, according to the present embodiment, when generating the image data, the reference data is generated using the reset level stored in the internal storage unit. Therefore, it is sufficient that the storage unit in the control circuit can store one data. Therefore, it is not necessary to provide a storage unit for reference data for all CMOS sensors outside the CMOS sensor.

<Third Embodiment>
The third embodiment of the present invention will be described below with reference to the drawings. FIG. 9 is a schematic block diagram showing a configuration example of the CMOS sensor 3 according to the third embodiment of the present invention.
The CMOS sensor 3 is a basic unit of one pixel of a global shutter type solid-state imaging device, and includes a PD 11, MOS transistors 12, 13, 14, 17 and 21, and an FD 15. The MOS transistors 12, 13, 14, 17 and 21 are, for example, n-channel MOS transistors. In FIG. 9, the same components as those of the CMOS sensor 1 of FIG. Only the configuration and operation different from those of the first embodiment will be described below. This CMOS sensor 3 can be used as the CMOS sensors S11, S12, S13 and S14 of FIG.

In the MOS transistor 21, the signal TY wiring LTY is connected to the drain, the source is connected to the cathode of the PD 11, and the signal D is supplied to the gate.
The MOS transistor 21 transfers the charge generated in the cathode of the PD 11 by being irradiated with light and accumulated in the charge of the PD 11 to the wiring TYL.
That is, the MOS transistor 21 is turned on in a period other than the exposure period so that charges generated outside the exposure period are not accumulated in the cathode of the PD 11, and the cathode is reset by transferring the charges to the wiring LTY. It keeps in. Here, the signal TY is always controlled to the “H” level voltage.
Since the subsequent configuration is the same as that of the first embodiment, description thereof is omitted.

Next, FIG. 10 is a timing chart showing an operation example of outputting data from the CMOS sensor 3 shown in FIG. The level control of the signals D, TX, R, SL and the power supply line LVV is performed by a control unit (not shown) (for example, the control unit 30 in FIG. 4, but the control of the signal D is added) as in the conventional example.
Prior to time t ₃₀₁ , the control circuit sets the signals TX, R, and SL to the “L” level, the signal D to the “H” level, and the potential of the power supply line LVV to the “L” level. Further, the power source line LVDD and the wiring LTY are always at the “H” level, that is, the voltage VDD. As a result, the MOS transistor 21 is turned on with the “H” level applied to the gate. For this reason, the charge generated in the PD 11 by the light irradiation is transferred to the wiring LTY via the MOS transistor 21.

At time t ₃₀₁ , the control circuit changes the signals TX and R from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 12 and 13, and the MOS transistors 12 and 13 are turned on. As a result, the charge generated at the cathode of the PD 11 and the charge accumulated in the FD 15 are transferred to the power supply line LVDD via the MOS transistors 12 and 13, whereby the reset process of the FD 15 is performed.

At time _t302 , the control circuit changes the signals TX and R from the “H” level to the “L” level in order to end the reset process. As a result, the “L” level is applied to the gate of the MOS transistor 12, and the MOS transistor 12 is turned off. The MOS transistor 13 is turned off because the “L” level is applied to the gate.
The PD 11 generates an electric charge when irradiated with light from the time when the reset process is completed. However, since the charge generated by the PD 11 is transferred to the wiring LTY via the MOS transistor 21, the cathode of the PD 11 remains in the reset state.
In addition, the control circuit changes the voltage VV of the signal line LVV from the “L” level (a voltage that is lower than the preset “H” level by a voltage that contributes to boosting) to the “H” level.
As a result, the voltage between the terminals of the FD 15 corresponds to the voltage of the power supply line LVV, and the voltage corresponding to the boost amount ΔVFD obtained from the equation (1) increases from the voltage VDD. As a result, as described above, the width of the amount of change due to the signal charge in the voltage between the terminals of the FD 15 can be increased, and the dynamic range of the image data can be expanded.

At time t ₃₀₃ , the control circuit does not perform the processing of the CMOS sensor 3 because it is within the period for saturating the voltage between the terminals of the FD 15 to the “H” level.

At time t ₃₀₄ , the control circuit changes the signal SL from the “L” level to the “H” level in order to read the reset level of the voltage across the terminals of the FD 15. As a result, the MOS transistor 17 is turned on when the “H” level of the gate is applied.
As a result, the MOS transistor 14 causes the signal current corresponding to the voltage across the terminals of the reset level FD 15 applied to the gate to flow to the control circuit via the MOS transistor 17.
Then, at this timing, the control circuit detects a signal current corresponding to the reset level of the voltage across the terminals of the FD 15 and writes and stores it as reference data in an external storage device.
From time t ₃₀₂ to time t ₃₀₄ is a time until the voltage VV of the power supply line LVV becomes the voltage VDD, that is, a time until the voltage between the terminals of the FDD 15 is boosted and saturated.

At time t ₃₀₅ , the control circuit changes the signal SL from the “H” level to the “L” level in order to transfer the signal charge from the cathode of the PD 11 to the FD 15.
As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off. As a result, the control circuit ends the detection of the signal current corresponding to the voltage (reset level) between the terminals of the FD 15 via the MOS transistor 17.

At time t ₃₀₆ , the control circuit changes the signal TX from the “L” level to the “H” level in order to transfer the signal charge generated in the PD 11 and accumulated in the cathode from the PD 11 to the FD 15. D is changed from “H” level to “L” level. As a result, the MOS transistor 12 is turned on because the “H” level is applied to the gate.
The MOS transistor 21 is turned off because the “L” level is applied to the gate. As a result, the charge generated at the cathode of the PD 11 does not move to the wiring LTY but is accumulated at the cathode of the PD 11 because the MOS transistor 21 is in the off state.
Therefore, the signal charge generated at the cathode of the PD 11 is transferred to the FD 15 via the MOS transistor 12, and the voltage between the terminals of the FD 15 changes according to the amount of signal charge.
At this time, in the CMOS sensors 3 of all the solid-state imaging devices, the transfer of signal charges from the capacitor 40 to F15 is performed simultaneously in synchronism (global shutter processing).
Here, the time from time t ₃₀₄ to time t ₃₀₆ is a processing time for reading out the signal current corresponding to the voltage (reset level) between the terminals of the FD 15 from all the CMOS sensors 3 in the solid-state imaging device and obtaining the reference data. is there.

At time t ₃₀₇ , the control circuit changes the signal TX from the “H” level to the “L” level and changes the signal D from the “L” level to the “H” level in order to end the exposure process. As a result, the “L” level is applied to the gate of the MOS transistor 12 and the MOS transistor 12 is turned off. Further, the MOS transistor 21 is turned on when the “H” level is applied to the gate. At this timing, the control circuit ends the transfer of signal charges from the PD 11 to the FD 15.
As a result, the signal charge is not transferred from the PD 11 via the MOS transistor 12, so that the change in the voltage between the terminals of the FD 15 is completed. Further, the charge generated at the cathode of the PD 11 moves to the wiring LTY via the MOS transistor 21. Therefore, no signal charge is accumulated on the cathode of the PD 11.

At time _t308 , the control circuit changes the signal SL from the “L” level to the “H” level.
As a result, the MOS transistor 17 is turned on because the “H” level is applied to the gate. At this time, the MOS transistor 17 enters a state in which the signal current flowing from the MOS transistor 14 to the drain flows out from the source.
Then, the control circuit starts reading the information on the charges accumulated in the FD 15. That is, the control circuit detects the signal current flowing through the MOS transistor 14 corresponding to the voltage between the terminals of the FD 15 via the MOS transistor 17 and converts this signal current into a voltage value to obtain exposure data at the time of exposure. . Further, the control circuit subtracts the reference data stored corresponding to the CMOS sensor 3 from the exposure data, and generates image data corresponding to the amount of light received by the CMOS sensor 3.

At time _t309 , the control circuit changes the signal SL from the “H” level to the “L” level.
As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off.
As a result, the control circuit ends reading of exposure data from the CMOS sensor 3. Further, the control circuit maintains the voltage level of the power supply line LVV at the “H” level until reading of exposure data from the other CMOS sensor 3 in the solid-state imaging device is completed.
Then, the control circuit changes the voltage level of the power supply line VLL from the “H” level to the “L” level at the timing when the reading of the exposure data from all the CMOS sensors 3 in the solid-state imaging device is completed.
In the period from time t ₃₀₈ to time t ₃₁₀ , the control circuit performs processing for reading exposure data from all the CMOS sensors 3 in the solid-state imaging device.
The control device generates image data of a moving image by repeatedly performing the processing from time t ₃₀₁ to time t ₃₁₀ described above.

The present embodiment can be used as a pixel of the solid-state imaging device of FIG. 4 as in the first embodiment of FIG.
In this embodiment, as described above, during the period other than the exposure period, the MOS transistor 21 is turned on, and the charge generated at the cathode of the PD 11 is transferred to the wiring LTY.
For this reason, in the present embodiment, even if a charge that becomes noise other than the exposure period is generated, the charge moves to the wiring LTY via the MOS transistor 21.
For this reason, according to the present embodiment, in addition to the effect of the global shutter type solid-state imaging device with the expanded dynamic range in the first embodiment, the charge generated at the cathode of the PD 11 outside the exposure period is not accumulated, and the signal The noise component of charges can be reduced, fluctuations in the amount of accumulated charges can be suppressed, and stable exposure data can be detected.

<Fourth Embodiment>
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a schematic block diagram showing a configuration example of the CMOS sensor 4 according to the fourth embodiment of the present invention.
The CMOS sensor 4 is a basic unit of one pixel of a global shutter type solid-state imaging device, and includes a PD 11, MOS transistors 12, 13, 14, 17, 19 and 21, an FD 15, and a capacitor 40. The MOS transistors 12, 13, 14, 17 and 21 are, for example, n-channel MOS transistors. In FIG. 11, the same components as those of the CMOS sensor 1 of FIG. Only the configuration and operation different from those of the first embodiment will be described below. This CMOS sensor 4 can be used as the CMOS sensors S11, S12, S13 and S14 of FIG.

In the fourth embodiment, the signal charge generated in the PD 11 in the second embodiment is transferred to the capacitor 40 and accumulated therein, and the charge generated in the PD 11 in the third embodiment other than the exposure period is connected to the wiring LTY. It is a combination with the configuration for transferring to the network.
Since the subsequent configuration is the same as that of the first embodiment, description thereof is omitted.

Next, FIG. 12 is a timing chart showing an operation example of outputting data from the CMOS sensor 4 shown in FIG. The level control of the signals D, TX, TR, R, SL, and the power supply line LVV is performed by a control unit (not shown) (for example, the control unit 30 in FIG. 4, but the signals D and TR are added) as in the conventional example. .
Prior to time t ₄₀₁ , the control circuit sets the signals TX, TR, R, and SL to the “L” level, the signal D to the “H” level, and the potential of the power supply line LVV to the “L” level. The power source line LVDD and the wiring LTY (that is, the signal TY) are always at the “H” level, that is, the voltage VDD. As a result, the MOS transistor 21 is turned on with the “H” level applied to the gate. For this reason, the charge generated in the PD 11 by the light irradiation is transferred to the wiring LTY via the MOS transistor 21.

At time t ₄₀₁ , the control circuit changes the signals TX, TR, and R from the “L” level to the “H” level. The “H” level is applied to the gates of the MOS transistors 12, 13 and 19, and the MOS transistors 12, 13 and 19 are turned on. As a result, the charge generated at the cathode of the PD 11 and the charge accumulated in the capacitor 40 and the FD 15 are transferred to the power supply line LVDD via the MOS transistors 12 and 13, thereby resetting the capacitor 40 and the FD 15. Done. At this time, the reset process is also performed on the capacitor 40, and the voltage between the terminals of the capacitor 40 becomes the voltage VDD.

At time t ₄₀₂ , the control circuit ends the reset process and changes the signals TX, TR, R, and D from the “H” level to the “L” level to start the exposure period.
Thereby, each of the MOS transistors 12, 13, 19 and 21 is turned off because the "L" level is applied to the gate.
That is, since the charge generated by the PD 11 does not move through the MOS transistors 19 and 21, the charge is accumulated in the cathode of the PD 11.
As a result, the PD 11 generates signal charges by irradiating light from the time when the reset process is completed, and accumulates the generated signal charges in the cathode. Thereby, an exposure period for accumulating signal charges on the cathode of the PD 11 is started.

At time t ₄₀₃ , the control circuit changes the signal TR from the “L” level to the “H” level in order to transfer the signal charge accumulated at the cathode of the PD 11 from the PD 11 to the capacitor 40. As a result, the MOS transistor 19 is turned on because the “H” level is applied to the gate.
As a result, the signal charge accumulated at the cathode of the PD 11 moves to the capacitor 40 via the MOS transistor 19.
That is, in this embodiment, the time from time t ₄₀₂ to time t ₄₀₃ is the exposure time. The transfer of signal charges from the PD 11 to the capacitor 40 is performed simultaneously in synchronism with all the CMOS sensors 4 of the solid-state imaging device (global shutter processing).

At time t ₄₀₄ , the control circuit changes the signal TR from the “H” level to the “L” level and also changes the signal D from the “L” level to “H” in order to end the transfer of the signal charge from the PD 11 to the capacitor 40. "Change to the level."
As a result, the “L” level is applied to the gate of the MOS transistor 19 and the MOS transistor 19 is turned off. Then, the transfer of the signal charge from the PD 11 to the capacitor 40 is completed, and the signal charge generated by the PD 11 is accumulated in the capacitor 40.
Further, the MOS transistor 21 is turned on when the “H” level is applied to the gate. Then, the charge generated in the PD 11 when irradiated with light moves to the wiring LTY via the MOS transistor 21. Therefore, no signal charge is accumulated on the cathode of the PD 11.

At time t ₄₀₅ , the control circuit changes the signal R from the “L” level to the “H” level in order to perform the reset process of the FD 15. As a result, the MOS transistor 13 is turned on since the “H” level is applied to the gate.
When the MOS transistor 13 is turned on, the electric charge present in the FD 15 moves to the power supply line LVDD, so that the voltage between the terminals of the FD 15 becomes the voltage VDD, and reset processing of the FD 15 is performed.

At time t ₄₀₆ , the control circuit ends the reset process for the FD 15 and changes the signal R from the “H” level to the “L” level and increases the voltage of the power supply line LVV in order to increase the voltage across the terminals of the FD 15. The “L” level (voltage that is lower than the preset “H” level by a voltage that contributes to boosting) is changed to the “H” level (voltage VDD).
As a result, the “L” level is applied to the gate of the MOS transistor 13, and the MOS transistor 13 is turned off. And the reset process of FD15 is complete | finished.
Further, the voltage between the terminals of the FD 15 corresponds to the voltage of the power supply line LVV, and the voltage corresponding to the boost amount ΔVFD obtained from the expression (1) is increased from the voltage VDD. As a result, as described above, the width of the amount of change due to the signal charge in the voltage between the terminals of the FD 15 can be increased, and the dynamic range of the image data can be expanded.

At time _t407 , the control circuit changes the signal SL from the “L” level to the “H” level in order to read the reset level of the voltage across the terminals of the FD15. As a result, the MOS transistor 17 is turned on when the “H” level of the gate is applied.
As a result, the MOS transistor 14 causes the signal current corresponding to the voltage across the terminals of the reset level FD 15 applied to the gate to flow to the control circuit via the MOS transistor 17.
Then, at this timing, the control circuit detects a signal current corresponding to the reset level of the voltage between the terminals of the FD 15 and writes and stores it as reference data in a storage unit inside one end.
From time t ₄₀₆ to time t ₄₀₇ is a time until the voltage VV of the power supply line LVV becomes the voltage VDD, that is, a time until the voltage between the terminals of the FDD 15 is boosted and saturated.

At time t ₄₀₈ , the control circuit changes the signal SL from the “H” level to the “L” level and transfers the signal TX from the “L” level to “L” to transfer the signal charge from the capacitor 40 to the FD 15. Change to “H” level.
As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off. As a result, the control circuit ends the detection of the signal current corresponding to the voltage (reset level) between the terminals of the FD 15 via the MOS transistor 17.
Further, the MOS transistor 12 is turned on because the “H” level is applied to the gate. As a result, the signal charge accumulated in the capacitor 40 is transferred from the capacitor 40 to the FD 15, and the voltage between the terminals of the FD 15 changes according to the amount of signal charge.

At time _t409 , the control circuit ends the charge transfer and changes the signal TX from the “H” level to the “L” level and reads the signal SL at the “L” level in order to read out the signal current as the exposure data. To “H” level.
As a result, the “L” level is applied to the gate of the MOS transistor 12, and the MOS transistor 12 is turned off. As a result, the transfer of signal charges from the capacitor 40 to the FD 15 is completed.
Then, the control circuit starts reading the information on the charges accumulated in the FD 15. That is, the MOS transistor 17 is turned on because the “H” level is applied to the gate. As a result, the MOS transistor 14 supplies a signal current corresponding to the voltage across the terminals of the FD 15 that has been applied to the gate and changed according to the signal charge, to the control circuit via the MOS transistor 17. Then, at this timing, the control circuit detects a signal current flowing through the MOS transistor 14 that has changed in accordance with the signal charge with respect to the reset level, sets it as exposure data, and performs processing for calculating image data from this exposure data.
At this time, the control circuit subtracts the reference data stored in the internal storage unit corresponding to the CMOS sensor 4 from the exposure data, and image data based on the signal charge corresponding to the amount of light received by the CMOS sensor 4. Is written and stored in an external storage device.

At time _t410 , the control circuit changes the signal SL from the “H” level to the “L” level in order to finish reading the exposure data from the CMOS sensor 4. As a result, the “L” level is applied to the gate of the MOS transistor 17, and thus the MOS transistor 17 is turned off.
Further, after time _t410 , the control circuit sequentially turns on the MOS transistors 17 of the other CMOS sensors 4 in the solid-state imaging device and reads exposure data from the other CMOS sensors 4 in time series. That is, the control circuit sequentially performs processing for obtaining image data from reset level reading to signal level reading for all the CMOS sensors 4 of the solid-state imaging device.

The present embodiment can be used as a pixel of the solid-state imaging device of FIG. 4 as in the first embodiment of FIG.
In the present embodiment, the above-described configuration allows the effect of the global shutter type solid-state imaging device having the expanded dynamic range in the first embodiment and the signal charge in the second embodiment to be transferred to the capacitor 40 at one end. The effect of suppressing the fluctuation of the charge amount of the accumulated signal charge and the effect of reducing the noise component of the signal charge because the charge generated outside the exposure period in the third embodiment is not accumulated in the PD 11. Have.

<Fifth Embodiment>
Next, with reference to the drawings, a biped walking robot equipped with any one of the first to fourth embodiments will be described.
FIG. 13 shows the appearance of the biped walking robot 500 in this embodiment, FIG. 13A is a view of the biped walking robot 500 viewed from the front, and FIG. 13B is a side view of the biped walking robot 500. It is the figure seen from.
As shown in FIG. 13A, the biped walking robot 500 includes two legs 502, and an upper body (base) 503 is provided above the two legs 502. A head 504 is provided on the upper portion of the upper body 503, and two arm portions 505 are connected to both sides of the upper body 503.
As shown in FIG. 13B, a storage unit 506 is provided on the back of the upper body 503, and the ECU (electronic control unit, details will be described later) and the joints of the biped robot 500 are driven therein. A battery power source (not shown) of the electric motor to be stored is accommodated. Note that a biped robot 500 shown in FIG. 13 is shown with a cover attached to protect the internal structure.

The biped walking robot 500 includes six joints on the left and right leg portions 502, and also includes six joints on the left and right arm portions 503.
The head 504 includes a neck joint around a vertical axis and a head swing mechanism that rotates the head 504 with an axis orthogonal to the vertical axis.
Further, inside the head 504, a solid-state imaging device is attached in a position corresponding to the left and right eyes so that it can be viewed in stereo (compound eyes) in parallel on the left and right. Image data (for example, color image data) obtained by imaging the left and right solid-state imaging devices is supplied to an ECU, which will be described later. An ECU (Electronic Control Unit) is based on the image data, and each joint of the biped walking robot 500 For example, during walking, the twelve joints in the left and right leg portions 502 are appropriately driven at a necessary angle, so that a desired movement can be given to the entire left and right leg portions 502, and an arbitrary three-dimensional motion can be achieved. Walk through the space.
In addition, the ECU arbitrarily performs a desired work by driving the 12 joints in the left and right arm portions 505 at necessary angles as appropriate.

  Next, FIG. 14 is a diagram illustrating a configuration example of an ECU 70 that controls driving of the biped walking robot 500 provided in the storage unit 506 of the biped walking robot 500 of FIG. 13. In FIG. 14, 50R (corresponding to the right eye) and 50L (corresponding to the left eye) are solid-state imaging devices attached to the head 504.

15 is a diagram showing a configuration example of the solid-state imaging device (solid-state imaging device 50R or 50L, hereinafter referred to as 50R) shown in FIG. The solid-state imaging device 50R includes a solid-state imaging element 550 and a lens 551.
The solid-state image sensor 550 is a solid-state image sensor configured by a CMOS sensor according to any one of the first to fourth embodiments.
The solid-state image sensor 550 includes a sensor unit 550A and a control unit 550B.
In the sensor unit 550A, the CMOS sensor according to any one of the first to fourth embodiments is arranged in a matrix on the surface of the semiconductor substrate.
The control unit 550B includes the control circuit 30, the timing generation circuit 20, the vertical register 21, and the horizontal register 22 in FIG.
The lens 551 focuses incident light and forms an image of the imaging target on the sensor unit 550A.
Then, the solid-state imaging device 500 obtains the image data of the imaging target formed on the sensor unit 550A by the processing of the solid-state imaging device according to any one of the first to fourth embodiments, and the obtained image data. Is output to the ECU 70.

Next, a configuration in which the ECU 70 controls the biped walking robot 500 based on image data obtained from the solid-state imaging device will be described with reference to FIG.
The operation of the ECU 70 is a distance image generation unit that analyzes image data input from the solid-state imaging devices 50R (right side) and 50L (left side) (because it is image data of all CMOS sensors arranged in a matrix). 70a, the difference image generation unit 70b and the edge image generation unit 7c, the moving body is detected from the analyzed image, the relative distance and the relative angle between the biped walking robot 500 and the moving body are calculated, and the calculated relative distance and Based on the relative angle, a motor control unit 70d that controls the electric motor M that drives each joint is provided so that the bipedal walking robot 500 performs an operation corresponding to the moving body as necessary.

  The distance image generation unit 70a indicates a distance (depth) from the biped walking robot 500 to the imaging target based on the parallax between the two images captured by the solid-state imaging devices 50L and 50R in synchronization with the same time. An image DeI is generated. That is, the distance image generation unit 70a uses the left solid-state imaging device 50L as a reference imaging device, the image captured by the reference left solid-state imaging device 50L (hereinafter referred to as “reference image BI”), and the right-side solid-state imaging device 50L. The image captured in synchronization with the same time by the solid-state imaging device 50R (hereinafter referred to as “same-time image”) is block-matched with a predetermined size block (for example, 16 × 16 pixels), and the parallax from the reference image And the distance image DeI is generated by associating the measured parallax size (parallax amount) with each pixel of the reference image. Here, the larger the value of the parallax, the closer the imaging target is from the solid-state imaging device 50R (or 50L), and the smaller the parallax, the farther the imaging target is.

The difference image generation unit 70b calculates a difference between two reference images BI captured in time series by the solid-state imaging device 50L, and generates a difference image DiI. That is, the difference image generation unit 70b obtains a difference between two reference images BI captured in time series (time t and time t + Δt) by the solid-state imaging device 50L, and the pixel having the difference has motion (movement). A difference value DiI is generated by giving a pixel value of 1 as a pixel and giving a pixel value of 0 to a pixel having no difference as a pixel having no movement (movement).
If the background in the reference image BI at time t and time t + Δt changes as the robot 1 moves, the reference image BI captured at time t + Δt is corrected based on the amount of movement of the solid-state imaging device 50L. Only the movement of the moving body is detected as a difference.

  The edge image generation unit 70c generates an edge image EI based on the reference image BI captured by the solid-state imaging device 50L. That is, the edge image generation unit 70c detects, as an edge, a pixel whose luminance of the reference image BI changes by a predetermined level or more, and generates an edge image EI including only the detected edge. More specifically, the edge detection is performed by applying an operator having a predetermined weight coefficient (such as a Sobel operator) to the entire image, calculating a product of the corresponding pixel luminance values, and in units of rows or columns. This is performed by detecting a line segment having a difference equal to or greater than a predetermined value from an adjacent line segment as an edge.

The motor control unit 70d calculates a distance (hereinafter referred to as “moving body distance”) to a position where the moving body is estimated to exist based on the distance image DeI and the difference image DiI. At this time, for each parallax (distance) represented by the distance image DeI, the motor control unit 70d accumulates the number of pixels of the difference image DiI at the position corresponding to the parallax, and the parallax with the maximum accumulated value ( It is estimated that there is a moving object at (distance), and is set as the moving object distance.
Then, the motor control unit 70d determines whether or not the distance is smaller than a set distance set as, for example, a certain threshold based on the moving body distance.
At this time, when the moving body distance is smaller than the set distance, the motor control unit 70a stops the walking of the biped walking robot 500. On the other hand, when the moving body distance is larger than the set distance, the motor control unit 70a walks the biped walking robot 500. The electric motor M is controlled so as to continue.
The gait generation method of the biped robot 500 is described in detail in Japanese Patent Application Laid-Open No. 2002-326173 and Japanese Patent Application Laid-Open No. 2004-299001 previously proposed by the present applicant. Description of is omitted.

In the present embodiment, as described above, when the biped walking robot 500 walks around a moving body, the image used for the recognition of the moving body is the CMOS of any one of the first to fourth embodiments. Acquired by the global shutter type solid-state imaging devices 50L and 50R composed of sensors.
For this reason, according to the present embodiment, a global shutter type solid-state imaging device having a function of boosting the voltage between terminals of the floating diffusion and capable of expanding the dynamic range of image data acquired from the CMOS sensor. Therefore, it is possible to obtain highly accurate image data and improve the controllability of the biped robot compared to the case where a solid-state imaging device composed of a conventional global shutter CMOS sensor is used. be able to.

The storage device may be a hard disk device, a magneto-optical disk device, a nonvolatile memory such as a flash memory, a storage medium that can only be read such as a CD-ROM, a volatile memory such as a RAM (Random Access Memory), or It shall be comprised by these combinations.
The functions of the control circuit described above may be realized by dedicated hardware, or may be realized by a memory and a microprocessor.
That is, the control circuit may be realized by dedicated hardware, and the processing unit 30 is configured by a memory and a CPU (central processing unit), and a program for realizing the function of the control circuit is provided. The function may be realized by loading it into a memory and executing it.

  Further, a program for realizing the functions of the control circuit in the first to fifth embodiments is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system. The solid-state image sensor may be controlled by executing. Here, the “computer system” includes an OS and hardware such as peripheral devices.

Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used.
The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory in a computer system serving as a server or a client in that case, and a program that holds a program for a certain period of time are also included. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention.
In each embodiment of the present invention, a circuit configuration using electrons (negative charges) as charges is described. However, a circuit configuration using holes (positive charges) as charges may be used.

1, 2, 3, 4, S11, S12, S21, S22 ... CMOS sensor 11 ... PD (photodiode)
12, 13, 14, 17, 19, 21 ... MOS transistor 15 ... FD (floating diffusion part)
DESCRIPTION OF SYMBOLS 20 ... Timing generation circuit 21 ... Vertical register 22 ... Horizontal register 30 ... Control circuit 40 ... Capacitor 50R, 50L ... Solid-state image sensor 70 ... ECU
70a ... Distance image generation unit 70b ... Difference image generation unit 70c ... Edge image generation unit 70d ... Motor control unit 500 ... Biped robot LVD, LVV ... Power line M ... Electric motor

Claims (7)

In a solid-state imaging device having a plurality of CMOS sensors arranged in a matrix and having a global shutter function,
The CMOS sensor photoelectrically converts incident light to generate electric charges, and accumulates the generated electric charges as signal charges;
A floating diffusion section for accumulating the signal charge transferred from the photodiode;
A transfer transistor for transferring the signal charge, interposed between the photodiode and the floating diffusion portion;
An amplification MOS transistor that outputs a signal current corresponding to the signal charge accumulated in the floating diffusion portion, and
In all the CMOS sensor of the solid-state imaging device, the power supply line for supplying a power supply terminal for the signal current of the amplifying MOS transistor are connected in common, and the gate electrode of the transfer transistor are connected in common, the photo Before reading the signal charge from the diode, after setting the terminal voltage of the floating diffusion portion to a predetermined voltage, power is applied to the power line, and the terminal voltage of the floating diffusion portion of each of the CMOS sensors, A solid-state imaging device, wherein the voltage is boosted simultaneously from the predetermined voltage by a capacitance between the gate electrode of the amplification MOS transistor and the power supply terminal . The voltage between the terminals of the floating diffusion part in all CMOS sensors is boosted at the same time, and the signal current is sequentially detected as a reference current at the timing when the voltage between the terminals is saturated by boosting, and after the reading of the reference current is completed, A controller that sequentially turns on the transfer transistor in all CMOS sensors to transfer the signal charge from the photodiode to the floating diffusion unit, and sequentially detects the signal current after the signal charge transfer as an exposure current; The solid-state imaging device according to claim 1 . When the capacitance value of the grounding capacitance of the gate electrode of the amplification MOS transistor is CFD and the capacitance value of the gate electrode of the amplification MOS transistor and the terminal to which the power is supplied is CVV,
CVV> CFD
The solid-state imaging device according to claim 2, wherein the amplification MOS transistor is formed so that A reset transistor interposed between the floating diffusion part and a power source;
4. The solid-state imaging device according to claim 2, wherein a reset process using a voltage between terminals of the floating diffusion unit as a power supply voltage is performed before the control unit boosts the voltage. 5. A drain transistor provided between the photodiode and the power supply for controlling accumulation of the signal charge generated by the photodiode being exposed;
3. The control circuit according to claim 2, wherein when the control unit does not accumulate the signal charge generated by exposure in the photodiode, the drain transistor is turned on to transfer the signal charge generated to the power source. 5. The solid-state imaging device according to claim 4. In the imaging method of the solid-state imaging device having a plurality of CMOS sensors arranged in a matrix and having a global shutter function,
In the CMOS sensor,
A photodiode photoelectrically converts incident light to generate charges, accumulates the generated charges as signal charges,
The signal charge transferred from the photodiode is accumulated in the floating diffusion portion via a transfer transistor interposed between the photodiode and the floating diffusion portion,
The amplification MOS transistor outputs a signal current corresponding to the signal charge accumulated in the floating diffusion portion,
At the time of boosting before reading out the signal charge from the photodiode, the power supply of the amplification MOS transistor is supplied to all the CMOS sensors of the solid-state imaging device after setting the terminal voltage of the floating diffusion portion to a predetermined voltage. A power supply voltage is simultaneously supplied to the terminal to be boosted, and the terminal voltage of the floating diffusion portion of each of the CMOS sensors is simultaneously boosted from the predetermined voltage by the capacitance of the gate electrode of the amplification MOS transistor and the power supply terminal, An imaging method for a solid-state imaging device, wherein a signal for transferring the signal charge is applied to the gate electrodes of all the transfer transistors of the solid-state imaging device at the time of shutter.   A bipedal walking robot equipped with the solid-state imaging device according to any one of claims 1 to 5.

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