JP5451740B2 - 多重ビット相変化メモリセル - Google Patents
多重ビット相変化メモリセル Download PDFInfo
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- JP5451740B2 JP5451740B2 JP2011502475A JP2011502475A JP5451740B2 JP 5451740 B2 JP5451740 B2 JP 5451740B2 JP 2011502475 A JP2011502475 A JP 2011502475A JP 2011502475 A JP2011502475 A JP 2011502475A JP 5451740 B2 JP5451740 B2 JP 5451740B2
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- phase change
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- 230000015654 memory Effects 0.000 title claims description 101
- 239000000463 material Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 18
- 239000012782 phase change material Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 1
- 208000031481 Pathologic Constriction Diseases 0.000 description 6
- 208000037804 stenosis Diseases 0.000 description 6
- 230000036262 stenosis Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910018321 SbTe Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000005387 chalcogenide glass Substances 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Description
複数のメモリ領域に対して、1個のセルあたり1ビット以上のビットを付与し、これによりデータ保存量を増加することができる。
本発明の実施形態を単なる例示として、以下図面につき説明する。
図面は概略図であり、縮尺通りではない。図面において、同一または類似の要素には同一符号を付して示す。
Claims (10)
- 第1電極および第2電極間に延在する相変化メモリ材料と、および
前記第1および第2の電極間に延在する相変化メモリ材料内の複数個のメモリ領域と
を備え、
前記複数個のメモリ領域は直列に配置され、前記相変化メモリ材料内の各メモリ領域は、相変化材料、ビア充填材料又は低抵抗材料の少なくともいずれか1つからなる領域の狭窄部として形成し、
前記複数個のメモリ領域は、それぞれ、電流および/または電圧の適切なプログラミング条件を加えることで低抵抗状態または高抵抗状態にプログラムすることができ、また
前記異なるメモリ領域は、高抵抗状態の異なる抵抗、および高抵抗状態と低抵抗状態の間で変換するための異なるプログラミング条件を有する
ことを特徴とする相変化メモリセル。 - 請求項1記載の相変化メモリセルにおいて、
各メモリ領域は、各リセット電流により結晶性低抵抗状態から非結晶性高抵抗状態に変換し、各セット電圧により非結晶性高抵抗状態から結晶性低抵抗状態に変換することができ、
各メモリ領域の幾何学的形状を異ならせることで、各メモリ領域の高抵抗状態における抵抗を異ならせ、各リセット電流および各セット電圧もそれぞれ異ならせる、相変化メモリセル。 - 請求項1または2記載の相変化メモリセルにおいて、各メモリ領域は、一定の幅および一定の長さを有し、幅に対する長さの各アスペクト比および各幅は、双方とも前記複数個のメモリ領域毎に異なるものとした、相変化メモリセル。
- 請求項1または2記載の相変化メモリセルにおいて、各メモリ領域は、テーパ付き形状にし、それぞれ異なる最小幅を有する、相変化メモリセル。
- 請求項1〜4のいずれか一項に記載の相変化メモリセルにおいて、相変化メモリ材料は、第1および第2の電極間で基板上に側方に延在する、相変化メモリセル。
- 請求項1〜4のいずれか一項に記載の相変化メモリセルにおいて、前記第1および第2の電極は底部電極および頂部電極とし、相変化メモリ材料は、メモリ領域を定義する異なる幅を有する複数個のビア内を充填し、また前記頂部電極と底部電極との間に延在させ、前記ビアを絶縁材料によって包囲する、相変化メモリセル。
- 請求項1〜6のうちいずれか一項に記載の相変化メモリセルにおいて、メモリ領域間に少なくとも1個の中間領域を有し、前記少なくとも1個の中間領域はメモリ領域よりも低抵抗の材料で形成する、相変化メモリセル。
- 請求項1乃至7のいずれか一項に記載の相変化メモリセルを操作する方法において、
前記第1および第2の電極間の抵抗を測定するステップと、および
どのメモリ領域が高抵抗状態であり、またどのメモリ領域が低抵抗状態であるかを、前記測定した抵抗から決定するステップと
を備えることを特徴とする、相変化メモリセルの操作方法。 - 請求項8記載の相変化メモリセル操作方法において、さらに、
前記メモリ領域のうち選択した1個またはそれ以上のメモリ領域を高抵抗状態に変化させるためのリセット電流を選択するステップと、
前記選択したメモリ領域を高抵抗状態に変化させるために、前記リセット電流を前記電極間に加えるステップと
を備えた、相変化メモリセル操作方法。 - 請求項8または9記載の相変化メモリセル操作方法において、さらに、
選択した1個またはそれ以上のメモリ領域を低抵抗状態に変化させるセット電流を選択するステップと、
前記選択したメモリ領域を低抵抗状態に変化させる、前記セット電流を前記電極間に加えるステップと
を備える、相変化メモリセル操作方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08103304.5 | 2008-04-01 | ||
EP08103304 | 2008-04-01 | ||
PCT/IB2009/051327 WO2009122347A2 (en) | 2008-04-01 | 2009-03-30 | Multiple bit phase change memory cell |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011518431A JP2011518431A (ja) | 2011-06-23 |
JP5451740B2 true JP5451740B2 (ja) | 2014-03-26 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2011502475A Active JP5451740B2 (ja) | 2008-04-01 | 2009-03-30 | 多重ビット相変化メモリセル |
Country Status (5)
Country | Link |
---|---|
US (1) | US8649213B2 (ja) |
EP (1) | EP2272113B1 (ja) |
JP (1) | JP5451740B2 (ja) |
CN (1) | CN101981721B (ja) |
WO (1) | WO2009122347A2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2260520B1 (en) | 2008-04-01 | 2015-02-25 | Nxp B.V. | Vertical phase change memory cell |
US9601689B2 (en) | 2014-09-11 | 2017-03-21 | Kabushiki Kaisha Toshiba | Memory device |
US10424374B2 (en) | 2017-04-28 | 2019-09-24 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
US10693065B2 (en) | 2018-02-09 | 2020-06-23 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US10424730B2 (en) | 2018-02-09 | 2019-09-24 | Micron Technology, Inc. | Tapered memory cell profiles |
US10541364B2 (en) | 2018-02-09 | 2020-01-21 | Micron Technology, Inc. | Memory cells with asymmetrical electrode interfaces |
US10854813B2 (en) | 2018-02-09 | 2020-12-01 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US11404635B2 (en) * | 2019-08-29 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory stacks and methods of forming the same |
US11309490B2 (en) * | 2020-02-10 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory devices and methods of forming the same |
US20220199899A1 (en) * | 2020-12-22 | 2022-06-23 | International Business Machines Corporation | Transfer length phase change material (pcm) based bridge cell |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7485891B2 (en) | 2003-11-20 | 2009-02-03 | International Business Machines Corporation | Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory |
KR100564608B1 (ko) | 2004-01-29 | 2006-03-28 | 삼성전자주식회사 | 상변화 메모리 소자 |
KR100657956B1 (ko) | 2005-04-06 | 2006-12-14 | 삼성전자주식회사 | 다치 저항체 메모리 소자와 그 제조 및 동작 방법 |
US7488968B2 (en) | 2005-05-05 | 2009-02-10 | Ovonyx, Inc. | Multilevel phase change memory |
JP2008541475A (ja) * | 2005-05-19 | 2008-11-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Pcmセルにおける“先溶融”領域の制御方法及びそれにより得た装置 |
CN101213612B (zh) | 2005-05-19 | 2010-09-29 | Nxp股份有限公司 | 相变存储单元和形成相变存储单元的方法 |
US7973384B2 (en) | 2005-11-02 | 2011-07-05 | Qimonda Ag | Phase change memory cell including multiple phase change material portions |
EP1966841B1 (en) | 2005-12-20 | 2010-09-08 | Nxp B.V. | A vertical phase change memory cell and methods for manufacturing thereof |
US20080019257A1 (en) * | 2006-07-18 | 2008-01-24 | Jan Boris Philipp | Integrated circuit with resistivity changing material having a step-like programming characteristitic |
US8084799B2 (en) | 2006-07-18 | 2011-12-27 | Qimonda Ag | Integrated circuit with memory having a step-like programming characteristic |
US7688618B2 (en) * | 2006-07-18 | 2010-03-30 | Qimonda North America Corp. | Integrated circuit having memory having a step-like programming characteristic |
JP4492816B2 (ja) | 2006-10-03 | 2010-06-30 | 株式会社半導体理工学研究センター | 多値記録相変化メモリ素子、多値記録相変化チャンネルトランジスタおよびメモリセルアレイ |
CN101267016A (zh) * | 2008-02-15 | 2008-09-17 | 中国科学院上海微系统与信息技术研究所 | 相变存储器单元器件的结构的改进 |
-
2009
- 2009-03-30 WO PCT/IB2009/051327 patent/WO2009122347A2/en active Application Filing
- 2009-03-30 US US12/935,656 patent/US8649213B2/en active Active
- 2009-03-30 CN CN200980111512.2A patent/CN101981721B/zh active Active
- 2009-03-30 JP JP2011502475A patent/JP5451740B2/ja active Active
- 2009-03-30 EP EP09726759.5A patent/EP2272113B1/en active Active
Also Published As
Publication number | Publication date |
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CN101981721A (zh) | 2011-02-23 |
WO2009122347A3 (en) | 2009-11-26 |
WO2009122347A2 (en) | 2009-10-08 |
JP2011518431A (ja) | 2011-06-23 |
EP2272113A2 (en) | 2011-01-12 |
US20120069645A1 (en) | 2012-03-22 |
US8649213B2 (en) | 2014-02-11 |
EP2272113B1 (en) | 2015-11-25 |
CN101981721B (zh) | 2013-12-25 |
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