CN103069603A - 单掩模相变存储器工艺集成 - Google Patents
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Abstract
本发明的一个实例实施例示出了一种制造相变存储器单元的方法。所述方法包括在绝缘衬底内形成非亚光刻过孔。所述绝缘衬底嵌在与半导体晶片的第一金属化层(金属1)相同的层上,并包括底部和侧壁。亚光刻孔穿过所述非亚光刻过孔的所述底部形成并延伸至掩埋导电材料。用导电非相变材料填充所述亚光刻孔。此外,在所述非亚光刻过孔内沉积相变材料。
Description
技术领域
本发明涉及计算机存储器,特别地,非易失性相变存储器。
背景技术
主要有两类计算机存储器:非易失性存储器和易失性存储器。频繁输入能量以保持信息在非易失性存储器中是不必要的,但在易失性存储器中却是需要的。非易失性存储器器件的实例是只读存储器(ROM),闪存电可擦除只读存储器,铁电随机存取存储器,磁随机存储器以及相变存储器。易失性存储器的实例包括动态随机存取存储器(DRAM)和静态随机存取存储器(SRAM)。本发明涉及相变存储器(也称为PCM、PRAM、PCRAM、双向联合存储器(Ovonic Unified Memory)、硫系(Chalcogenide)RAM以及C-RAM)。
在相变存储器中,信息存储在可操纵成不同相位的材料中。其中每个相位拥有可用于存储信息的不同的电特性。由于其具备可检测的电阻差异,非晶和晶体相位是用于比特存储(1和0)的典型相位。特别地,非晶相位相对于晶体相位具有较高电阻。此外,非晶相位和晶体相位在相变材料中是可逆的。
硫系玻璃是一类常用作相变材料的材料。此类材料包含硫族(元素周期表第16族)元素和更正电元素。硒(Se)和碲(Te)是该族中产生相变存储器单元过程中用于制造硫系玻璃最常用的两种半导体材料。一个此类实例有Ge2Sb2Te5(GST)、SbTe和In2Se3。然而,一些相变材料不使用硫族元素,例如GeSb。因此,只要其可保持独立的非晶和晶体态,多种材料可用于相变材料单元中。
相变存储器单元通过给予足够强以致改变内部相变材料相位的脉冲实现编程。这一般通过提供穿过相变材料的电脉冲实现。由于欧姆加热,相变材料改变其相位。后沿转换快的相对高强度、短持续时间电流脉冲导致相变材料融化并迅速冷却。相变材料没有时间形成有组织的晶体,从而产生了非晶固态相。一个相对低强度、长持续时间的脉冲允许相变材料缓慢加热和冷却,从而晶体为晶体相。调整脉冲的强度和持续时间以制造用于单存储器单元的多比特存储的变化电阻级。
相变存储器通过提供不足以实现编程,即改变材料相的脉冲实现读操作。该脉冲的电阻可读取为“1”或“0”。非晶相具有较高电阻,通常用于代表二进制0。晶体相位具有较低电阻,可用于代表二进制1。在存在变化电阻级的单元中,相位可用于表示,例如,“00”“01”“10”和“11”。
发明内容
本发明的一个实例实施例是一种用于制造相变存储器单元的方法。该方法包括在绝缘衬底内形成亚光刻过孔。该绝缘衬底嵌在与半导体晶片的第一金属化层(金属1)相同的层上,并包括底部和侧壁。亚光刻孔穿过非亚光刻过孔的底部形成并延伸到掩埋导电材料。亚光刻孔用导电非易失性相变材料填充。此外,相变材料沉积到非亚光刻过孔中。
本发明的另一实例实施例是一种半导体晶片中的相变存储器单元。该半导体晶片包括第一金属化层(金属1)。该相变存储器单元包括限定非亚光刻过孔的绝缘衬底。该非亚光刻过孔位于第一金属化层上并包括底部和侧壁。中间绝缘材料位于绝缘衬底之下。该中间绝缘层材料限定了穿过非亚光刻过孔的底部的亚光刻孔。底部电极位于该亚光刻孔中,并且由导电非相变材料构成。该非亚光刻过孔包括位于其中的相变材料。该相变材料电耦合到底部电极。衬里沿非亚光刻过孔的侧壁设置。该衬里被电耦合到相变存储器材料并由导电非相变材料构成。
附图说明
认为是本发明的主旨被特别的指出并在说明书结论部分的权利要求中被明确主张。结合附图考虑下列相似描述,本发明的上述以及其他目的、特征以及优点将显而易见。
图1示出了本发明构思的相变存储器的一个实例的截面图。
图2示出了本发明构思的相变存储器的示例制造流程。
图3A-J示出了在由本发明的一个实施例构思的一个制造过程期间的相变存储器单元的截面图。
图4A-N示出了在由本发明的另一实施例构思的制造过程期间的相变存储器单元的截面图。
具体实施方式
参考本发明的实施例描述本发明。对于本发明的整个说明书,可以参考附图。
图1示出了本发明构思的实例相变存储器单元102的截面图。存储器单元102被制造在包含第一层金属化层(金属1)106的半导体晶片104上。
存储器单元102包括绝缘衬底108,例如二氧化硅(SiO2)。此外,绝缘衬底108限定了非亚光刻过孔110。即,非亚光刻过孔110至少是用于制造晶片104的光刻技术的一个特征尺寸的宽度。非亚光刻过孔110置于第一层金属化层106上并包括底部112和侧壁114。非亚光刻过孔110的尺寸应使得其长高比(即,纵横比)不大于一。
存储器单元102还包括置于绝缘衬底108之下的中间绝缘材料116。中间绝缘材料116可由如氮化硅(SiN)的材料组成。中间绝缘材料116限定了穿过非亚光刻过孔底部112的亚光刻孔118。即,亚光刻孔118小于用于制造晶片104的光刻技术的一个特征尺寸的宽度。在一个实例中,亚光刻孔118的宽度约为光刻特征尺寸的三分之一。
底电极120置于亚光刻孔118之中。底电极120由导电非相变材料组成。这里所使用的导电非相变材料是在施加热时不会被配置为可编程到不同电阻状态的导电材料。导电非相变材料可为,例如,氮化钛(TiN)、钨(W)、氮化钽(TaN)。
非亚光刻过孔全部或至少部分地用相变材料122填充。如上所述,相变材料122可为,Ge2Sb2Te5(GST)、SbTe以及In2Se3,并在施加热时会配置为可编程到非晶(高阻)态或晶体(低阻)态。此外,相变材料122电耦合到底电极120。
衬里124由导电非相变材料组成,如TiN、W和TaN,沿非亚光刻过孔110的侧壁114设置衬里124。衬里124也电耦合到相变材料122并电耦合到置于相变材料122之上的顶电极126。此外,顶电极126电耦合到相变材料122。存储器单元102可包括直接置于绝缘衬底108之上的化学机械抛光(CMP)停止层128。
图2示出了制作本发明构思的相变存储器单元的实例制造流程图202。两个实例制造过程起始点在图3A和图4A中示出。
在步骤204中,CMP停止层置于绝缘衬底之上。在图4A中,所述CMP停止层128被示出为在绝缘衬底108之上。CMP停止层128可由SiN组成。如以下将详细讨论的,CMP停止层128配置为阻止对绝缘衬底108的化学机械抛光。
图3A的实例不包括CMP停止层。在该实例中,SiN的第一牺牲层302置于绝缘衬底108之上。返回至图4A,存储器单元还包括Si的第二牺牲层402和SiO2的第三牺牲层404。
之后,在步骤206,在绝缘衬底108中的非亚光刻过孔110被形成。公知光刻工艺均可使用,同时采用光致抗蚀剂掩模304来蚀刻非亚光刻过孔110。非亚光刻过孔110的宽度为所采用光刻技术的至少一个特征尺寸。如上所述,非亚光刻过孔110包括底部和侧壁。此外,绝缘衬底108嵌在与半导体晶片的第一层金属化层(金属1)的相同的层上(见图1)。
之后,在步骤208,光致抗蚀剂掩模304被去除以及底切非亚光刻过孔110以便在非亚光刻过孔110之上形成突出部(overhang)306。图3B和4B示出了在非亚光刻过孔110之上形成的突出部306。在一个实施例中,执行缓冲氧化物蚀刻(BOE)以便选择性蚀刻非亚光刻过孔的侧壁。
之后,在步骤210,亚光刻掩模在非亚光刻过孔110中形成。如图3C和4C所示,该步骤可包括用保形材料308填充非亚光刻过孔110从而在非亚光刻过孔110中形成钥匙孔310。图4D示出了保形材料308的蚀刻从而在所述非亚光刻过孔110中的所述保形材料形成了阶梯间隔物406。基于氯的蚀刻化学如80sccm Ar/80sccm Cl2/2sccm O2可使用以相对于氮化硅中间绝缘层116选择性地蚀刻硅阶梯间隔物406。
之后,在步骤212,穿过非亚光刻过孔110底部形成亚光刻孔118。如图3D所示,亚光刻孔118延伸穿过中间绝缘层116到掩埋导电材料314。换言之,在保形材料308中的钥匙孔腔310向下转移到中间绝缘层116。在一个实施例中,亚光刻孔118约为所采用光刻技术的特征尺寸宽度的三分之一。
回到图4E,示出了低选择性贯穿蚀刻步骤。该蚀刻可由低水平聚合氟碳化合物化学组成,如CF4or CHF3。该蚀刻去除了在中间绝缘层116中的在亚光刻孔118之下的材料。该蚀刻还蚀刻了在较大过孔结构顶上的SiN的第一牺牲层302,从而将第二牺牲层402(见图4F)暴露。典型的蚀刻速率趋势为SiO2>SiN>Si,但所有三种材料将具有合适的蚀刻速率。
因此,如图3D和4F所示,在阶梯间隔物406下的中间绝缘层116被选择性蚀刻,停止在掩埋导电材料314上。该操作包括基于甲基氟/氧的选择性SiN蚀刻。该蚀刻化学可为CH3F/O2。该步骤相对Si高度选择性地蚀刻SiN并且对SiO2具有较好的选择性。因此,该过程将向下蚀刻钥匙孔,穿过SiN中间绝缘层116并去除该区域任何残留的SiN。硅阶梯间隔物406用作该步骤的蚀刻掩模(由于蚀刻化学的高度选择性)。
在图4G中,示出了存储器单元,其中阶梯间隔物从非亚光刻过孔110去除。选择性硅蚀刻可在此操作期间采用。该蚀刻还去除第二牺牲层402。
之后,在步骤214,亚光刻孔118被填充以导电非相变材料316。如上所述,导电非相变材料316为,例如TiN、W和TaN。产生的结构在图3E和4H中示出。在一个实施例中,用导电非相变材料316填充亚光刻孔118包括在亚光刻孔118内执行非相变材料316的化学气相沉积(CVD)。
之后,在步骤216中,将沿非亚光刻过孔的侧壁的导电非相变材料318与填充在亚光刻孔中的导电非相变材料316电隔离。如图3F和4I中示出的,这些结构可通过例如的执行反应离子蚀刻(RIE)以从非亚光刻过孔110底部去除导电非相变材料实现。
之后,在步骤218中,相变材料122被沉积在非亚光刻过孔110中。该步骤包括执行相变材料122的物理气相沉积(PVD)或溅射,如图3G和4J所示。
由于非亚光刻过孔110在宽度上是至少一个特征尺寸,该过程在所述相变存储器单元的制造期间有利避免了相变材料的CVD或原子层沉积(ALD)(或其他先进的相变材料填充工艺)。此外,由于仅在底电极之上的小体积的相变材料被重设,存储器单元设计允许工作过程的低功耗。该低功耗反过来实现了更小的支撑电子结构(如功率晶体管)在存储器单元中的使用。因此,可实现单管芯上的更高密度的存储器单元。
之后,在步骤220,凹陷在非亚光刻过孔110中的相变材料122。该操作在图3H和4K中示出。在一种实例中,步骤220是通过化学机械抛光(CMP)实现。在图4L中,CMP停止层128被配置为防止绝缘衬底108的化学机械抛光。如上所述,CMP停止层128可由SiN构成。
之后,在步骤222,顶电极126被沉积在非亚光刻过孔110中的相变材料之上。在图3I和4M中,顶电极126被示出为电耦合到相变材料122。
在步骤224,凹陷在非亚光刻过孔110之上的顶电极126。在一个实施例中,通过顶电极126上的第二CMP实施步骤224,如图3J和4N所示。在图4N中,CMP停止层128被配置为防止绝缘衬底108的化学机械抛光。
虽然已经描述了本发明,但应该理解,本领域的技术人员在现在和以后都可以做出落入下面权利要求的范围内的各种改善和增强。因此,权利要求应理解为维持对首次描述的本发明的适当保护。
Claims (20)
1.一种用于制造相变存储器单元的方法,所述方法包括:
在绝缘衬底内形成非亚光刻过孔,所述绝缘衬底嵌在与半导体晶片的第一金属化层(金属1)相同的层上,所述非亚光刻过孔包括底部和侧壁;
形成穿过所述非亚光刻过孔的所述底部的亚光刻孔,所述亚光刻孔延伸至掩埋导电材料;
用导电非相变材料填充所述亚光刻孔;以及
在所述非亚光刻过孔中沉积相变材料。
2.根据权利要求1的方法,进一步在所述非亚光刻过孔之上形成突出部。
3.根据权利要求2的方法,其中形成所述突出部物包括进行缓冲氧化物蚀刻以使所述非亚光刻过孔的所述侧壁被选择性蚀刻。
4.根据权利要求1的方法,还包括在所述非亚光刻过孔内形成亚光刻掩模。
5.根据权利要求4的方法,其中形成所述亚光刻掩模包括:
用保形材料填充所述非亚光刻过孔以在所述非亚光刻过孔内形成钥匙孔腔;
蚀刻穿过所述保形材料以便在所述非亚光刻过孔内通过所述保形材料形成阶梯间隔物。
6.根据权利要求5的方法,其中形成所述亚光刻孔包括选择性蚀刻在所述阶梯间隔物之下的中间绝缘层。
7.根据权利要求1的方法,其中用所述导电非相变材料填充所述亚光刻孔包括在所述亚光刻孔内执行所述导电非相变材料的化学气相沉积。
8.根据权利要求1的方法,还包括电隔离沿所述非亚光刻过孔的所述侧壁的所述导电非相变材料与填充在所述亚光刻孔中的所述导电非相变材料。
9.根据权利要求8的方法,其中电隔离所述导电非相变材料包括进行反应离子蚀刻以从所述非亚光刻过孔的所述底部去除所述导电非相变材料。
10.根据权利要求1的方法,其中在所述非亚光刻过孔中沉积所述相变材料包括在所述非亚光刻过孔内进行所述相变材料的物理气相沉积。
11.根据权利要求1的方法,还包括凹陷所述非亚光刻过孔内的所述相变材料。
12.根据权利要求11的方法,其中凹陷在所述非亚光刻过孔内的所述相变材料包括在所述相变材料上进行化学机械抛光。
13.根据权利要求1的方法,还包括在所述非亚光刻过孔内的所述相变材料之上沉积顶电极。
14.根据权利要求13的方法,还包括凹陷在所述非亚光刻过孔之上的所述顶电极。
15.根据权利要求14的方法,其中凹陷在所述非亚光刻过孔之上的所述顶电极包括在所述顶导电材料上执行化学机械抛光。
16.根据权利要求15的方法,还包括在所述绝缘衬底之上沉积CMP停止层,所述CMP停止层被配置为防止所述绝缘衬底的所述化学机械抛光。
17.一种在半导体晶片中的相变存储器单元,所述半导体晶片包括第一金属化层(金属1),所述相变存储器单元包括:
限定非亚光刻过孔的绝缘衬底,所述非亚光刻过孔位于所述第一金属化层上并包括底部和侧壁;
位于所述绝缘衬底之下的中间绝缘材料,所述中间绝缘材料限定穿过所述非亚光刻过孔的所述底部的亚光刻孔;
位于所述亚光刻孔内的底电极,所述底电极由导电非相变材料构成;
位于所述非亚光刻过孔内并电耦合到所述底电极的相变材料;以及
沿所述非亚光刻过孔的所述侧壁设置并电耦合到所述相变材料的衬里,所述衬里由所述导电非相变材料构成。
18.根据权利要求17中的相变存储器单元,还包括位于所述相变材料之上并电耦合到所述相变材料的顶电极。
19.根据权利要求17中的相变存储器单元,其中所述非亚光刻过孔的所述长度与所述非亚光刻过孔的所述高度的比率不大于一。
20.根据权利要求17中的相变存储器单元,还包括直接位于所述绝缘衬底之上的CMP停止层。
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