JP5442573B2 - 改良された閾値下の振れを有するトンネル電界効果トランジスタ - Google Patents
改良された閾値下の振れを有するトンネル電界効果トランジスタ Download PDFInfo
- Publication number
- JP5442573B2 JP5442573B2 JP2010225452A JP2010225452A JP5442573B2 JP 5442573 B2 JP5442573 B2 JP 5442573B2 JP 2010225452 A JP2010225452 A JP 2010225452A JP 2010225452 A JP2010225452 A JP 2010225452A JP 5442573 B2 JP5442573 B2 JP 5442573B2
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- Japan
- Prior art keywords
- gate dielectric
- field effect
- effect transistor
- source
- channel
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/211—Gated diodes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/021—Manufacture or treatment of gated diodes, e.g. field-controlled diodes [FCD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US24918609P | 2009-10-06 | 2009-10-06 | |
| US61/249,186 | 2009-10-06 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011100986A JP2011100986A (ja) | 2011-05-19 |
| JP2011100986A5 JP2011100986A5 (enExample) | 2013-11-07 |
| JP5442573B2 true JP5442573B2 (ja) | 2014-03-12 |
Family
ID=43037878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010225452A Active JP5442573B2 (ja) | 2009-10-06 | 2010-10-05 | 改良された閾値下の振れを有するトンネル電界効果トランジスタ |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8304843B2 (enExample) |
| EP (1) | EP2309544B1 (enExample) |
| JP (1) | JP5442573B2 (enExample) |
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| US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
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| US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
| US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
| US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
| US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
| US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
| JP5404671B2 (ja) | 2011-02-14 | 2014-02-05 | 株式会社東芝 | 半導体装置 |
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| US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
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| US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
| US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
| US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
| US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
| CN103688362B (zh) * | 2011-07-22 | 2017-03-29 | 国际商业机器公司 | 隧道场效应晶体管 |
| US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
| US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
| WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
| US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
| US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
| US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
| US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
| US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
| US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
| US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
| US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
| US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
| US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
| US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
| US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
| US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
| US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
| US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
| US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
| US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
| JP5717706B2 (ja) | 2012-09-27 | 2015-05-13 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US9431068B2 (en) | 2012-10-31 | 2016-08-30 | Mie Fujitsu Semiconductor Limited | Dynamic random access memory (DRAM) with low variation transistor peripheral circuits |
| US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
| US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
| US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
| US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
| US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
| US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
| US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
| US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
| WO2014142856A1 (en) * | 2013-03-14 | 2014-09-18 | Intel Corporation | Leakage reduction structures for nanowire transistors |
| US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
| US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
| JP6083704B2 (ja) * | 2013-03-25 | 2017-02-22 | 国立研究開発法人産業技術総合研究所 | トンネルfetのデバイスシミュレーション方法及びシステム並びにトンネルfetのコンパクトモデル設計方法及びコンパクトモデル |
| US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
| US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
| KR102189055B1 (ko) * | 2014-03-27 | 2020-12-09 | 인텔 코포레이션 | 포켓을 가진 p-터널링 전계 효과 트랜지스터 디바이스 |
| CN106030817B (zh) * | 2014-03-28 | 2019-11-22 | 英特尔公司 | 具有可变带隙沟道的隧穿场效应晶体管 |
| US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
| US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
| KR101792615B1 (ko) * | 2016-03-17 | 2017-11-02 | 서울대학교산학협력단 | 비대칭 채널과 게이트 절연막을 갖는 터널링 전계효과 트랜지스터 및 그 제조방법 |
| US10141436B2 (en) * | 2016-04-04 | 2018-11-27 | Purdue Research Foundation | Tunnel field effect transistor having anisotropic effective mass channel |
| US20180138307A1 (en) * | 2016-11-17 | 2018-05-17 | Globalfoundries Inc. | Tunnel finfet with self-aligned gate |
| CN108807266B (zh) * | 2017-05-03 | 2021-03-09 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
| US10276679B2 (en) * | 2017-05-30 | 2019-04-30 | Vanguard International Semiconductor Corporation | Semiconductor device and method for manufacturing the same |
| CN109087943A (zh) * | 2017-06-13 | 2018-12-25 | 联华电子股份有限公司 | 隧穿场效晶体管结构与其制作方法 |
| FR3086101B1 (fr) | 2018-09-17 | 2022-07-08 | Ion Beam Services | Dispositif d'amelioration de la mobilite des porteurs dans un canal de mosfet sur carbure de silicium |
| CN115498031B (zh) * | 2022-10-08 | 2025-04-04 | 西安邮电大学 | 一种基于硅基的可调控双栅隧穿场效应晶体管 |
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| US6127235A (en) * | 1998-01-05 | 2000-10-03 | Advanced Micro Devices | Method for making asymmetrical gate oxide thickness in channel MOSFET region |
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| US7880160B2 (en) * | 2006-05-22 | 2011-02-01 | Qimonda Ag | Memory using tunneling field effect transistors |
| EP1900681B1 (en) * | 2006-09-15 | 2017-03-15 | Imec | Tunnel Field-Effect Transistors based on silicon nanowires |
| EP1901354B1 (en) | 2006-09-15 | 2016-08-24 | Imec | A tunnel field-effect transistor with gated tunnel barrier |
| JP2008252086A (ja) * | 2007-03-12 | 2008-10-16 | Interuniv Micro Electronica Centrum Vzw | ゲートトンネル障壁を持つトンネル電界効果トランジスタ |
| US8148718B2 (en) * | 2007-05-31 | 2012-04-03 | The Regents Of The University Of California | Low voltage transistors |
| US7829945B2 (en) * | 2007-10-26 | 2010-11-09 | International Business Machines Corporation | Lateral diffusion field effect transistor with asymmetric gate dielectric profile |
-
2010
- 2010-08-30 EP EP10174506.5A patent/EP2309544B1/en active Active
- 2010-09-08 US US12/877,909 patent/US8304843B2/en active Active
- 2010-10-05 JP JP2010225452A patent/JP5442573B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US8304843B2 (en) | 2012-11-06 |
| EP2309544B1 (en) | 2019-06-12 |
| EP2309544A2 (en) | 2011-04-13 |
| US20110079860A1 (en) | 2011-04-07 |
| JP2011100986A (ja) | 2011-05-19 |
| EP2309544A3 (en) | 2012-10-10 |
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