JP5437558B2 - Electromagnetic noise countermeasure structure for printed circuit boards - Google Patents

Electromagnetic noise countermeasure structure for printed circuit boards Download PDF

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JP5437558B2
JP5437558B2 JP2006310063A JP2006310063A JP5437558B2 JP 5437558 B2 JP5437558 B2 JP 5437558B2 JP 2006310063 A JP2006310063 A JP 2006310063A JP 2006310063 A JP2006310063 A JP 2006310063A JP 5437558 B2 JP5437558 B2 JP 5437558B2
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浩之 木股
康弘 山中
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Mitsubishi Electric Corp
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Description

この発明は、プリント基板の電磁ノイズ対策構造に関するものである。   The present invention relates to an electromagnetic noise countermeasure structure for a printed circuit board.

プリント基板に形成されるグランド(以降、「GND」と記す)には、電源GND、リターン電流を流すためのシグナルGND、基準電位を与えるためのフレームGNDなどがある。さらに、シグナルGNDでも、アナログ回路でのGNDとデジタル回路でのGNDとがあり、そして、例えばアナログ回路では扱う周波数帯域などに応じたGNDが設けられる。デジタル回路においても同様である。   The ground (hereinafter referred to as “GND”) formed on the printed circuit board includes a power supply GND, a signal GND for supplying a return current, a frame GND for supplying a reference potential, and the like. Further, the signal GND includes a GND in an analog circuit and a GND in a digital circuit, and a GND corresponding to a frequency band handled by the analog circuit, for example, is provided. The same applies to digital circuits.

これらのGNDは、相互間を直接直接すると互いに他の回路にノイズとして干渉することになるので、相互間を直接接続できない異種GNDである。一方、これらの異種GNDが隣接する場合に、GND間を非接続の状態にしておくと、その2つのGND間の電位が安定せず、電磁ノイズの発生源となり、外部からのノイズ侵入に弱いという問題がある。   These GNDs are heterogeneous GNDs that cannot be directly connected to each other because they directly interfere with each other as noise when they are directly connected to each other. On the other hand, when these different types of GND are adjacent to each other, if the GND is not connected, the potential between the two GNDs is not stable, becomes a source of electromagnetic noise, and is vulnerable to noise intrusion from the outside. There is a problem.

プリント基板に形成されるGNDに対する電磁ノイズ対策方法として、例えば特許文献1では、アナログ回路とデジタル回路とが混在して実装される多層基板において、表面層に設けられるアナロググランドと中間層に設けられるデジタルグランドとの間をコンデンサにて接続することで、層間ノイズを低減する方法が開示されている。   As an electromagnetic noise countermeasure method for GND formed on a printed circuit board, for example, in Patent Document 1, in a multi-layer board in which an analog circuit and a digital circuit are mixedly mounted, an analog ground provided on a surface layer and an intermediate layer are provided. A method of reducing interlayer noise by connecting a capacitor to the digital ground is disclosed.

また、例えば特許文献2では、アナログ回路ブロックとデジタル回路ブロックとが同一平面上に混在して実装される回路基板において、アナログ回路ブロックとデジタル回路ブロックとの間に複数の電子部品(電解コンデンサ)を並べて配置して相互間をシールドすることで、デジタル回路ブロックからアナログ回路ブロックへの高周波ノイズの混入を低減する方法が開示されている。   For example, in Patent Document 2, in a circuit board on which an analog circuit block and a digital circuit block are mixedly mounted on the same plane, a plurality of electronic components (electrolytic capacitors) are provided between the analog circuit block and the digital circuit block. Are arranged side by side and shielded from each other to thereby reduce the mixing of high frequency noise from the digital circuit block to the analog circuit block.

特開2001−284828号公報JP 2001-284828 A 特開2006−165035号公報JP 2006-165035 A

しかしながら、上記の特許文献1,2に記載の電磁ノイズ対策方法は、いずれもシグナルGNDに対する電磁ノイズ対策方法であり、しかもアナログGNDとデジタルGNDとの間に対するものであり、同種回路内に隣接して存在する異種GND間や、隣接するフレームGNDとシグナルGNDとの間など、上記した各種の異種GNDが隣接する場合に適用できる有効な電磁ノイズ対策方法は未だ提案されていない。   However, the electromagnetic noise countermeasure methods described in Patent Documents 1 and 2 are both electromagnetic noise countermeasure methods for signal GND, and between analog GND and digital GND, and are adjacent to the same kind of circuit. There has not yet been proposed an effective electromagnetic noise countermeasure method that can be applied when the above-mentioned various types of GND are adjacent to each other, such as between different types of GND, or between adjacent frame GND and signal GND.

近年では、電子機器から放射される不要放射による電磁障害EMI(Electro Magnetic Interference)に関する国際規格CISPR(国際無線障害特別委員会)や、外部からの侵入電磁波に対する耐性(イミュニティ)に関する国際規格IEC(国際電気標準会議)が定められ、遵守すべきとの要請がある。   In recent years, the international standard CISPR (International Radio Interference Special Committee) for electromagnetic interference EMI (Electro Magnetic Interference) due to unwanted radiation radiated from electronic equipment, and the international standard IEC (International There is a request that the Electrotechnical Commission) be established and observed.

この発明は、上記に鑑みてなされたものであり、同一の基板面上に特性の違いから直接接続できない2つのGNDが存在する場合に、その2つのGNDによる不要放射ノイズの低減と外来ノイズに対する耐性向上とを可能にするプリント基板の電磁ノイズ対策構造を得ることを目的とする。   The present invention has been made in view of the above. When there are two GNDs that cannot be directly connected due to a difference in characteristics on the same substrate surface, reduction of unnecessary radiation noise due to the two GNDs and external noise can be prevented. An object of the present invention is to obtain an electromagnetic noise countermeasure structure for a printed circuit board that can improve resistance.

上述した目的を達成するために、この発明は、プリント基板において、同一の基板面上に隣接して配置される2つのグランドが特性の違いから直接接続できない場合に、前記2つのグランド間は、抵抗素子、コンデンサ、インダクタのうちのいずれか一つの回路素子を介して接続されていることを特徴とする。   In order to achieve the above-described object, in the present invention, when two grounds arranged adjacent to each other on the same board surface cannot be directly connected due to a difference in characteristics, the two grounds are It is connected through any one circuit element of a resistor element, a capacitor, and an inductor.

この発明によれば、特性の違いから直接接続できない2つのGND間の電位を安定化することができるので、不要放射ノイズの低減と外来ノイズに対する耐性向上とを図ることができる。   According to the present invention, since the potential between two GNDs that cannot be directly connected due to the difference in characteristics can be stabilized, it is possible to reduce unnecessary radiation noise and improve resistance to external noise.

この発明によれば、同一の基板面上に特性の違いから直接接続できない2つのGNDが存在する場合に、その2つのGNDによる不要放射ノイズの低減と外来ノイズに対する耐性向上とを可能にするという効果を奏する。   According to the present invention, when there are two GNDs that cannot be directly connected due to a difference in characteristics on the same substrate surface, it is possible to reduce unnecessary radiation noise and improve resistance to external noise by the two GNDs. There is an effect.

以下に図面を参照して、この発明にかかるプリント基板の電磁ノイズ対策構造の好適な実施の形態を詳細に説明する。   Exemplary embodiments of an electromagnetic noise countermeasure structure for a printed circuit board according to the present invention will be described below in detail with reference to the drawings.

実施の形態1.
図1は、この発明の実施の形態1によるプリント基板の電磁ノイズ対策構造の構成を示す概念図である。図1において、プリント基板の同一の基板面に隣接して配置されるGND1とGND2は、その特性の違いから直接接続できない異種GNDである。このような異種GNDとしては、電源GNDとシグナルGND、フレームGNDとシグナルGND、アナログ回路でのGNDとデジタル回路でのGND、同種回路内に隣接して存在する異種GNDなど各種ある。
Embodiment 1 FIG.
FIG. 1 is a conceptual diagram showing the configuration of an electromagnetic noise countermeasure structure for a printed circuit board according to Embodiment 1 of the present invention. In FIG. 1, GND1 and GND2 arranged adjacent to the same board surface of the printed circuit board are heterogeneous GNDs that cannot be directly connected due to their characteristic differences. As such a different type GND, there are various types such as a power supply GND and a signal GND, a frame GND and a signal GND, a GND in an analog circuit and a GND in a digital circuit, and a different type GND adjacent to the same type circuit.

このような場合に、この実施の形態1では、GND1とGND2との間を、抵抗素子、コンデンサ、インダクタのうちのいずれか一つの回路素子3を介して接続し、その2つのGND間の電位を安定化させ、電磁ノイズ対策が採れるようにする。   In such a case, in the first embodiment, GND1 and GND2 are connected via a circuit element 3 of any one of a resistance element, a capacitor, and an inductor, and the potential between the two GNDs is connected. So that countermeasures against electromagnetic noise can be taken.

この構成によれば、国際規格CIRPR(publ.11等:放射電磁界),IEC(61000−4−2等:静電気イミュニティ)をクリアすることを目的とするか、その他の不要放射ノイズの低減を目的とするか、外来ノイズに対する耐性向上を目的とするか、に応じて適切な回路素子を選択することで、簡単に対応することができる。   According to this configuration, the objective is to clear international standards CIRPR (publ.11 etc .: radiated electromagnetic field), IEC (61000-4-2 etc .: electrostatic immunity) or to reduce other unnecessary radiated noise. It is possible to easily cope with this problem by selecting an appropriate circuit element depending on whether the purpose is to improve the resistance against external noise.

具体例を示すと、国際規格CIRPR(publ.11等)に定める30MHz〜1000MHzの放射ノイズ低減要請に応える場合は、回路素子3に1000pF〜10000pFのコンデンサを用いる。特に、GND1がオーディオ回路で、GND2がデジタル回路である場合、1000pF〜10000pFの容量値とすることにより、オーディオ回路に影響を与える1MHz以下のノイズ成分をデジタル回路からオーディオ回路に混入させることなく、30MHz〜1000MHzのノイズの成分のみを対策することが可能となる。   As a specific example, a capacitor of 1000 pF to 10000 pF is used for the circuit element 3 in response to a request for reduction of radiation noise of 30 MHz to 1000 MHz defined in the international standard CIRPR (publ. 11 etc.). In particular, when GND1 is an audio circuit and GND2 is a digital circuit, by setting a capacitance value of 1000 pF to 10000 pF, a noise component of 1 MHz or less that affects the audio circuit is not mixed from the digital circuit to the audio circuit. Only a noise component of 30 MHz to 1000 MHz can be taken.

また、IEC(61000−4−2等)に定める静電気イミュニティ向上の要請に応える場合は、回路素子3に1000pF〜1μFのコンデンサを用いる。   Further, in order to meet the demand for improvement in electrostatic immunity defined by IEC (61000-4-2 etc.), a capacitor of 1000 pF to 1 μF is used for the circuit element 3.

また、その他の静電気イミュニティ向上を図る場合として、回路素子3に抵抗値が100Ω〜1kΩ程度の抵抗素子を用い、当該抵抗素子にてノイズ成分を消散させる。また、その他の不要放射ノイズの低減策として、GND1とGND2との間を物理的に絶縁するが、DCレベルは同一にしたいケースでは、回路素子3にインダクタを用い、微少な直流電流が流れるようにする。   In order to improve other static electricity immunity, a resistance element having a resistance value of about 100Ω to 1 kΩ is used for the circuit element 3, and a noise component is dissipated by the resistance element. In addition, as another measure for reducing unnecessary radiation noise, GND1 and GND2 are physically insulated, but in the case where the DC level is desired to be the same, an inductor is used for the circuit element 3 so that a minute direct current flows. To.

以上のように、この実施の形態1によれば、同一の基板面に直接接続できない2つのGNDが存在する場合でも、その間の電位を安定化することができるので、電磁ノイズ放射の低減、及び電磁ノイズイミュニティの向上を図ることができる。これによって、従来対策が困難であった国際規格CIRPR(publ.11等:放射電磁界),IEC(61000−4−2等:静電気イミュニティ)への適合の可能性を高くすることができる。また、その他の不要放射ノイズの低減やノイズイミュニティの向上にも効果が期待できる可能性がある。   As described above, according to the first embodiment, even when there are two GNDs that cannot be directly connected to the same substrate surface, the potential between them can be stabilized. Electromagnetic noise immunity can be improved. As a result, it is possible to increase the possibility of conforming to the international standards CIRPR (publ.11 etc .: radiated electromagnetic field) and IEC (61000-4-2 etc .: electrostatic immunity), which have conventionally been difficult to take countermeasures. In addition, there is a possibility that an effect can be expected to reduce other unnecessary radiation noise and improve noise immunity.

実施の形態2.
図2は、この発明の実施の形態2によるプリント基板の電磁ノイズ対策構造の構成を示す概念図である。図2に示すように、この実施の形態2では、2つのグランド1,2は、対向辺に複数のパッド4がそれぞれ設けられ、必要に応じて選択したパッド間を回路素子3で接続できるようにしている。
Embodiment 2. FIG.
FIG. 2 is a conceptual diagram showing a configuration of an electromagnetic noise countermeasure structure for a printed circuit board according to Embodiment 2 of the present invention. As shown in FIG. 2, in the second embodiment, the two grounds 1 and 2 are provided with a plurality of pads 4 on opposite sides, respectively, so that the circuit elements 3 can connect between the pads selected as necessary. I have to.

この構成によれば、最適な接続箇所及び個数を適宜選択することができる。   According to this configuration, the optimum connection location and number can be selected as appropriate.

実施の形態3.
図3は、この発明の実施の形態3によるプリント基板の電磁ノイズ対策構造の構成を示す概念図である。図3に示すように、この実施の形態3では、図2に示した構成において2つのグランド1,2の間を、電磁誘導を避けるに足る間隔5だけ離すようにしている。
Embodiment 3 FIG.
FIG. 3 is a conceptual diagram showing a configuration of an electromagnetic noise countermeasure structure for a printed circuit board according to Embodiment 3 of the present invention. As shown in FIG. 3, in the third embodiment, the two grounds 1 and 2 in the configuration shown in FIG. 2 are separated by an interval 5 sufficient to avoid electromagnetic induction.

この構成によれば、ノイズ対策上の不確定要因を排除することが可能となる。なお、この実施の形態3では、実施の形態2への適用例を示したが、実施の形態1に同様に適用できることは言うまでもない。   According to this configuration, it becomes possible to eliminate uncertain factors for noise countermeasures. In the third embodiment, an example of application to the second embodiment has been described. Needless to say, the third embodiment can be similarly applied.

以上のように、この発明にかかるプリント基板の電磁ノイズ対策構造は、同一の基板面上に特性の違いから直接接続できない2つのGNDが存在する場合に、その2つのGNDによる不要放射ノイズの低減と外来ノイズに対する耐性向上とを可能にするのに有用であり、特に、低放射電磁波レベルと高ノイズ耐性が同時に求められる電子機器(例えば、自動車搭載用電子機器、パーソナルコンピュータ及びその周辺機器、電子医療機器、計測機器、産業用機器など)に適用するのに適している。   As described above, the printed circuit board electromagnetic noise countermeasure structure according to the present invention reduces unnecessary radiation noise caused by two GNDs when there are two GNDs that cannot be directly connected due to the difference in characteristics on the same board surface. In particular, electronic devices that are required to have low radiation electromagnetic wave level and high noise resistance at the same time (for example, electronic devices for automobiles, personal computers and their peripheral devices, electronic devices) Suitable for application to medical equipment, measuring equipment, industrial equipment, etc.

この発明の実施の形態1によるプリント基板の電磁ノイズ対策構造の構成を示す概念図である。It is a conceptual diagram which shows the structure of the electromagnetic noise countermeasure structure of the printed circuit board by Embodiment 1 of this invention. この発明の実施の形態2によるプリント基板の電磁ノイズ対策構造の構成を示す概念図である。It is a conceptual diagram which shows the structure of the electromagnetic noise countermeasure structure of the printed circuit board by Embodiment 2 of this invention. この発明の実施の形態3によるプリント基板の電磁ノイズ対策構造の構成を示す概念図である。It is a conceptual diagram which shows the structure of the electromagnetic noise countermeasure structure of the printed circuit board by Embodiment 3 of this invention.

符号の説明Explanation of symbols

1,2 グランド(GND)
3 回路素子
4 パッド
5 間隙
1, 2 Ground (GND)
3 circuit element 4 pad 5 gap

Claims (1)

プリント基板において、同一の基板面上に隣接して配置される2つのグランドが特性の違いから直接接続できない場合に、
前記2つのグランド間は、抵抗素子、コンデンサ、インダクタのうちのいずれか一つの回路素子を介して接続されており、
前記2つのグランドは、それぞれ、対向辺における互いに対応する位置に複数の凸状パターンを有し、
前記2つのグランドは、一方における前記複数の凸状パターンのうち選択された1つの凸状パターンと他方における前記複数の凸状パターンのうち選択された1つの凸状パターンとの間のみが回路素子で接続されており、
前記回路素子は、100Ω〜1kΩの抵抗素子であり、
前記2つのグランドは、それぞれ、略矩形状であり、
前記2つのグランドにおいて、一方のグランドにおける複数の凸状パターンは、他方のグランドに対向する辺上に互いに離間しながら配列されているとともに、他方のグランドに近づくように延びており、他方のグランドに対向する辺に沿った方向の幅として第1の幅及び前記第1の幅より広い第2の幅を含むとともに、他方のグランドに対向する辺に沿った方向の離間する間隔として第1の間隔及び前記第1の間隔より広い第2の間隔を含み、
前記2つのグランドにおいて、他方のグランドにおける複数の凸状パターンは、一方のグランドに対向する辺上に互いに離間しながら配列されているとともに、一方のグランドに近づくように延びており、一方のグランドに対向する辺に沿った方向の幅として前記第1の幅及び前記第2の幅を含むとともに、一方のグランドに対向する辺に沿った方向の離間する間隔として前記第1の間隔及び前記第2の間隔を含む
ことを特徴とするプリント基板の電磁ノイズ対策構造。
In a printed circuit board, when two grounds arranged adjacent to each other on the same board surface cannot be directly connected due to a difference in characteristics,
The two grounds are connected via a circuit element of any one of a resistance element, a capacitor, and an inductor,
Each of the two grounds has a plurality of convex patterns at positions corresponding to each other on opposite sides,
The two grounds are circuit elements only between one convex pattern selected from the plurality of convex patterns on one side and one convex pattern selected from the plurality of convex patterns on the other side. Connected with
The circuit element is a resistance element of 100Ω to 1 kΩ,
Each of the two grounds has a substantially rectangular shape,
In the two grounds, the plurality of convex patterns in one ground are arranged on the side facing the other ground while being spaced apart from each other, and extend so as to approach the other ground. The first width and the second width wider than the first width are included as the width in the direction along the side facing the first, and the first spacing is the spacing in the direction along the side facing the other ground . An interval and a second interval wider than the first interval;
In the two grounds, the plurality of convex patterns in the other ground are arranged on the side facing the one ground while being spaced apart from each other, and extend so as to approach one ground. The first width and the second width are included as the width in the direction along the side facing the first, and the first distance and the second width are separated as the spacing in the direction along the side facing the one ground . An electromagnetic noise countermeasure structure for a printed circuit board, characterized by comprising an interval of 2 .
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JP6377393B2 (en) * 2014-04-10 2018-08-22 三菱重工サーマルシステムズ株式会社 Electric compressor control system and electric compressor for vehicle air conditioner equipped with the same
KR20160011867A (en) * 2014-07-23 2016-02-02 엘에스산전 주식회사 Inverter assembly without galvanic isolation
CN109565176A (en) * 2016-08-03 2019-04-02 博世株式会社 Control device
CN109845087B (en) * 2016-10-25 2022-06-17 三菱电机株式会社 Power control device, motor, air conditioner, and method for manufacturing motor
KR101999509B1 (en) * 2017-03-24 2019-07-11 미쓰비시덴키 가부시키가이샤 Circuit board
CN117063618B (en) * 2021-04-06 2024-05-17 三菱电机株式会社 Printed circuit board
CN113939074A (en) * 2021-09-24 2022-01-14 合肥联宝信息技术有限公司 Anti-interference circuit board and electronic equipment
WO2024166265A1 (en) * 2023-02-08 2024-08-15 日立Astemo株式会社 Electronic control device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63194386A (en) * 1987-02-09 1988-08-11 三菱電機株式会社 Printed wiring board for flexible disc device
JPH02187093A (en) * 1989-01-13 1990-07-23 Toshiba Corp Printed wiring board
JPH0523566U (en) * 1991-09-02 1993-03-26 カシオ計算機株式会社 Printed wiring boards for electronic devices
JP3666967B2 (en) * 1996-01-12 2005-06-29 キヤノン株式会社 Ground connection structure
JP3546904B2 (en) * 1996-03-27 2004-07-28 東芝ライテック株式会社 Discharge lamp lighting device
JPH10242601A (en) * 1997-02-25 1998-09-11 Canon Inc Method for connecting printed wiring board with housing, and electronic apparatus
JPH11177274A (en) * 1997-12-08 1999-07-02 Canon Inc Method for connecting printed wiring board and cable and box-like body, and electronic apparatus
JP3782577B2 (en) * 1998-04-15 2006-06-07 キヤノン株式会社 Multilayer printed wiring board and electronic apparatus provided with the wiring board
JP2000074740A (en) * 1998-08-31 2000-03-14 Sumitomo Metal Mining Co Ltd Pyroelectric infrared ray sensor
JP4005794B2 (en) * 2001-11-14 2007-11-14 株式会社日立製作所 Electronic control unit for automobile
JP2005294511A (en) * 2004-03-31 2005-10-20 Hitachi Electronics Service Co Ltd Electronic circuit unit having connector terminal and circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4177642A4 (en) * 2020-07-01 2024-07-31 Canon Electron Tubes & Devices Co Ltd Radiation detector

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