JP5396053B2 - Semiconductor electrostatic protection device - Google Patents

Description

  The present invention relates to a semiconductor electrostatic protection device, in particular, an electrostatic protection device (element) formed by connecting a plurality of stages of transistors in series, and relates to a configuration for adjusting the turn-on voltage.

  FIG. 6 shows a configuration of a semiconductor protection device disclosed in Patent Document 1 below. In this conventional example, a low-concentration P-type impurity region 11 formed on the surface of a P-type semiconductor substrate 10 and a low-concentration P-type are shown. High-concentration P-type impurity region 12 to be a contact portion of impurity region 11, source portion 13 (14: source terminal) made of high-concentration N-type impurity region, high-concentration P-type impurity region 15, and high-concentration N-type impurity A drain portion 16 (17: drain terminal) composed of a region and a conductive film 18 formed on a semiconductor substrate in a region sandwiched between the drain portion 16 and the high-concentration P-type impurity region 12. By setting the impurity concentration of the concentration P-type impurity region 12 and the low concentration P-type impurity region 11 and the widths of the insulating films 19, 20 and the conductive film 18, the turn-on voltage and the holding voltage are set to desired values. It has been made.

FIG. 7 shows a current-voltage characteristic of the thick oxide film transistor. In this transistor, when the voltage of the drain portion (16) starts to rise, the current value gradually increases. When the voltage rises, the NPN bipolar structure composed of the drain portion (16) -the low-concentration P-type impurity region (11) -the source portion (13) is turned on at the turn-on voltage and reaches the holding voltage. In Patent Document 1 described above, the holding voltage and the turn-on voltage are set to desired values.
JP 2003-179145 A

  However, in the conventional example of FIG. 6, in order to obtain a desired holding voltage and turn-on voltage, the impurity concentration of the impurity region (drain portion 16, high-concentration P-type impurity region 12 and low-concentration P-type impurity region 11) and the insulating film ( 19 and 20) and the width of the conductive film (18) are set, it is necessary to add or change process conditions (addition of a photomask, etc.), and there is a problem that manufacturing is complicated.

  FIG. 8 shows another configuration of a conventional semiconductor electrostatic protection device for setting a holding voltage to a desired value. As shown in FIG. 8, this device uses a transistor while connecting an emitter and a collector. 23 and 24 are connected in series between a collector part (terminal) 25 and an emitter part (terminal) 26, and the bases of these transistors 23 and 24 are connected to the emitter part 26, so that the transistors are arranged in two stages. Thus, the holding voltage is made higher than in the case of one stage. The holding voltage can be variably set to a desired value by increasing or decreasing the number of stages of the transistors.

  However, as shown in FIG. 8, when the number of transistor stages is increased in order to increase the holding voltage, the turn-on voltage also increases at the same time, and the turn-on voltage cannot be set to a desired value alone. .

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor static circuit capable of adjusting a turn-on voltage to a desired value in a configuration in which a plurality of transistors are connected in series in order to variably set a holding voltage. It is to provide an electric protection device.

In order to achieve the above object, according to the first aspect of the present invention, a plurality of transistors are connected in series while connecting an emitter and a collector, and the collector of the first transistor is connected to a terminal to which a surge is applied. and, in the semiconductor electrostatic protection device for grounding the emitter of the transistor of the last stage, respectively between the emitter-collector junction point between the transistors of the collector and the respective stages of the transistors of the first stage, for the turn-on voltage setting resistor Is connected.
According to a second aspect of the present invention, a MOS transistor is used as the transistor, and the drain is a collector, the back gate is a base, and the source is an emitter.
According to a third aspect of the present invention, when N stages of transistors are connected in series, the resistance value of the turn-on setting resistor is set so as to decrease from the N-1 stage to the first stage. And

  According to the configuration of the present invention, the turn-on voltage is adjusted to a desired value by appropriately selecting the values of the turn-on voltage setting resistors from the first stage to the (N-1) th stage, and a small resistance value can be selected. For example, the turn-on voltage decreases, and if a larger value is selected, the turn-on voltage increases. This turn-on voltage setting resistor can be provided by forming a wiring such as polysilicon between the collector of the first stage transistor and the emitter-collector connection point between the transistors of each stage. The resistance value for a desired turn-on voltage is set by adjusting the length and thickness of the layer.

  According to the semiconductor electrostatic protection device of the present invention, in a configuration in which a plurality of stages of transistors are connected in series in order to variably set the holding voltage, the turn-on voltage can be set to a desired value only by disposing the turn-on voltage setting resistor. There is an effect that can be adjusted. In addition, since the turn-on voltage setting resistor can be provided by using the wiring resistance, there is an advantage that it is not necessary to add or change process conditions, and manufacturing is facilitated.

FIG. 1 shows the configuration of a semiconductor electrostatic protection device according to a first embodiment of the present invention. As shown in the drawing, this first embodiment is a first-stage bipolar transistor (hereinafter simply referred to as a transistor). to) the emitter of TR ₁ in the form of connecting the collector of the second stage transistor TR _2, between the collector portion (terminal) 1 and the emitter portion (terminal) 2, the transistor _TR 1 to Tr _n n stages Are connected in series. Further, all the bases of the N-stage transistors TR _{1 to} TR _n are connected in common, and this common line is connected to the emitter section 2 of the N-stage transistor. According to such a configuration, a desired holding voltage can be set by arbitrarily selecting the number of stages of the N-stage transistors TR _{1 to} TR _n .

The collector of the resistor _{R 1,} also the first stage transistor TR ₁ between the emitter-collector connection point between the first stage transistor TR ₁ the collector and the first stage transistor _TR 1 -2 stage transistor TR ₂ and 2 The resistor R ₂ is connected between the emitter-collector connection point between the _third -stage transistor TR _{2 and the} third-stage transistor TR _{3 so that} the emitter between the collector of the first-stage transistor TR ₁ and the transistors at each stage. The turn-on voltage setting resistors R _{1 to} R _n-1 are connected to the collector connection points, respectively. These resistors R _{1 to} R _n-1 are formed by the length and thickness of the connection wiring (layer).

The first embodiment has the above configuration, and its operation will be described below.
Emitter 2 of the N-th stage transistor TR _n is grounded, a positive surge to the collector unit 1 of the first stage transistor TR ₁ is considered a case where it is applied, applied from the collector unit 1 of the first stage transistor TR ₁ The positive surge thus applied is first applied to the collector section 3 of the N-th stage transistor TR _n via the resistor R _n−1 . Then, the surge applied to the collector unit 3 of the N-th stage transistor TR _n, caused the yield to the collector unit 3 of the N-th stage transistor TR _n, holes of the hole-electron pairs generated by this N If the product of the resistance value of the P-type impurity region forming the base of the current and the n-th transistor TR _n flowing when passing through the base of the stage transistor TR _n is about 1V, the n-th stage transistor TR _n Turns on.

Next, since the N-th stage transistor TR _n is turned on, the potential of the emitter section (3) of the N−1-th stage transistor TR _n−1 before the N-th stage approaches the ground potential. the surge applied to the collector portion of the eye transistor TR _n-1, caused the yield to the collector of the n-1 stage transistor TR _n-1, n-1 on the same principle as the n-th stage transistor TR _n described above The positive surge applied from the collector part 1 of the first-stage transistor TR ₁ is finally switched from the first-stage transistor TR ₁ to the N-stage transistor TR _n so that the stage transistor TR _n−1 is turned on. The semiconductor circuit is protected from static electricity by flowing out of the emitter section 2 after passing through.

In the configuration of this first embodiment, reducing the value of the resistor R ₁ to R _n, the amount of surge applied to the collector unit 3 of the N-th stage transistor TR _n increases, the N-th stage transistor TR _n lower the turn-on voltage, consequently it is possible to reduce the turn-on voltage of the first stage transistor TR _1. Therefore, by selecting the values of the resistors R _{1 to} R _n , the turn-on voltage can be set to a desired value in the configuration in which the holding voltage is set according to the number of stages of the transistors TR _{1 to} TR _n .

FIG. 2 shows the configuration of the second embodiment. This second embodiment is a MOS (NMOS) type transistor using a lateral bipolar transistor.
In the second embodiment, as shown in FIG. 2, in the N-stage MOS transistors MT _{1 to} MT _n , the drain is replaced with the collector of the transistor of the first embodiment, the back gate is the base, and the source is replaced with the emitter. N-stage MOS transistors MT _{1 to} MT _n are connected in series between the drain portion 4 and the source portion 5. Further, all the gates and back gates of MT ₁ to MT _n of the N-stage MOS transistor are connected in common, and the common line of these gates and back gate is the source portion 5 of the N- _th MOS transistor MT _n. Connected to. According to such a configuration, a desired holding voltage can be set by arbitrarily selecting the number of stages of the N-stage MOS transistors MT _{1 to} MT _n .

The resistor r ₁ is connected between the drain of the first-stage MOS transistor MT _{1 and} the drain of the second-stage MOS transistor MT ₂ , and the drain of the first-stage MOS transistor MT ₁ and each drain Turn-on voltage setting resistors r _{1 to} r _n−1 are connected between the drains of the MOS transistors of the stage.

The second embodiment has the above configuration, and its operation will be described below.
The above N-th stage MOS (NMOS) transistors source unit 5 of the MT _n is grounded, a positive surge to the first-stage drain portion 4 of the MOS transistor MT ₁ Consider a case where it is applied, the first stage MOS type positive surge applied from the drain portion 4 of the transistor MT ₁ is applied to the drain portion 6 of the via resistance _{r n-1} n-th MOS transistor MT _n. Then, the surge applied to the drain section 6 of the N-th stage MOS transistor MT _n, breakdown occurs in the drain portion 6 of the N-th stage MOS transistor MT _n, of the hole-electron pairs generated by this product of about 1V between the resistance value of the P-type impurity region holes to form a back gate of the current and the n-th stage MOS transistor MT _n flowing when passing through the back gate of the n-th stage MOS transistor MT _n becomes the degree, n-th MOS transistor MT _n is turned on. That is, the drain of the MOS transistor MT _n, the back gate, respectively source collector, base, parasitic NPN when regarded emitter turned on.

Then, by the N-th stage MOS transistor MT _n is turned on, close to the potential ground potential of the source of the N-1 stage MOS transistor _{MT n-1,} N-1 stage MOS transistor MT _n the surge applied to the drain of _-1, breakdown occurs in the drain part of the n-1 stage MOS transistor _{MT n-1,} so that this n-1 stage MOS transistor _{MT n-1} is turned on a manner, by flowing from the source region 5 positive surge applied from the drain portion 4 passes through the n-th stage MOS transistor MT _n the first stage MOS transistor MT _1, the semiconductor circuit is protected from static electricity The

FIG. 3 shows the configuration of a device composed of two-stage MOS transistors MT ₁ and MT ₂ for the purpose of trial evaluation in the configuration of the second embodiment, and the current-voltage characteristic result in this device is shown. FIG. 4 shows an enlarged view of the turn-on voltage portion of the current-voltage characteristic results of FIG.

In FIG. 4 and FIG. 5, 101 characteristics before resistance connection, 102 characteristics when the resistance value of the resistor _{r 1} and 1 k [Omega, 103 is the characteristics when the resistance value of the resistor _{r 1} was 100 [Omega, as can be seen from this figure, when connecting the resistance r ₁ of 1kΩ is the turn-on voltage than that before connection of resistors r ₁ is lowered, and when connecting the resistance r ₁ of 100Ω, as compared with the case of 1kΩ As a result, the turn-on voltage decreased. Therefore, in the second embodiment, by selecting the resistance values of the resistors _r 1 ~r _n, in the configuration to set the holding voltage by the number of stages of MOS transistors _MT 1 to MT _n, the turn-on voltage to the desired value It becomes possible to set.

The resistance value of the resistor _R 1 to R _n or _r 1 ~r _n in each example are all may be used as the same value as described above, the transistor _TR 1 to Tr _n or _MT 1 ~ N stages in MT _n, as directed from the n-1 stage resistor R _n-1 in the first stage resistor R _1, it may be set so that the resistance value decreases according to the setting of such a resistance value, As it goes to the first stage, it turns on at an earlier time, so that the electrostatic protection device can be operated quickly.

It is a circuit diagram which shows the structure of the semiconductor electrostatic protection apparatus which concerns on 1st Example of this invention. It is a circuit diagram which shows the structure of the semiconductor electrostatic protection apparatus which concerns on 2nd Example. It is a circuit diagram which shows the structure for carrying out trial manufacture evaluation with the semiconductor electrostatic protection apparatus of 2nd Example. It is a graph which shows the current-voltage characteristic of the semiconductor electrostatic protection apparatus of the structure of FIG. FIG. 5 is a graph in which a turn-on region in the current-voltage characteristic of FIG. 4 is enlarged. It is a figure which shows the structure of the conventional semiconductor protection apparatus. It is a graph which shows the current-voltage characteristic of a thick oxide film transistor. It is a circuit diagram which shows the other structure of the conventional semiconductor electrostatic protection apparatus.

Explanation of symbols

1, 3 ... collector part, 2 ... emitter part,
4, 6 ... Drain part, 5 ... Source part,
TR _{1 to} TR _n ... bipolar transistors,
MT _{1 to} MT _n ... MOS (NMOS) type transistors,
_{R 1 ~R n, r 1 ~r} n ... resistance.

Claims (3)

A semiconductor electrostatic protection device in which a plurality of stages of transistors are connected in series, a collector of the first stage transistor is connected to a terminal to which a surge is applied, and an emitter of the last stage transistor is grounded while connecting the emitter and collector In
Respectively, the semiconductor electrostatic protection apparatus characterized by connecting a turn-on voltage setting resistor between the emitter-collector junction point between the transistors of the collector and the respective stages of the transistors of the first stage.   2. The semiconductor electrostatic protection device according to claim 1, wherein a MOS transistor is used as the transistor, and the drain is a collector, the back gate is a base, and the source is an emitter.   3. The N-stage transistor is set so as to decrease as the resistance value of the turn-on setting resistor increases from the (N-1) th stage to the first stage when N-stage transistors are connected in series. The semiconductor electrostatic protection device as described.

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