JP5384693B2 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
JP5384693B2
JP5384693B2 JP2012106193A JP2012106193A JP5384693B2 JP 5384693 B2 JP5384693 B2 JP 5384693B2 JP 2012106193 A JP2012106193 A JP 2012106193A JP 2012106193 A JP2012106193 A JP 2012106193A JP 5384693 B2 JP5384693 B2 JP 5384693B2
Authority
JP
Japan
Prior art keywords
adhesive layer
semiconductor package
substrate
semiconductor
functional element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012106193A
Other languages
Japanese (ja)
Other versions
JP2012182481A (en
Inventor
さやか 平船
道和 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2012106193A priority Critical patent/JP5384693B2/en
Publication of JP2012182481A publication Critical patent/JP2012182481A/en
Application granted granted Critical
Publication of JP5384693B2 publication Critical patent/JP5384693B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Description

本発明は、半導体パッケージに係り、より詳細には、機能素子が一方の面に配された半導体基板と、該一方の面上に該機能素子と重ならない領域に複数の独立した空間を有する接着層を介して接合された保護基板を備える半導体パッケージに関する。 The present invention relates to a semiconductor package, and more particularly, the functional element having a semiconductor substrate arranged on one surface, a space more independent in a region which does not overlap with the functional elements on one surface the It relates to a semiconductor package comprising a protective substrate which is bonded via the adhesive layer.

従来、イメージセンサ等の機能素子を備えてなる半導体パッケージとして、製造工程中及び使用中の外部雰囲気から機能素子を保護するために、半導体基板上に配された機能素子を保護基板により封止してなる構造が広く用いられている。
たとえば、特許文献1には、機能素子を一方の面に設け、該機能素子と電気的に接続され他方の面まで至る貫通電極を有する半導体基板と、キャップ基板とが、該機能素子の周囲に配された封止材を用いて該機能素子が内側となるように接合された構成の半導体パッケージ及びその製造方法が記載されている。
Conventionally, as a semiconductor package including a functional element such as an image sensor, the functional element disposed on the semiconductor substrate is sealed with a protective substrate in order to protect the functional element from the external atmosphere during the manufacturing process and in use. This structure is widely used.
For example, in Patent Document 1, a functional substrate is provided on one surface, a semiconductor substrate having a through electrode that is electrically connected to the functional device and extends to the other surface, and a cap substrate are disposed around the functional device. A semiconductor package having a structure in which the functional elements are bonded to each other by using an arranged sealing material and a manufacturing method thereof are described.

機能素子が一方の面に配された半導体基板と、該一方の面上に接着層を介して接合された保護基板とを備える半導体パッケージの構造においては、接合の信頼性を向上させることが重要である。
しかしながら、半導体基板に接着層を形成し熱圧着で保護基板と接合する際には、様々な理由により、接着層と基板界面に気泡が発生する。該気泡の発生は、たとえば、接着樹脂を熱硬化する際に発生するガスや、接着樹脂や基板表面の凹凸に起因するものである。接着層が接着エリア全域に形成された構成とした場合、その気泡により接合不良、ひいては信頼性の低下をまねく虞があった。
In the structure of a semiconductor package including a semiconductor substrate in which a functional element is arranged on one surface and a protective substrate bonded to the one surface via an adhesive layer, it is important to improve the reliability of the bonding It is.
However, when an adhesive layer is formed on the semiconductor substrate and bonded to the protective substrate by thermocompression bonding, bubbles are generated at the interface between the adhesive layer and the substrate for various reasons. The generation of the bubbles is caused by, for example, gas generated when the adhesive resin is thermally cured, or unevenness on the surface of the adhesive resin or the substrate. In the case where the adhesive layer is formed in the entire adhesive area, there is a risk that the air bubbles may cause poor bonding and eventually decrease reliability.

特開2006−19428号公報JP 2006-19428 A

本発明は、上記事情に鑑みてなされたものであり、半導体基板と保護基板の間に接着層を配して両者を接合した際に、接着層と各基板との界面における気泡の発生を低減するとともに、発生した気泡が接合状態の不良を誘導しにくい構造を備えた半導体パッケージを提供することを第一の目的とする。
また、本発明は、半導体基板と保護基板の間に接着層を配して両者を接合した際に、接着層と各基板との界面における気泡の発生を低減し、良好な接合状態を簡便に形成できる半導体パッケージの製造方法を提供することを第二の目的とする。
The present invention has been made in view of the above circumstances, and reduces the generation of bubbles at the interface between the adhesive layer and each substrate when the adhesive layer is disposed between the semiconductor substrate and the protective substrate and bonded together. In addition, a first object is to provide a semiconductor package having a structure in which the generated bubbles are less likely to induce a defective bonding state.
In addition, the present invention reduces the generation of bubbles at the interface between the adhesive layer and each substrate when an adhesive layer is disposed between the semiconductor substrate and the protective substrate and bonded to each other. It is a second object to provide a method for manufacturing a semiconductor package that can be formed.

前記課題を解決するため、本発明の請求項1に係る導体パッケージは、光学デバイスが一方の面に配された半導体基板と、該一方の面上に透明な接着層を介して接合された透明な保護基板とを備える半導体パッケージであって、前記光学デバイスは、前記半導体基板と前記接着層とによって封止され、前記接着層は、前記光学デバイスと重ならない領域に複数の第一空間を有し、該第一空間は互いに独立して、かつ、外部空間から孤立して配されており、全ての前記第一空間は各々、前記半導体基板から前記保護基板に至るように、前記接着層の厚み方向に貫通していることを特徴とする。 To solve the above problems, a semi-conductor package according to claim 1 of the present invention includes a semiconductor substrate having an optical device is disposed on one side, are joined via a transparent adhesive layer on one face the A semiconductor package comprising a transparent protective substrate, wherein the optical device is sealed by the semiconductor substrate and the adhesive layer, and the adhesive layer has a plurality of first spaces in a region that does not overlap the optical device. The first spaces are arranged independently of each other and isolated from the external space, and all the first spaces are respectively connected to the protective layer from the semiconductor substrate to the protective substrate. It penetrates in the thickness direction .

本発明の請求項2に係る半導体パッケージは、請求項1において、前記第一空間が前記半導体基板の外周域に配されていることを特徴とする。
本発明の請求項3に係る半導体パッケージは、請求項1又は2において、前記接着層が前記光学デバイスと重なる領域に第二空間を有することを特徴とする。
本発明の請求項4に係る半導体パッケージは、請求項1乃至3のいずれか一項において、前記接着層が接着機能を備えた樹脂からなることを特徴とする。
A semiconductor package according to a second aspect of the present invention is the semiconductor package according to the first aspect, wherein the first space is arranged in an outer peripheral region of the semiconductor substrate.
A semiconductor package according to a third aspect of the present invention is characterized in that, in the first or second aspect, the adhesive layer has a second space in a region overlapping the optical device .
A semiconductor package according to a fourth aspect of the present invention is characterized in that, in any one of the first to third aspects, the adhesive layer is made of a resin having an adhesive function.

本発明の請求項5に係る半導体パッケージの製造方法は、機能素子が一方の面に配された半導体基板を用い、該一方の面において該機能素子と重ならない領域に、複数の第一空間が互いに独立するとともに、外部空間から孤立するように、内在してなる接着層を形成する工程Aと、前記接着層を介して保護基板を取り付ける工程Bとを、少なくとも備えたことを特徴とする。   A method for manufacturing a semiconductor package according to claim 5 of the present invention uses a semiconductor substrate in which functional elements are arranged on one surface, and a plurality of first spaces are formed in a region that does not overlap the functional elements on the one surface. It is characterized by comprising at least a process A for forming an inherent adhesive layer so as to be independent from each other and isolated from the external space, and a process B for attaching a protective substrate via the adhesive layer.

本発明の請求項6に係る半導体パッケージの製造方法は、請求項5において、前記工程Aが前記第一空間とともに、前記機能素子と重なる領域に第二空間が内在するように前記接着層を設けることを特徴とする。   The method for manufacturing a semiconductor package according to claim 6 of the present invention is the method for manufacturing a semiconductor package according to claim 5, wherein the adhesive layer is provided so that the second space is included in a region where the step A and the functional element overlap with the first space. It is characterized by that.

本発明に係る半導体パッケージ(請求項1)は、半導体基板と保護基板とを接合する接着層に複数の互いに独立し、かつ、外部空間から孤立した第一空間を内在させて設けたことにより、これらの第一空間は接着樹脂を熱硬化させて接着層を形成した際に発生する出ガスのたまり場として機能する。ゆえに、接着層と各基板との界面付近から第一空間へ出ガスは誘導されるので、この界面付近に出ガスは残存しにくくなり、ひいては界面における気泡の発生を低減させることができる(第一効果)。また、これらの第一空間の存在は、両基板に対して接着層が凹凸をなして接触する構成をもたらすので、接着層を挟んで両基板を圧着した際に、樹脂からなる接着層が過度に外力を受ける虞がなくなり、ひいては接着層自体の変形が抑制される(第二効果)。本発明は、これら2つの効果を兼ね備えることにより、接合状態の信頼性が高い半導体パッケージの提供に寄与する。   A semiconductor package according to the present invention (Claim 1) is provided by providing a plurality of independent first and second isolated spaces from an external space in an adhesive layer that joins a semiconductor substrate and a protective substrate. These first spaces function as a pool for outgas generated when the adhesive resin is thermally cured to form an adhesive layer. Therefore, since the outgas is induced from the vicinity of the interface between the adhesive layer and each substrate to the first space, the outgas hardly remains in the vicinity of the interface, and as a result, the generation of bubbles at the interface can be reduced (first). One effect). In addition, the presence of these first spaces results in a configuration in which the adhesive layer is in contact with both substrates in an uneven manner, so that when the substrates are pressure-bonded with the adhesive layer sandwiched, the adhesive layer made of resin is excessive. This eliminates the possibility of receiving external force and thus suppresses deformation of the adhesive layer itself (second effect). By combining these two effects, the present invention contributes to the provision of a semiconductor package with high reliability in the bonded state.

本発明に係る半導体パッケージの製造方法(請求項5)は、機能素子が一方の面に配された半導体基板を用い、該一方の面において該機能素子と重ならない領域に、複数の互いに独立するとともに、外部空間から孤立するように、第一空間を有する接着層を形成する工程Aに続けて、前記接着層を介して保護基板を取り付ける工程Bを行うことにより、工程Bにおいて接着層と各基板との界面付近で発生した出ガスを、機能素子と重ならない領域に設けた第一空間へ誘導することができる。これにより、機能素子と重なる領域において出ガスが残存しにくくなり、機能素子と重なる領域に発生する気泡を著しく低減できる。ゆえに、本発明によれば、良好な接合状態とされた半導体パッケージを簡便に形成できる製造方法が得られる。   A method of manufacturing a semiconductor package according to the present invention (Claim 5) uses a semiconductor substrate in which a functional element is disposed on one surface, and a plurality of independent elements are provided in a region that does not overlap the functional element on the one surface. In addition, the process B for attaching the protective substrate through the adhesive layer is followed by the process A for forming the adhesive layer having the first space so as to be isolated from the external space. The outgas generated near the interface with the substrate can be guided to a first space provided in a region that does not overlap with the functional element. As a result, it is difficult for the outgas to remain in the region overlapping the functional element, and the bubbles generated in the region overlapping the functional element can be significantly reduced. Therefore, according to the present invention, it is possible to obtain a manufacturing method capable of easily forming a semiconductor package having a good bonded state.

本発明に係る第一実施形態の半導体パッケージの一例を示す模式図。The schematic diagram which shows an example of the semiconductor package of 1st embodiment which concerns on this invention. 本発明に係る第一実施形態の半導体パッケージの他の一例を示す模式図。The schematic diagram which shows another example of the semiconductor package of 1st embodiment which concerns on this invention. 本発明に係る第一実施形態の半導体パッケージの他の一例を示す模式図。The schematic diagram which shows another example of the semiconductor package of 1st embodiment which concerns on this invention. 本発明に係る第二実施形態の半導体パッケージの一例を示す模式図。The schematic diagram which shows an example of the semiconductor package of 2nd embodiment which concerns on this invention. 図1に示した半導体パッケージの製造方法の工程を表す模式図。The schematic diagram showing the process of the manufacturing method of the semiconductor package shown in FIG. 図5に続く工程を表す模式図。The schematic diagram showing the process of following FIG. 図4に示した半導体パッケージの製造方法の工程を表す模式図。FIG. 5 is a schematic diagram showing a process of the semiconductor package manufacturing method shown in FIG. 4. 図7に続く工程を表す模式図。The schematic diagram showing the process of following FIG.

以下、本発明に係る半導体パッケージの実施形態を図面に基づいて説明する。
図1は、本発明の第一実施形態に係る半導体パッケージの一例を示す図面であり、図1(a)は図1(b)のA−A線における接着層の形状を示す模式的な平面図、(b)は半導体パッケージを厚さ方向から見た模式的な断面図である。
本発明の第一実施形態に係る半導体パッケージ1は、機能素子12が一方の面に配された半導体基板11と保護基板16とが、機能素子12と重ならない領域αに複数の第一空間13a(13)を有する接着層14を介して接合されることにより構成されている。このとき第一空間13a(13)は互いに独立していることを特徴とする。
その際、図2に示すように、半導体基板11と保護基板16との間を貫通してなる第一空間13b(13)としても良いし、半導体基板11あるいは保護基板16の何れか一方のみに開口するように配してなる第一空間13c(13)としても構わない。
本発明に係る半導体パッケージの構造によれば、半導体基板11と保護基板16を接合する接着層14において、機能素子12と重ならない領域αに複数の互いに独立した第一空間13を内在させて設けたことにより、これらの第一空間13は接着樹脂を熱硬化させて接着層14を形成した際に発生する出ガスのたまり場として機能する。ゆえに、接着層14と各基板との界面付近から第一空間13へ出ガスは誘導されるので、この界面付近に出ガスは残存しにくくなり、ひいては界面における気泡(以下、「ボイド」とも呼ぶ)の発生を低減させることができる(第一効果)。また、第一空間13の存在により、両基板に対して接着層14が凹凸をなして接触する構成となり、接着層14を挟んで両基板を圧着した際に、樹脂からなる接着層14が過度に外力を受ける虞がなくなり、ひいては接着層自体の変形が抑制される(第二効果)。その結果、接着層14を介して接合された両基板間の接合状態の信頼性の向上が図れる。
Hereinafter, embodiments of a semiconductor package according to the present invention will be described with reference to the drawings.
FIG. 1 is a drawing showing an example of a semiconductor package according to the first embodiment of the present invention. FIG. 1A is a schematic plan view showing the shape of an adhesive layer taken along the line AA in FIG. FIG. 2B is a schematic cross-sectional view of the semiconductor package viewed from the thickness direction.
The semiconductor package 1 according to the first embodiment of the present invention includes a plurality of first spaces 13a in a region α where the semiconductor substrate 11 and the protective substrate 16 in which the functional elements 12 are arranged on one surface do not overlap the functional elements 12. It is comprised by joining through the contact bonding layer 14 which has (13). At this time, the first spaces 13a (13) are independent of each other.
At that time, as shown in FIG. 2, the first space 13 b (13) penetrating between the semiconductor substrate 11 and the protective substrate 16 may be used, or only one of the semiconductor substrate 11 and the protective substrate 16 may be provided. The first space 13c (13) may be arranged so as to open.
According to the structure of the semiconductor package of the present invention, a plurality of first spaces 13 that are independent from each other are provided in a region α that does not overlap the functional element 12 in the adhesive layer 14 that joins the semiconductor substrate 11 and the protective substrate 16. As a result, these first spaces 13 function as a pool of outgas generated when the adhesive resin 14 is formed by thermosetting the adhesive resin. Therefore, since the outgas is induced from the vicinity of the interface between the adhesive layer 14 and each substrate to the first space 13, it is difficult for the outgas to remain in the vicinity of this interface, and as a result bubbles (hereinafter also referred to as “voids”) at the interface. ) Can be reduced (first effect). Further, due to the presence of the first space 13, the adhesive layer 14 comes into contact with both substrates in an uneven manner, and the adhesive layer 14 made of resin is excessive when the substrates are pressure-bonded with the adhesive layer 14 in between. This eliminates the possibility of receiving external force and thus suppresses deformation of the adhesive layer itself (second effect). As a result, it is possible to improve the reliability of the bonding state between the two substrates bonded via the adhesive layer 14.

さらに本発明の半導体パッケージ1において、複数の互いに独立した第一空間13は、半導体基板11に設けた機能素子12から見て、半導体基板11の外周寄りの領域に配されていることが好ましい。このような配置を採用することにより、外周域で発生する気泡(ボイド)を積極的に無くすことができるため、接合不良をより一層低減することが可能となる。
その際、第一空間13を構成するパターンの形状や面積、あるいは個数は、接着強度を満足するものであればいかようにでも可能である。たとえば、接着層14の形状の一例としては、図3(a)〜(d)に示すものが挙げられる。
図3(a)は、4辺の外周に沿って長手方向を有するように矩形状の第一空間13d、13eを設けた配置例である。図3(b)は、対向する2辺の外周に沿って長手方向を有するように矩形状の第一空間13f、13gを千鳥状に設け、特に一方の第一空間13gが局部的に半導体パッケージ1の外部と連通している配置例である。図3(c)は、対向する2辺の外周に沿って円形状の第一空間13hを設けた配置例である。図3(d)は、4辺の外周に沿って長手方向が全て一方向を成すように矩形状の第一空間13i、13jを設けた配置例である。
このように第一空間13を外周域に配する構造を採用することにより、外周域において、接着層と各基板との界面における気泡の発生を低減することができる。これにより、ウエハレベルパッケージ技術においてダイシングして半導体パッケージをチップ化した際の、特に側面付近における接合状態の信頼性の向上が図れる。
Furthermore, in the semiconductor package 1 of the present invention, the plurality of independent first spaces 13 are preferably arranged in a region near the outer periphery of the semiconductor substrate 11 when viewed from the functional element 12 provided on the semiconductor substrate 11. By adopting such an arrangement, air bubbles (voids) generated in the outer peripheral region can be positively eliminated, so that it is possible to further reduce bonding defects.
At this time, the shape, area, or number of patterns constituting the first space 13 can be any as long as it satisfies the adhesive strength. For example, examples of the shape of the adhesive layer 14 include those shown in FIGS.
FIG. 3A is an arrangement example in which rectangular first spaces 13d and 13e are provided so as to have a longitudinal direction along the outer periphery of the four sides. In FIG. 3B, rectangular first spaces 13f and 13g are provided in a zigzag pattern so as to have a longitudinal direction along the outer periphery of two opposing sides, and in particular, one of the first spaces 13g is locally provided in the semiconductor package. 1 is an example of arrangement in communication with the outside of 1. FIG. 3C is an arrangement example in which a circular first space 13h is provided along the outer periphery of two opposing sides. FIG. 3D is an arrangement example in which the rectangular first spaces 13 i and 13 j are provided so that the longitudinal directions are all in one direction along the outer periphery of the four sides.
By adopting the structure in which the first space 13 is arranged in the outer peripheral area in this way, the generation of bubbles at the interface between the adhesive layer and each substrate can be reduced in the outer peripheral area. As a result, when the semiconductor package is diced by wafer level package technology, the reliability of the bonded state particularly in the vicinity of the side surface can be improved.

図4は、本発明の第二実施形態に係る半導体パッケージの一例を説明する図面であり、図4(a)は図4(b)のB−B線に沿う接着層の形状を示す図、(b)は厚さ方向に沿う断面図である。
本発明の第二実施形態に係る半導体パッケージ2は、第一実施形態に係る半導体パッケージと同様、機能素子12が一方の面に配された半導体基板11と保護基板16が、接着層14を介して接合された構成である。
第二実施形態に係る半導体パッケージ2では、前記接着層14に機能素子12と重ならない領域αに配された複数の互いに独立した第一空間13k(13)の他に、機能素子12と重なる領域βに第二空間15を有することを特徴とする。
第二実施形態に係る半導体パッケージの構造によれば、まず第一実施形態と同様に、第一空間13k(13)を配したことによる効果、すなわち、上述した第一効果及び第二効果を備えている。これに加えて、さらに機能素子12と重なる領域βに第二空間15を有することにより、機能素子12の上部に気泡が残存し、その気泡の影響により機能素子12の能力が阻害される虞がなくなる。ゆえに、第二空間15を備えたことにより、たとえば機能素子12として撮像素子や発光素子などを搭載してなる半導体パッケージが提供できる。
FIG. 4 is a drawing for explaining an example of a semiconductor package according to the second embodiment of the present invention. FIG. 4A is a view showing the shape of an adhesive layer along the line BB in FIG. (B) is sectional drawing which follows a thickness direction.
Similar to the semiconductor package according to the first embodiment, the semiconductor package 2 according to the second embodiment of the present invention includes a semiconductor substrate 11 having a functional element 12 disposed on one surface and a protective substrate 16 via an adhesive layer 14. Are joined together.
In the semiconductor package 2 according to the second embodiment, in addition to the plurality of mutually independent first spaces 13k (13) arranged in the region α that does not overlap with the functional element 12 in the adhesive layer 14, the region that overlaps with the functional element 12 The second space 15 is included in β.
According to the structure of the semiconductor package according to the second embodiment, first, similarly to the first embodiment, the effect by arranging the first space 13k (13), that is, the first effect and the second effect described above are provided. ing. In addition, by having the second space 15 in the region β that overlaps with the functional element 12, air bubbles remain in the upper part of the functional element 12, and the capability of the functional element 12 may be hindered by the influence of the air bubbles. Disappear. Therefore, the provision of the second space 15 can provide a semiconductor package in which, for example, an image sensor or a light emitting element is mounted as the functional element 12.

本発明を利用することが可能な半導体パッケージ(デバイス)としては、イメージセンサやMEMSデバイスといった、基板表面に三次元構造を持つ機能素子を有するデバイスが挙げられる。本発明の半導体パッケージは、ウエハレベルパッケージ技術を用いた製造にも好適に用いることができる。   Examples of semiconductor packages (devices) that can use the present invention include devices having functional elements having a three-dimensional structure on the substrate surface, such as image sensors and MEMS devices. The semiconductor package of the present invention can be suitably used for manufacturing using wafer level package technology.

保護基板16としては、たとえばガラス基板やシリコン基板など、用途によって選択することが可能である。イメージセンサなどの光学デバイスをパッケージングする場合は、ガラス基板などの透明な基板が一般的に使用される。   The protective substrate 16 can be selected depending on the application, such as a glass substrate or a silicon substrate. In the case of packaging an optical device such as an image sensor, a transparent substrate such as a glass substrate is generally used.

接着層14は、接着機能を有する樹脂を用いて形成されることが好ましく、これにより製造プロセスの低温化が図れる。特に、温度耐性の低い(200℃程度)素子、たとえば個体撮像素子のパッケージ等に応用できる。また、接着層14が接着機能を有する樹脂からなる接着樹脂層である場合は、ウエハレベルパッケージ技術において、パッケージ後にダイシングを行うとき、メタルにより接着層を形成した場合に比べてダイシングブレードで比較的容易に切断することができる。またさらに、感光性接着樹脂等を用いれば、プロセスの簡略化を図ることができる。   The adhesive layer 14 is preferably formed using a resin having an adhesive function, which can reduce the temperature of the manufacturing process. In particular, it can be applied to an element having a low temperature resistance (about 200 ° C.), for example, a package of an individual imaging element. In addition, when the adhesive layer 14 is an adhesive resin layer made of a resin having an adhesive function, in the wafer level package technology, when dicing after packaging, the dicing blade is relatively less than when the adhesive layer is formed of metal. Can be easily cut. Furthermore, if a photosensitive adhesive resin or the like is used, the process can be simplified.

また、本発明の半導体パッケージの構造は、表面に機能素子を有さない半導体基板の場合にも有効である。たとえば、ウエハサポートシステムのように、デバイス基板かサポート基板かの全面に接着剤を塗布して接合する場合にも、接着層に中空構造を持たせることにより、接着層と各基板との界面における気泡の発生を低減することができ、接合状態の信頼性の向上が図れる。   The structure of the semiconductor package of the present invention is also effective for a semiconductor substrate that does not have a functional element on the surface. For example, even when an adhesive is applied to the entire surface of a device substrate or a support substrate, as in a wafer support system, by bonding the adhesive layer with a hollow structure, the interface between the adhesive layer and each substrate is provided. The generation of bubbles can be reduced, and the reliability of the joined state can be improved.

次に、これらの半導体パッケージの製造方法の一例について、図面に基づいて説明する。
図5は、本発明の第一実施形態に係る半導体パッケージの製造方法の工程を説明する図面であり、機能素子と重ならない領域に複数の互いに独立した第一空間を有する接着層を備えた半導体基板の一例を示す断面図である。図6は、図5に続く工程として、半導体基板に保護基板を接合した状態を説明する図面であり、図6(a)は図6(b)のC−C線に沿う接着層の形状を示す図、図6(b)は厚さ方向に沿う断面図である。
Next, an example of a method for manufacturing these semiconductor packages will be described with reference to the drawings.
FIG. 5 is a diagram for explaining a process of the semiconductor package manufacturing method according to the first embodiment of the present invention, in which a semiconductor having an adhesive layer having a plurality of independent first spaces in a region that does not overlap with a functional element. It is sectional drawing which shows an example of a board | substrate. FIG. 6 is a diagram for explaining a state in which a protective substrate is bonded to a semiconductor substrate as a process subsequent to FIG. 5. FIG. 6A shows the shape of the adhesive layer along the line CC in FIG. FIG. 6B is a cross-sectional view along the thickness direction.

本発明の第一実施形態に係る半導体パッケージの製造方法は、まず、図5に示すように、半導体基板11の機能素子12が配された側の面上に、機能素子12と重ならない領域αに第一開口部13Aを有する接着層14を形成する(工程A)。
ここでは、半導体基板11に接着層14を形成した例について詳述するが、保護基板16に接着層14を形成してもよい。
接着層の形成には、ワニス状やペースト状の感光性接着剤をスピンコート法、印刷法、ディスペンス法などにより塗布したり、フィルム状の感光性接着剤をラミネートにより形成し、フォトリソグラフィにより任意のパターンを形成したりする方法を用いることができる。接着樹脂としては、たとえばエポキシ樹脂、シリコーン樹脂、アクリル樹脂、ポリイミド樹脂、ベンゾシクロブテン樹脂が挙げられる。
In the method of manufacturing a semiconductor package according to the first embodiment of the present invention, first, as shown in FIG. 5, a region α that does not overlap with the functional element 12 on the surface of the semiconductor substrate 11 on which the functional element 12 is disposed. Then, the adhesive layer 14 having the first opening 13A is formed (step A).
Here, although an example in which the adhesive layer 14 is formed on the semiconductor substrate 11 will be described in detail, the adhesive layer 14 may be formed on the protective substrate 16.
The adhesive layer can be formed by applying a varnish-like or paste-like photosensitive adhesive by spin coating, printing, dispensing, etc., or by forming a film-like photosensitive adhesive by lamination, and by photolithography. The method of forming the pattern can be used. Examples of the adhesive resin include epoxy resin, silicone resin, acrylic resin, polyimide resin, and benzocyclobutene resin.

次に、図6に示すように、第一開口部13Aは半導体基板11の機能素子12が配された側の面と保護基板16との間に設けられた空隙であり、半導体基板11が接着層14を介して保護基板16と接合されることにより形成される(工程B)。
その際の接合方法としては、たとえば熱圧着法が挙げられる。この方法では、真空チャンバ内で加熱プレスし、その最中またはプレス後に所定の硬化温度で接着剤を熱硬化させる。硬化温度は、材料により異なるが、150〜400℃程度が一般的である。
Next, as shown in FIG. 6, the first opening 13 </ b> A is a gap provided between the surface of the semiconductor substrate 11 on which the functional element 12 is disposed and the protective substrate 16. It is formed by being bonded to the protective substrate 16 through the layer 14 (step B).
As a joining method at that time, for example, a thermocompression bonding method is exemplified. In this method, the adhesive is heated and pressed in a vacuum chamber, and the adhesive is thermally cured at a predetermined curing temperature during or after the pressing. The curing temperature varies depending on the material, but is generally about 150 to 400 ° C.

第一実施形態に係る半導体パッケージの製造方法は、工程Aとそれに続く工程Bとを少なくとも備えることを特徴とし、これにより、半導体基板11と保護基板16との間に配される接着層14に、複数の互いに独立した第一空間13a(13)を有する構造の半導体パッケージを得ることができる。
その際、工程Bにおいて、接着層14と各基板との界面付近で発生した出ガスを、機能素子12と重ならない領域αに設けた第一空間13a(13)へ誘導することができる。これにより、機能素子12と重なる領域βにおいて出ガスが残存しにくくなり、機能素子12と重なる領域βに発生する気泡を著しく低減することができる。ゆえに、本発明によれば、接合状態の信頼性の高い半導体パッケージを簡便な工程で形成できる製造方法が得られる。
次いで、図6に示すように、二重の二点鎖線で示した箇所[たとえば、接着層14b(14)の部分]において切断処理を行うことにより、個片化された半導体パッケージが形成される。
The method for manufacturing a semiconductor package according to the first embodiment includes at least a process A and a process B following the process A, whereby the adhesive layer 14 disposed between the semiconductor substrate 11 and the protective substrate 16 is provided. A semiconductor package having a structure having a plurality of first spaces 13a (13) independent from each other can be obtained.
At that time, in step B, the outgas generated near the interface between the adhesive layer 14 and each substrate can be guided to the first space 13 a (13) provided in the region α that does not overlap the functional element 12. This makes it difficult for the outgas to remain in the region β overlapping with the functional element 12, and the bubbles generated in the region β overlapping with the functional element 12 can be significantly reduced. Therefore, according to the present invention, a manufacturing method capable of forming a highly reliable semiconductor package in a bonded state by a simple process can be obtained.
Next, as shown in FIG. 6, by performing a cutting process at a location [for example, a portion of the adhesive layer 14 b (14)] indicated by a double two-dot chain line, an individualized semiconductor package is formed. .

本発明に係る半導体パッケージの製造方法は工程Aと工程Bを少なくとも備えているが、工程Aと工程Bによる作用・効果が得られる限り、これら2つの工程以外の工程を別に備えていても構わない。   The method for manufacturing a semiconductor package according to the present invention includes at least a process A and a process B. However, as long as the operations and effects of the process A and the process B can be obtained, processes other than these two processes may be separately provided. Absent.

図7は、本発明の第二実施形態に係る半導体パッケージの製造方法の工程を説明する図面であり、機能素子と重ならない領域の複数の互いに独立した第一空間とともに、機能素子と重なる領域に第二空間を有する接着層を備えた半導体基板の一例を示す断面図である。図8は、図7に続く工程として、半導体基板に保護基板を接合した状態を説明する図面であり、図8(a)は図8(b)のC−C線に沿う接着層の形状を示す図、図6(b)は厚さ方向に沿う断面図である。   FIG. 7 is a diagram for explaining a process of a method for manufacturing a semiconductor package according to the second embodiment of the present invention, in a region overlapping with a functional element, together with a plurality of independent first spaces in a region not overlapping with the functional element. It is sectional drawing which shows an example of the semiconductor substrate provided with the contact bonding layer which has 2nd space. FIG. 8 is a diagram for explaining a state in which a protective substrate is bonded to a semiconductor substrate as a process following FIG. 7, and FIG. 8A shows the shape of the adhesive layer along the line CC in FIG. 8B. FIG. 6B is a cross-sectional view along the thickness direction.

本発明の第二実施形態に係る半導体パッケージの製造方法は、第一実施形態に係る半導体パッケージの製造方法と同様、まず、半導体基板11の上に接着層14を形成した後、その接着層14の上に保護基板16を接合する方法である。
第二実施形態に係る半導体パッケージの製造方法は、図7に示すように、接着層14を形成する工程Aにおいて、機能素子12と重ならない領域αに配された複数の互いに独立した第一開口部13Kと同時に、機能素子12と重なる領域βに配された第二開口部15Kを設けることを特徴とする。
その後、図8に示すように、第一開口部13K及び第二開口部15Kにおいて半導体基板11の機能素子12が配された側の面と保護基板16との間に空隙を備えるように、接着層14を介して保護基板16を接合する工程Bを行うことにより、半導体基板11と保護基板16との間に配される接着層14において、機能素子12に重ならない領域αに内在する複数の互いに独立した第一空間13k(13)とともに機能素子12に重なる領域βに第二空間15を有する構造の半導体パッケージを得ることができる。
次いで、図8に示すように、二重の二点鎖線で示した箇所[たとえば、接着層14e(14)の部分]において切断処理を行うことにより、個片化された半導体パッケージが形成される。切断後の半導体パッケージにはそれぞれ、第一空間13k、13k’(13)が設けられる。
In the semiconductor package manufacturing method according to the second embodiment of the present invention, the adhesive layer 14 is first formed on the semiconductor substrate 11 and then the adhesive layer 14, as in the semiconductor package manufacturing method according to the first embodiment. This is a method of bonding the protective substrate 16 on the substrate.
As shown in FIG. 7, the method for manufacturing a semiconductor package according to the second embodiment includes a plurality of independent first openings arranged in a region α that does not overlap with the functional element 12 in the step A of forming the adhesive layer 14. Simultaneously with the portion 13K, a second opening 15K disposed in the region β overlapping with the functional element 12 is provided.
Thereafter, as shown in FIG. 8, the first opening 13 </ b> K and the second opening 15 </ b> K are bonded so that a gap is provided between the surface of the semiconductor substrate 11 on which the functional element 12 is disposed and the protective substrate 16. By performing the process B in which the protective substrate 16 is bonded via the layer 14, the adhesive layer 14 disposed between the semiconductor substrate 11 and the protective substrate 16 has a plurality of regions α that do not overlap the functional element 12. A semiconductor package having a structure in which the first space 13k (13) independent from each other and the second space 15 in the region β overlapping the functional element 12 can be obtained.
Next, as shown in FIG. 8, by performing a cutting process at a location [for example, a portion of the adhesive layer 14 e (14)] indicated by a double two-dot chain line, an individualized semiconductor package is formed. . First spaces 13k and 13k ′ (13) are provided in the cut semiconductor packages, respectively.

第二実施形態に係る半導体パッケージの製造方法によれば、まず第一実施形態と同様に、工程Bにおいて、接着層14と各基板との界面付近で発生した出ガスを、第一空間13k(13)へ誘導することにより、基板界面に発生する気泡を著しく低減することができる効果を備えている。これに加えて、機能素子12と重なる領域βに同時に第二空間15を形成することにより、機能素子12の上部に気泡が残存し、その気泡の影響により機能素子12の能力が阻害される虞がなくなる。
この方法によると、第一開口部13Kと第二開口部15Kを同時に形成するため工程数の増加は少なく、たとえば機能素子12として撮像素子や発光素子などを搭載する場合に好適な半導体パッケージを簡便に形成できる製造方法が得られる。
According to the method for manufacturing a semiconductor package according to the second embodiment, first, similarly to the first embodiment, in step B, the outgas generated near the interface between the adhesive layer 14 and each substrate is converted into the first space 13k ( 13), it is possible to remarkably reduce bubbles generated at the substrate interface. In addition to this, by simultaneously forming the second space 15 in the region β overlapping with the functional element 12, bubbles remain in the upper part of the functional element 12, and the capability of the functional element 12 may be hindered by the influence of the bubbles. Disappears.
According to this method, since the first opening 13K and the second opening 15K are formed at the same time, the number of processes is not increased. For example, a semiconductor package suitable for mounting an image sensor or a light emitting element as the functional element 12 can be easily obtained. The manufacturing method which can be formed is obtained.

本発明は、機能素子が配された半導体基板と保護基板が、複数の独立した空間を有する接着層を介して接合された半導体パッケージ及びその製造に利用することが可能であり、たとえば、イメージセンサやMEMSデバイスといった、基板表面に三次元構造を持つ機能素子を有するデバイス等に好適である。   INDUSTRIAL APPLICABILITY The present invention can be used for a semiconductor package in which a semiconductor substrate on which a functional element is arranged and a protective substrate are bonded via an adhesive layer having a plurality of independent spaces, and the manufacturing thereof, for example, an image sensor. It is suitable for a device having a functional element having a three-dimensional structure on the substrate surface, such as a semiconductor device or a MEMS device.

α 機能素子と重ならない領域、β 機能素子と重なる領域、1,2 半導体パッケージ、11 半導体基板、12 機能素子、13(13a、13b、13c、13d、13e、13f、13g、13h、13i、13j、13k、13k’) 第一空間、13A、13K 第一開口部、14 接着層、15 第二空間、15K 第二開口部、16 保護基板、17 ダイシングライン。   Region that does not overlap with α functional element, region that overlaps with β functional element, 1, 2 semiconductor package, 11 semiconductor substrate, 12 functional element, 13 (13a, 13b, 13c, 13d, 13e, 13f, 13g, 13h, 13i, 13j 13k, 13k ′) first space, 13A, 13K first opening, 14 adhesive layer, 15 second space, 15K second opening, 16 protective substrate, 17 dicing line.

Claims (4)

光学デバイスが一方の面に配された半導体基板と、該一方の面上に透明な接着層を介して接合された透明な保護基板とを備える半導体パッケージであって、
前記光学デバイスは、前記半導体基板と前記接着層とによって封止され、
前記接着層は、前記光学デバイスと重ならない領域に複数の第一空間を有し、該第一空間は互いに独立して、かつ、外部空間から孤立して配されており、
全ての前記第一空間は各々、前記半導体基板から前記保護基板に至るように、前記接着層の厚み方向に貫通していることを特徴とする半導体パッケージ
An optical device is a semiconductor package comprising a semiconductor substrate disposed on one surface, and a transparent protective substrate bonded on the one surface via a transparent adhesive layer,
The optical device is sealed by the semiconductor substrate and the adhesive layer,
The adhesive layer has a plurality of first spaces in a region that does not overlap the optical device , the first spaces are arranged independently of each other and isolated from the external space ,
Each and every of the first space, the way extending from the semiconductor substrate to the protective substrate, a semiconductor package, characterized in that extending through the thickness direction of the adhesive layer.
前記第一空間が前記半導体基板の外周域に配されていることを特徴とする請求項1に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the first space is arranged in an outer peripheral region of the semiconductor substrate. 前記接着層が前記光学デバイスと重なる領域に第二空間を有することを特徴とする請求項1又は2に記載の半導体パッケージ。 The semiconductor package according to claim 1, wherein the adhesive layer has a second space in a region overlapping with the optical device . 前記接着層が接着機能を備えた樹脂からなることを特徴とする請求項1乃至3のいずれか一項に記載の半導体パッケージ。   The semiconductor package according to any one of claims 1 to 3, wherein the adhesive layer is made of a resin having an adhesive function.
JP2012106193A 2012-05-07 2012-05-07 Semiconductor package Expired - Fee Related JP5384693B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012106193A JP5384693B2 (en) 2012-05-07 2012-05-07 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012106193A JP5384693B2 (en) 2012-05-07 2012-05-07 Semiconductor package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2008072521A Division JP5028308B2 (en) 2008-03-19 2008-03-19 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2012182481A JP2012182481A (en) 2012-09-20
JP5384693B2 true JP5384693B2 (en) 2014-01-08

Family

ID=47013357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012106193A Expired - Fee Related JP5384693B2 (en) 2012-05-07 2012-05-07 Semiconductor package

Country Status (1)

Country Link
JP (1) JP5384693B2 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1012757A (en) * 1996-06-25 1998-01-16 Kokusai Electric Co Ltd Micropackage
JP2006049700A (en) * 2004-08-06 2006-02-16 Fuji Photo Film Co Ltd Manufacturing method of solid-state image pickup device
JP4808971B2 (en) * 2005-01-13 2011-11-02 日本電信電話株式会社 Manufacturing method of fine structure
JP2008072521A (en) * 2006-09-14 2008-03-27 Fujitsu Ltd Equipment, method and program for communication
JP5373262B2 (en) * 2006-12-06 2013-12-18 株式会社デンソー Cap fixing method of semiconductor substrate
CN101911485B (en) * 2008-01-17 2014-07-09 株式会社村田制作所 Piezoelectric device

Also Published As

Publication number Publication date
JP2012182481A (en) 2012-09-20

Similar Documents

Publication Publication Date Title
US8962389B2 (en) Microelectronic packages including patterned die attach material and methods for the fabrication thereof
JP5384690B2 (en) Chip package
JP4234269B2 (en) Semiconductor device and manufacturing method thereof
JP2010230655A (en) Sensor device and manufacturing method thereof
JP5472557B1 (en) Composite electronic component and electronic device including the same
JP2015225933A (en) Semiconductor device and manufacturing method of the same
US8748926B2 (en) Chip package with multiple spacers and method for forming the same
JP5088373B2 (en) Manufacturing method of electronic parts
JP5384693B2 (en) Semiconductor package
JP2012033718A (en) Semiconductor device and manufacturing method of the same
JP5028308B2 (en) Semiconductor package and manufacturing method thereof
WO2014027476A1 (en) Semiconductor device
US20120306032A1 (en) Method of bonding semiconductor substrate and mems device
WO2014010237A1 (en) Method for producing semiconductor device
JP5278147B2 (en) Semiconductor package and semiconductor package manufacturing method
JP2001223288A (en) Integrated circuit device and its manufacturing method
JP2016082060A (en) package
JP2014179470A (en) Packaging structure of image sensor
WO2017150044A1 (en) Semiconductor light receiving module and method for manufacturing semiconductor light receiving module
JP5783601B2 (en) Hollow package
KR20190068267A (en) Gas sensor
KR102081612B1 (en) Semiconductor package and method for manufacturing the same
JP2008171904A (en) Laminated semiconductor device and its manufacturing method
JP2008118029A (en) Semiconductor device manufacturing method and semiconductor device
JP2015126187A (en) Semiconductor package

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130226

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130426

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130528

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130826

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20130903

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130924

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131002

R151 Written notification of patent or utility model registration

Ref document number: 5384693

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees