JP2001223288A - Integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the package size of an IC(integrated circuit) having a chip size package. SOLUTION: A pad electrode 14a being connected with an IC is formed on an insulation film 12 covering the surface of the IC chip region of a semiconductor wafer. A contact hole 22a made in the chip region for protecting the IC chip region of a glass protection board is filled with a conduction plug 26a and a relief groove 24a surrounding the contact hole 22a, a bump electrode 28a connected with the plug 26a, and an adhesion layer 30 of thermoplastic adhesive are provided on the lower surface side. When the electrode 28a is connected with the electrode 14a, the IC is sealed by bonding the wafer and the protection board through the adhesion layer 30 and a bump electrode 32a is formed on the plug 26a. Finally, an IC device comprising an IC chip 10 and a protection chip 20 is separated, by dicing, from a laminate of the wafer and the protection board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC (integrated circuit) device having a chip size package (CSP) and a method of manufacturing an IC device for performing chip size packaging in a wafer state, and more particularly to an IC chip. A pad electrode provided on one main surface of the IC chip is connected to a conductive plug buried in a connection hole of the protection chip for protecting the IC chip by a bump electrode, and the protection chip is adhered to one main surface of the IC chip by an adhesive layer. Seal one main surface of chip
The size of the CSP can be reduced by making the chip and the protection chip have substantially the same cutting shape.

[0002]

2. Description of the Related Art Conventionally, as a method of manufacturing an IC device for performing chip size packaging in a wafer state, FIG.
To 24 are known (for example, see Japanese Unexamined Patent Publication No.
511097).

In the process shown in FIG. 22, a semiconductor wafer with a built-in IC is bonded to an insulating protective plate 1 made of glass or the like by an epoxy layer 3, and the semiconductor wafer is ground by a grinding process.
Reduce the thickness to about μm. Then, the semiconductor wafer is divided into a plurality of IC chips 2 by cutting and etching.
A, 2B. Thereafter, the insulating sheath film 4 is covered with the epoxy layer 5 to expose the protection plate 3 and the IC chips 2A, 2B.
Adhere to the back side of Pad part 2 of IC chips 2A and 2B
The portions a and 2b extending outward from the edges of the IC chips 2A and 2B are sandwiched between the epoxy layers 3 and 5.

Next, in the step of FIG. 23, a groove 6 is formed by performing a cutting process on a portion between the IC chips 2A and 2B in the lamination of the protective plate 1 and the epoxy layers 3 and 5.
At this time, the protection plate 1 is divided into portions 1A and 1B corresponding to the IC chips 2A and 2B, and the epoxy layer 3 is divided into portions 3A and 3B corresponding to the IC chips 2A and 2B. The ends of the pad portions 2a and 2b are exposed on the side wall surface of the groove 6. Thereafter, metal contact portions (wirings) 7a and 7b are formed by a metal lamination method so as to contact the ends of the pad portions 2a and 2b, respectively, and reach the upper surfaces of the protection plates 1A and 1B.

Thereafter, in a step shown in FIG.
By performing a cutting process (dicing) on a portion between the IC chips 2A and 2B with respect to the lamination of the exterior film 4, the groove 6 is formed.
Is formed. As a result, the epoxy layer 5 has portions 5A, 5B corresponding to the IC chips 2A, 2B.
The exterior film 4 is divided into portions 4A and 4B corresponding to the IC chips 2A and 2B. A first IC device 9A including a laminate of the exterior film 4A to the protection plate 1A, and an exterior film 4
The second IC device 9B including the laminate of B to the protection plate 1B is separated from the laminate of FIG.

As another prior art, after the step of FIG. 22, each end of the pad portions 2a and 2b is exposed.
The laminate of FIG. 22 is separated into two IC devices by performing a cutting process on the laminate of FIG.
It is also known that a metal contact portion (for example, 7a) that contacts a pad portion (for example, 2a) is formed on the side surface of each C device (for example, see Japanese Patent Application Laid-Open No. 8-503,813).

[0007]

According to the above-mentioned prior art, the terminal wiring 7a is led out to the upper surface of the protection plate 1A via the side of the stack (3A, 1A) covering the IC chip 2A and the IC chip 2A. Since the epoxy layer 5A and the package film 4A are arranged on the back side of the IC chip 2A, the package size becomes considerably larger than the size of the IC chip 2A, and the terminal wiring length becomes considerably longer.

Further, according to the above-mentioned conventional technology, there is a problem that the process is complicated. That is, before or after separating the laminated body into a plurality of IC devices, to form a terminal wiring on the inclined surface of the groove 6 or the cut surface of the groove 8, metal deposition (for example, sputtering), photolithography and selection Etching, plating, etc. are required.

Further, the semiconductor wafer is mounted on the IC chip 2A,
After dividing into 2B, terminal wiring is formed.
Bonding with an epoxy layer 5 and grooves 6 and / or grooves 8
Is required.

An object of the present invention is to provide a novel integrated circuit device capable of reducing the size of a CSP.

It is another object of the present invention to provide a method of manufacturing a novel integrated circuit device in which chip size packaging in a wafer state is greatly simplified.

[0012]

An integrated circuit device according to the present invention has an integrated circuit formed on one main surface and a plurality of pad electrodes connected to the integrated circuit formed around the integrated circuit. And an insulating protection chip for covering and protecting one main surface of the integrated circuit chip, comprising a plurality of connection holes respectively corresponding to the plurality of pad electrodes. A conductive plug is buried in each connection hole, and each conductive plug is connected to a corresponding pad electrode by a bump electrode on an opposing surface facing one main surface of the integrated circuit chip, and the opposing surface is connected to the integrated circuit. Sealing the one main surface of the integrated circuit chip by being adhered to one main surface of the chip by an adhesive layer, wherein the integrated circuit chip and the protection chip are Qualitatively those having the same cutting geometry.

According to the structure of the present invention, each pad electrode is led out to the exposed surface side of the protection chip via the bump electrode and the conductive plug at the shortest distance, and one main surface of the integrated circuit chip is connected to the protection chip and the adhesive. Sealed by layers, the integrated circuit chip and the protection chip have substantially the same cut shape. Therefore, the size of the CSP can be reduced,
The terminal wiring length can also be reduced.

In the structure of the present invention, another bump electrode may be provided at the end of each conductive plug on the exposed surface of the protective chip. This makes it easy to mount the integrated circuit device on a circuit board or the like.

According to a method of manufacturing an integrated circuit device according to the present invention, there is provided a semiconductor wafer having an integrated circuit chip area, wherein an integrated circuit is formed in the integrated circuit chip area and connected to the integrated circuit around the integrated circuit. Preparing an electrode having a plurality of pad electrodes formed thereon, and an insulating protection substrate having a protection chip area for covering and protecting the integrated circuit chip area, wherein the protection chip area includes the plurality of pad electrodes. Providing a plurality of connection holes respectively corresponding to the pad electrodes and burying a conductive plug in each connection hole; and providing the protection chip area for each pad electrode in the integrated circuit chip area. The semiconductor wafer and the protection substrate are adhered to each other with an adhesive layer along with the connection of the corresponding conductive plugs within the bump electrodes, thereby forming the integrated circuit chip area. A step of stopping, is intended to include a step of separating by cutting the integrated circuit device including the integrated circuit chip area to the protected chip area of a laminate of the semiconductor wafer to the protective substrate.

According to the manufacturing method of the present invention, the formation of the connection hole can be performed by well-known photolithography and selective etching, such as embedding a conductive plug in the connection hole, forming a bump electrode, and forming an adhesive layer. The processing can be performed by a simple processing such as screen printing. Further, when each conductive plug is connected to a corresponding pad electrode by a bump electrode, the semiconductor wafer and the protection substrate are bonded and sealed with an adhesive layer, and then the semiconductor wafer or the protection substrate laminate is cut. Since the integrated circuit device is separated, each of the sealing process and the cutting process is completed in one step. Therefore, the process can be greatly simplified.

In the manufacturing method of the present invention, after the sealing step and before the separating step, each conductive plug in the protection chip region has an end opposite to the end to which the corresponding bump electrode is connected. Other bump electrodes may be connected.
In this way, connection of the bump electrodes can be performed in a wafer state, and in particular, when a plurality of integrated circuit chip regions are provided on a semiconductor wafer, a large number of bump electrodes can be formed at once.

In the manufacturing method of the present invention, in the step of preparing the protective substrate, a relief groove is formed around each connection hole on the front surface side of the protective substrate to be bonded to the semiconductor wafer so as to allow the adhesive layer to flow. It may be. This makes it possible to achieve uniform bonding when bonding the semiconductor wafer and the protective substrate with the bonding layer.

In the method of the present invention, in the step of preparing the protection substrate, the opening size on the main surface opposite to the main surface is larger than the opening size on the main surface of the protection substrate to be bonded to the semiconductor wafer. Each connection hole may be formed so as to be as follows. This makes it easier to embed the conductive paste in each connection hole to form a conductive plug.

[0020]

FIG. 1 shows an IC device according to an embodiment of the present invention. FIG. 2 shows a cross section taken along line AA 'of FIG.

The IC device shown in FIGS. 1 and 2 has an IC chip 10 made of a semiconductor, an insulating protective chip 20 for covering and protecting the IC chip, and bonding the protective chip to the IC chip 10. And an adhesive layer 30.

On one main surface of the IC chip 10, an IC
(Not shown) and an insulating film 12 such as a field insulating film. On the insulating film 12, a plurality of pad electrodes such as 14a and 14b connected to the IC are formed around the IC. As a pad electrode, a symmetric pad electrode arrangement may be realized by providing a dummy pad electrode that is not connected to the IC. Further, in order to apply the present invention to a mounting substrate that does not support a narrow pitch, the pitch of the pad electrodes may be widened and rearranged in accordance with the mounting substrate. The pad electrodes such as 14a and 14b are 16a,
Each of the protective insulating films is covered with a protective insulating film such as 16b, and a connection hole exposing the central portion of the corresponding pad electrode is formed in each protective insulating film.

The protection chip 20 is provided with a plurality of connection holes such as 22a and 22b corresponding to a plurality of pad electrodes such as 14a and 14b. Conductive plugs such as 26a and 26b are embedded in the connection holes such as 22a and 22b. Ring-shaped relief grooves such as 24a and 24b are provided on the surface of the protection chip 20 facing the one main surface of the IC chip 10 so as to surround the connection holes such as 22a and 22b. Each escape groove is provided with an adhesive layer 30.
This allows the inflow of water.

The conductive plugs such as 26a and 26b are 28a,
The protection chip 20 is bonded to the IC formation surface of the IC chip 10 by the adhesive layer 30 by being connected to the pad electrodes such as 14a and 14b by bump electrodes such as 28b, thereby sealing the IC formation surface of the IC chip 10. Is done.
On the exposed surface of the protection chip 20 opposite to the surface facing the semiconductor chip 10, bump electrodes such as 32a and 32b connected to conductive plugs such as 26a and 26b are provided. When the bump electrodes are provided on the mounting substrate, the bump electrodes such as 32a may be omitted.

The IC chip 10 and the protection chip 20 are:
4a, 14b and the like have substantially the same cut shape obtained by cutting along the grid line region 18 provided so as to surround the frame-shaped arrangement of the pad electrodes. The CSP that covers the IC chip 10 includes the protection chip 20 and the adhesive layer 30 and is as small as the IC chip 10. Also,
From the CSP, the pad electrode such as 14a is led to the exposed surface side of the protection chip via the bump electrode such as 28a and the conductive plug such as 26a at the shortest distance, so that the terminal wiring length is reduced.

Next, with reference to FIGS.
The method for manufacturing the C apparatus will be described.

In the step shown in FIG. 3, a protective substrate 20A made of, for example, silica glass, quartz or polyimide and having a thickness of 100 to 300 μm is prepared. As shown in FIG. 10, the protective substrate 20A is used for a semiconductor wafer 10A in a sealing step described later.
And a plurality of protection chip areas respectively corresponding to a plurality of IC chip areas provided on the semiconductor wafer 10A. Each IC chip area is surrounded by a grid line area 18. One of the many IC chip areas is defined as 10a, and the area 1
The protection chip area corresponding to 0a is set to 20a.

FIG. 11 shows a frame-like arrangement of pad electrodes such as 14a and 14b in the IC chip area 10a. A cross section taken along line BB ′ of FIG. 11 is shown in FIG. FIG. 12 shows a protection chip area 20a to be overlapped with the IC chip area 10a.

In the step of FIG. 3, connection holes 22a, 22b and the like corresponding to the pad electrodes 14a, 14b and the like are formed in the protective substrate 20A by photolithography and selective etching. FIG. 12 shows a frame-like arrangement of the connection holes formed at this time. CC ′ in FIG.
The cross section along the line corresponds to the cross section in FIG. Connection hole 22a,
FIG. 13 is a partial cross-sectional perspective view showing the formation state of 22b. In photolithography and selective etching,
The connection holes such as 22a and 22b can be formed by performing dry etching or wet etching with a resist layer having a connection hole pattern disposed on one main surface and the other main surface of the protection substrate 20A.

Each connection hole such as 22a may be formed to have the same size (for example, 100 to 300 μm in diameter) from the surface of the protection substrate 20A facing the semiconductor wafer 10A to the exposed surface on the opposite side. In this embodiment, the protection substrate 20A is formed such that the opening size on the exposed surface opposite to the facing surface is larger than the opening size on the surface facing the semiconductor wafer 10A. In the examples of FIGS. 3 and 13, when the opening size on the facing surface is 100 to 150 μm in diameter, the opening size on the exposed surface can be 150 to 300 μm in diameter. This facilitates the formation of the conductive plug in the step of FIG.

Next, in the step shown in FIG. 4, the protection substrate 20A has a surface 22a, 22b on the surface facing the semiconductor wafer 10A.
Release grooves such as 24a and 24b are formed by photolithography and selective etching so as to surround the connection holes such as. The relief grooves 24a formed at this time,
24b is also shown in FIGS. Figures 15 and 1
6 shows a state in which the protection substrate 20A shown in FIGS. 13 and 14 is turned upside down so that the escape groove 24a is arranged at the upper right side. Each relief groove is for enabling the flow of the adhesive layer 30 in the process of FIG. 8 and has a depth of 50 to 150 μm. In addition, the width of each relief groove (D shown for the relief groove 24a) can be set to 50 μm as an example.

Next, in the step of FIG. 5, a conductive paste containing copper or silver is applied to the conductive pastes 22a and 22a by a silk screen printing method.
After filling into the connection holes such as 2b, 30 to 125 ° C.
The conductive plugs 26a, 26b, etc., which fill the connection holes 22a, 22b, etc., respectively, are formed by performing a baking process for minutes. At this time, since the connection holes such as 22a and 22b are formed with the upper opening size larger than the lower opening size, the conductive paste can be easily and reliably filled. The state of formation of the conductive plugs 26a and 26b is also shown in FIG.

Next, in the step shown in FIG. 6, the protective substrate 20A has a surface 26a, 26b on the surface facing the semiconductor wafer 10A.
Then, bump electrodes such as 28a and 28b made of solder are formed so as to be respectively connected to the conductive plugs such as. For this purpose, after baking solder bumps on the ends of the respective conductive plugs by a silk screen printing method or a solder bump dispenser, baking treatment can be performed at 200 ° C. The height of each bump electrode such as 28a is 30 to 50 μm
It can be. The state of formation of the bump electrodes 28a and 28b is also shown in FIG.

Next, in the step shown in FIG. 7, 24a, 24b are formed on the surface of the protection substrate 20A facing the semiconductor wafer 10A.
An adhesive layer 30 made of a thermoplastic adhesive is formed by a silk screen printing method in a region (a region corresponding to the IC forming portion and the grid line region 18 of the semiconductor wafer 10A) other than the region surrounded by the relief groove. After printing, the adhesive layer 30 is cured at 135 to 160 ° C. The state of formation of the adhesive layer 30 is also shown in FIG. The thickness of the adhesive layer 30 can be 40 to 60 μm. The adhesive layer 30 may be made of a thermosetting adhesive.

The process described above with reference to FIGS. 3 to 7 is a process for preparing a protective substrate 20A to be superimposed on the semiconductor wafer 10A, but before or after such a process or in parallel with such a process. , 10, 11, and 17 are prepared. That is, for example, on a semiconductor wafer 10A made of silicon, ICs are formed for each IC chip area such as 10a by a known method, and 14a,
A plurality of pad electrodes such as 14b are formed. Each pad electrode has an under bump metal having good connectivity with a solder bump as an uppermost layer.

The pad electrode 14a is covered with a protective insulating film 16a as shown in FIGS. 8 and 17, and a connection hole 16H exposing the central portion of the pad electrode 14a is formed in the insulating film 16a by photolithography and selective etching. It is formed. The pad electrode 14a can be a square having a side length of 150 μm, and the connection hole 16H can be a square having a side length of 80 to 100 μm. FIG.
The arrangement of the pad electrodes and the connection holes as shown in FIG.
The same applies to other pad electrodes. FIG.
The width W of the grid line region 18 shown in FIG.
m.

Next, in the step of FIG. 8, as shown in FIG. 18, the bump electrode such as 28a is aligned with the pad electrode such as 14a and the protective substrate 20A is overlaid on the semiconductor wafer 10A.
A predetermined pressure is applied to the protection substrate 20A. Protection substrate 20A
When a transparent material is used, alignment is easy.

Thereafter, the stacked body of the semiconductor wafer 10A to the protection substrate 20A is placed in a vacuum oven and heat-treated at 135 to 150 ° C. for 30 minutes in the above-mentioned pressurized state. As a result, as shown in FIG. 8, the bump electrodes such as 28a and 28b are connected to the pad electrodes such as 14a and 14b, and the semiconductor wafer 10A and the protection substrate 20A are adhered to each other by the adhesive layer 30. The IC formation surface is sealed for each area.

In the heat treatment for sealing, as shown in FIG. 18, the volume corresponding to the thickness of the adhesive layer 30.times.the area corresponding to the opening area of the relief groove 24a and the relief groove 24a are provided between the semiconductor wafer 10A and the protective substrate 20A. There is a space containing the volume of If the pressure in this space is higher than the normal pressure, the thickness of the bump electrode 28a and the adhesive layer 30 due to heating is prevented from decreasing. Therefore, a measure for preventing the pressure increase in the space is required. In this embodiment, a pressure increase is suppressed by performing a heat treatment after the space is previously depressurized, thereby enabling the adhesive layer 30 to flow into the relief groove 24a.

FIG. 19 shows the change in the temperature of the vacuum oven and the change in the pressure in the relief groove in the heat treatment for sealing by curves TM and PR, respectively. In the period P _1, the pressure in the relief groove 24a is reduced toward the vacuum from atmospheric pressure by evacuating the oven. When heating is started at time t ₀ in such a reduced pressure, in the period P _2, the bump electrode 28a and the adhesive layer 3
0 gradually fluidizes, and the bump electrode 28a
H and a part of the adhesive layer 30 escapes into the groove 24a.
Flows into. When the middle of the period P ₂ is increased toward the pressure inside the oven to normal pressure, rises as shown in pressures curve PR in relief groove 24a. Time t ₁ to the end of the period P _2, the surface facing the semiconductor wafer 10A of the protective substrate 20A corresponds to the time of contact with the top of the insulating film 16a. After this point, the pressure in the relief groove 24a hardly changes. As shown in FIG. 8, when the heat treatment is completed in a state where the surface of the protection substrate 20A facing the semiconductor wafer 10A is in contact with the tops of the insulating films 16a and 16b, the semiconductor substrate 1
0A and the protective substrate 20A can be uniformly bonded by the adhesive layer 30.

Next, in the step shown in FIG. 9, on the exposed surface of the protection substrate 20A opposite to the surface facing the semiconductor wafer 10A, 32a, 32a made of solder are connected so as to be connected to conductive plugs such as 26a, 26b, respectively. A bump electrode such as 32b is formed. For this purpose, baking treatment can be performed at 250 ° C. after solder bumps are provided on the ends of each conductive plug by a silk screen printing method or a solder bump dispenser. The height of each bump electrode such as 32a can be 100 to 150 μm.

Thereafter, the stacked body of the semiconductor wafers 10A to 20A is diced along the grid line region 18 to form the cutting grooves 34, thereby forming an IC device including the semiconductor chips 10 to 20 from the stacked body. Is separated. At this time, the IC such as 10a shown in FIG.
An IC device similar to that shown in FIG. 9 is obtained for each chip area.

According to the manufacturing method described above with reference to FIGS. 3 to 19, the protection substrate 20A can be prepared by a simple process in a step different from that of the semiconductor wafer 10A. Also, 26
a and other conductive plugs by bump electrodes such as 28a.
When connecting the semiconductor wafer 10A and the protection substrate 20A with an adhesive layer 30 to seal the IC forming surface when connecting to the pad electrode such as a, etc., the laminate of the semiconductor wafer 10A to the protection substrate 20A is cut and the IC is cut. I tried to separate the equipment,
Both the sealing process and the cutting process can be completed in one step. Therefore, the yield can be improved and the cost can be reduced by simplifying the process.

In the above embodiment, the connection holes such as 16H provided in the insulating film such as 16a are not limited to squares,
As shown in FIG. 20, the shape may be a circle or the like.

Instead of providing bump electrodes such as 28a on the protective substrate 20A, as shown in FIG. 21, they are provided on the semiconductor wafer 10A so as to be connected to pad electrodes such as 14a via connection holes such as 16H. You may. In this case, the sealing process can be performed in the same manner as described above with reference to FIG.

Further, instead of providing the adhesive layer 30 on the protective substrate 20A, the adhesive layer 30 may be provided on the semiconductor wafer 10A. In this case, the sealing process can be performed in the same manner as described above with reference to FIG. The method for forming the adhesive layer 30 on the protective substrate 20A or the semiconductor wafer 10A is not limited to the silk screen printing method, but also includes a method of attaching an adhesive sheet and a method of selectively removing unnecessary portions of the adhesive layer that is entirely applied. A method or the like may be used.

[0047]

As described above, according to the present invention, each pad electrode of the integrated circuit chip is led to the exposed surface side of the protection chip via the bump electrode and the conductive plug with the shortest distance, and the integrated circuit chip is integrated. Since the circuit formation surface is sealed with the protective chip and the adhesive layer, and the integrated circuit chip and the protective chip have substantially the same cut shape, the size of the CSP can be reduced and the terminal wiring length can be reduced.
The effect of realizing a very small integrated circuit device can be obtained.

Further, according to the manufacturing method of the present invention, the protection substrate can be prepared by a simple process in a process different from that for the semiconductor wafer. In addition, when each conductive plug is connected to a corresponding pad electrode by a bump electrode, the semiconductor wafer and the protection substrate are bonded and sealed with an adhesive layer, and then the stacked body of the semiconductor wafer or the protection substrate is cut. In this case, the integrated circuit device is separated by the
It only requires a process. Therefore, the effect that the process can be greatly simplified can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an IC device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line A-A 'of FIG.

3 is a cross-sectional view showing a step of forming a connection hole in a protection substrate in the method of manufacturing the IC device in FIG.

FIG. 4 is a sectional view showing a relief groove forming step following the step of FIG. 3;

FIG. 5 is a cross-sectional view showing a conductive plug forming step following the step of FIG. 4;

FIG. 6 is a cross-sectional view showing a first bump electrode forming step following the step of FIG. 5;

FIG. 7 is a cross-sectional view showing an adhesive layer forming step following the step of FIG. 6;

FIG. 8 is a sectional view showing a sealing step following the step of FIG. 7;

9 is a cross-sectional view showing a second bump electrode forming step and a dicing step following the step of FIG.

FIG. 10 is a perspective view showing a state in which a protective substrate is overlaid on a semiconductor wafer.

FIG. 11 is a perspective view showing an IC chip area.

FIG. 12 is a perspective view showing a protection chip area overlapped with the IC chip area of FIG. 11;

FIG. 13 is a partial cross-sectional perspective view showing a state of formation of connection holes in a protection substrate.

FIG. 14 is a partial cross-sectional perspective view showing a state where a conductive plug is embedded in a connection hole.

FIG. 15 is a partial cross-sectional perspective view showing a state where bump electrodes are formed on conductive plugs.

FIG. 16 is a partial cross-sectional perspective view showing a state where an adhesive layer is formed on a protective substrate.

FIG. 17 is a perspective view showing an example of a pad electrode provided on a semiconductor wafer.

FIG. 18 is a cross-sectional view showing a state in which a protective substrate is overlaid on a semiconductor wafer to perform a sealing process.

FIG. 19 is a graph showing a temperature change of a vacuum oven and a pressure change in a relief groove in a sealing process.

FIG. 20 is a perspective view showing another example of the pad electrode provided on the semiconductor wafer.

FIG. 21 is a perspective view showing a bump electrode provided on a semiconductor wafer.

FIG. 22 is a cross-sectional view showing a bonding step in a conventional method for manufacturing an IC device.

23 is a cross-sectional view showing a groove forming step and a wiring forming step following the step of FIG. 22;

24 is a cross-sectional view showing a dicing step following the step of FIG.

[Explanation of symbols]

10: IC chip, 10A: semiconductor wafer, 10a: I
C chip area, 12, 16a, 16b: insulating film, 14
a, 14b: pad electrode, 18: grid line area,
20: protection chip, 20A: protection substrate, 20a: protection chip area, 22a, 22b: connection hole, 24a, 24b:
Escape groove, 26a, 26b: conductive plug, 28a, 28
b, 32a, 32b, 36a: Bump electrodes.

Claims (6)

[Claims] An integrated circuit chip comprising a semiconductor having an integrated circuit formed on one main surface thereof and a plurality of pad electrodes connected to the integrated circuit formed around the integrated circuit; An insulating protection chip for covering and protecting one of the main surfaces of the plurality of pad electrodes, the insulating chip having a plurality of connection holes respectively corresponding to the plurality of pad electrodes, and a conductive plug embedded in each of the connection holes; Each conductive plug is connected to a corresponding pad electrode by a bump electrode on an opposing surface opposing one main surface of the circuit chip, and the opposing surface is bonded to one main surface of the integrated circuit chip by an adhesive layer. An integrated circuit chip that seals one main surface of the integrated circuit chip, wherein the integrated circuit chip and the protection chip have substantially the same cut shape. 2. A bump electrode is provided at an end of each conductive plug on an exposed surface of the protection chip opposite to a surface facing one main surface of the integrated circuit chip. 2. The integrated circuit device according to 1. 3. A semiconductor wafer having an integrated circuit chip area, wherein an integrated circuit is formed in the integrated circuit chip area, and a plurality of pad electrodes connected to the integrated circuit are formed around the integrated circuit. Providing an insulating protection substrate having a protection chip area for covering and protecting the integrated circuit chip area, wherein the protection chip area has a plurality of pad electrodes respectively corresponding to the plurality of pad electrodes. Providing a connection hole formed therein and a conductive plug buried in each connection hole; and providing a corresponding conductive plug in the protection chip area to a bump electrode for each pad electrode in the integrated circuit chip area. Bonding the semiconductor wafer and the protection substrate with an adhesive layer to seal the integrated circuit chip area as the semiconductor wafer is connected to the semiconductor wafer. Preparation of an integrated circuit device including a step of separating by cutting the integrated circuit device including the integrated circuit chip area to the protected chip area of a laminate of the protective substrate. 4. After the sealing step and before the separating step, another end of each conductive plug in the protection chip region opposite to the end to which the corresponding bump electrode is connected is connected to another end. 4. The method of manufacturing an integrated circuit device according to claim 3, further comprising a step of connecting a bump electrode. 5. In the step of preparing the protection substrate, a relief groove is formed around each connection hole on the main surface side of the protection substrate to be bonded to the semiconductor wafer, so as to allow the adhesive layer to flow therethrough. A method for manufacturing an integrated circuit device according to claim 3. 6. In the step of preparing the protection substrate, an opening size on a main surface of the protection substrate opposite to the main surface is larger than an opening size on a main surface to be bonded to the semiconductor wafer. 6. The method of manufacturing an integrated circuit device according to claim 3, wherein each connection hole is formed as described above.