JP5384483B2 - マルチプレクサを設計する方法及び装置 - Google Patents

マルチプレクサを設計する方法及び装置 Download PDF

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Publication number
JP5384483B2
JP5384483B2 JP2010510350A JP2010510350A JP5384483B2 JP 5384483 B2 JP5384483 B2 JP 5384483B2 JP 2010510350 A JP2010510350 A JP 2010510350A JP 2010510350 A JP2010510350 A JP 2010510350A JP 5384483 B2 JP5384483 B2 JP 5384483B2
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Japan
Prior art keywords
multiplexer
multiplexers
representation
integrated circuit
partition
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JP2010510350A
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English (en)
Japanese (ja)
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JP2010530660A (ja
JP2010530660A5 (enExample
Inventor
ケニス エス マケルヴェイン
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Synopsys Inc
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Synopsys Inc
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Publication of JP2010530660A5 publication Critical patent/JP2010530660A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP2010510350A 2007-05-31 2008-05-30 マルチプレクサを設計する方法及び装置 Active JP5384483B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/809,613 2007-05-31
US11/809,613 US7730438B2 (en) 2007-05-31 2007-05-31 Methods and apparatuses for designing multiplexers
PCT/US2008/006831 WO2008150435A1 (en) 2007-05-31 2008-05-30 Methods and apparatuses for designing multiplexers

Publications (3)

Publication Number Publication Date
JP2010530660A JP2010530660A (ja) 2010-09-09
JP2010530660A5 JP2010530660A5 (enExample) 2011-07-21
JP5384483B2 true JP5384483B2 (ja) 2014-01-08

Family

ID=39748526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010510350A Active JP5384483B2 (ja) 2007-05-31 2008-05-30 マルチプレクサを設計する方法及び装置

Country Status (5)

Country Link
US (1) US7730438B2 (enExample)
EP (1) EP2153360A1 (enExample)
JP (1) JP5384483B2 (enExample)
CN (1) CN101790730B (enExample)
WO (1) WO2008150435A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8751986B2 (en) * 2010-08-06 2014-06-10 Synopsys, Inc. Method and apparatus for automatic relative placement rule generation
JP6127807B2 (ja) * 2013-07-26 2017-05-17 富士通株式会社 送信回路、通信システム及び通信方法
US9361417B2 (en) 2014-02-07 2016-06-07 Synopsys, Inc. Placement of single-bit and multi-bit flip-flops
JP6735095B2 (ja) * 2015-12-25 2020-08-05 ザインエレクトロニクス株式会社 信号多重化装置
US10528692B1 (en) 2017-11-07 2020-01-07 Synopsis, Inc. Cell-aware defect characterization for multibit cells
US12387022B2 (en) * 2022-03-02 2025-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of optimizing an integrated circuit design

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1462964A3 (en) * 1988-10-05 2006-06-07 Quickturn Design Systems, Inc. Method for stimulating functional logic circuit with logical stimulus
US6505337B1 (en) * 1998-11-24 2003-01-07 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables
US6438735B1 (en) * 1999-05-17 2002-08-20 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US6449762B1 (en) * 1999-10-07 2002-09-10 Synplicity, Inc. Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis
US6711729B1 (en) * 2000-12-05 2004-03-23 Synplicity, Inc. Methods and apparatuses for designing integrated circuits using automatic reallocation techniques
US6973632B1 (en) * 2002-06-11 2005-12-06 Synplicity, Inc. Method and apparatus to estimate delay for logic circuit optimization
US7506278B1 (en) * 2005-03-08 2009-03-17 Xilinx, Inc. Method and apparatus for improving multiplexer implementation on integrated circuits

Also Published As

Publication number Publication date
US20080301608A1 (en) 2008-12-04
JP2010530660A (ja) 2010-09-09
EP2153360A1 (en) 2010-02-17
CN101790730B (zh) 2013-10-23
CN101790730A (zh) 2010-07-28
US7730438B2 (en) 2010-06-01
WO2008150435A1 (en) 2008-12-11

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