JP5350184B2 - Multilayer circuit board manufacturing method and multilayer circuit board manufactured by the manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer circuit board having mutually connected electric circuits and interlayer connection holes. <P>SOLUTION: The method of manufacturing the multilayer circuit board includes: forming an insulating layer 20 on a circuit formation surface of a board 10 where circuits 11 are formed; forming holes 21 in the insulating layer 20 from an outer surface and filling the holes 21 with plating metal to form metal columns 22; forming a second insulating layer 23 and a resin film 24 on the outer surface of the insulating layer 20 and tops of the metal columns 22; forming a circuit pattern 25 by forming grooves and holes having predetermined shapes and depths from an outer surface of the resin film 24; bonding a plating catalyst 26 to the surface of the resin film 24 and a surface of the circuit pattern 25; removing the resin film 24 from the second insulating layer 23; subjecting the insulating layer 20 and second insulating layer 23 to electroless plating to form an electroless plating film at the part of the circuit pattern 25 and exposed parts of the metal columns 22; and forming circuits 27 on the insulating layer 20 and second insulating layer 23 and making interlayer connections between the circuits 11 and circuits 27 through the metal columns 22. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention belongs to the technical field of multilayer circuit boards, and relates to a method of manufacturing a multilayer circuit board using an additive method and a multilayer circuit board manufactured by the manufacturing method.

  2. Description of the Related Art In recent years, functions of mobile information terminal devices such as mobile phones, computers and peripheral devices, and various information home appliances have been highly advanced. Accordingly, circuit boards mounted on these electric devices are increasingly required to have higher density of electric circuits. In order to realize such a high density circuit board, a method for accurately forming a circuit having a narrower line width and line spacing is required. In high-density wiring, short-circuiting or migration between wirings is likely to occur. Further, in a narrow width wiring, the mechanical strength of the wiring is lowered, and the circuit is easily cut off by an impact or the like. Furthermore, as the number of stacked layers increases, the unevenness generated on the circuit formation surface becomes larger, so that it becomes difficult to form a fine circuit.

  Conventionally, a subtractive method and an additive method are known as a method of forming a circuit on a circuit board. The subtractive method is a method of forming a circuit by removing (subtractive) a metal foil other than a portion where a circuit is desired to be formed on the surface of the metal foil-clad laminate. On the other hand, the additive method is a method of forming a circuit by performing electroless plating only on a portion on the insulating base material where the circuit is to be formed.

  In general, the subtractive method is a method of leaving a metal foil only in a circuit formation portion by etching a thick metal foil. According to this method, a portion of the metal to be removed is wasted. On the other hand, the additive method does not waste metal because the electroless plating film can be formed only on the portion where the metal wiring is to be formed. Also in this respect, the additive method is a preferable circuit forming method.

  The full additive method, which is one of conventional representative additive methods, is performed as follows, for example. First, a plating catalyst is deposited on the surface of the insulating substrate. Next, a photoresist layer is formed on the plating catalyst. Next, the surface of the photoresist layer is exposed through a photomask on which a predetermined circuit pattern is formed. Next, the circuit pattern is developed. Then, by applying electroless plating to the surface of the circuit pattern formed by development, metal wiring is formed on the circuit pattern portion. An electric circuit is formed on the insulating base material by such a process.

  In the conventional additive method described above, the plating catalyst is deposited on the entire surface of the insulating substrate. As a result, the following problems have arisen. That is, when the photoresist layer is developed with high accuracy, the plating film can be formed only on the portion not protected by the photoresist. However, if the photoresist layer is not developed with high accuracy, a plating film may be unnecessarily formed in a portion where a circuit is not originally desired to be formed. This occurs because the plating catalyst is deposited on the entire surface of the insulating substrate. Unnecessarily formed plating films cause short circuits and migration between adjacent circuits. Such a short circuit or migration is more likely to occur when a circuit having a narrow line width and line interval is formed.

  In order to cope with such a problem, for example, it is conceivable to apply the following technique described in Patent Document 1. First, a protective film of resin is coated on the insulating substrate. Next, grooves and through holes corresponding to the circuit pattern are drawn and formed on the insulating substrate coated with the protective film by machining or laser beam irradiation. Next, an activation layer is formed on the entire surface of the insulating substrate. Next, the activation layer is left only on the inner wall surface of the groove and the through hole by peeling off the resin protective film. Then, by plating the insulating base material, a conductive layer is selectively formed only on the inner surfaces of the activated grooves and through holes.

  In connection with this technology, the applicant of the present invention relates to an invention in which a plating catalyst for electroless plating is left with high accuracy only on a portion where electroless plating is desired, such as a circuit pattern portion or an inner wall surface of a through hole. Patent applications have already been filed (Japanese Patent Application No. 2008-118818 and Japanese Patent Application No. 2009-104086 based on this). A circuit forming method according to this patent application will be described with reference to FIG.

  First, as shown in FIG. 5A, a resin film b is coated on the surface of the insulating base material a. Next, as shown in FIG. 5B, a groove c or a through hole d having a desired circuit pattern is formed on the insulating base material a coated with the resin film b. In FIG. 5B, the bottom surface of the groove c coincides with the surface of the insulating base material a, but the groove c may be dug deeper than the surface of the insulating base material a. Next, as shown in FIG. 5C, a plating catalyst e is deposited on the surface of the groove c and the through hole d and the surface of the resin film b. Here, the plating catalyst is a concept including its precursor. Next, as shown in FIG. 5D, the plating film e is left only on the surfaces of the groove c and the through hole d by peeling off the resin film b. Then, as shown in FIG. 5E, a circuit in which a conductive layer is accurately formed only on the inner wall surfaces of the groove c and the through hole d by forming the electroless plating film f only on the portion where the plating catalyst e remains. A substrate x is obtained.

JP 58-186994 A

  By the way, in recent years, as a method for manufacturing a high-density multilayer circuit board, there is known a build-up method in which an electric circuit of each layer is sequentially formed one by one and stacked while forming a via hole as an interlayer connection hole. . However, when the additive method as described with reference to FIGS. 5A to 5E is applied to such a build-up method, the following problem may occur. This problem will be described with reference to FIG.

  First, as shown in FIG. 6A, a circuit board g on which a first electric circuit h is formed is prepared. In FIG. 6A, the circuit h is mounted on the upper surface of the circuit board g, but may be embedded in the upper surface of the circuit board g. The method for forming the first circuit h is not limited here. Next, as shown in FIG. 6B, an insulating layer i is formed on the upper surface of the circuit board g on which the first circuit h is formed. Next, as shown in FIG. 6C, a resin film j is formed on the upper surface (outer surface) of the insulating layer i. Next, as shown in FIG. 6D, by performing laser processing from the outer surface of the formed resin film j, a circuit pattern k having a depth greater than or equal to the thickness of the resin film j and an interlayer connection hole m are formed. The circuit pattern k includes a wiring groove, an electrode pad hole, and the like. The interlayer connection hole m reaches the first circuit h of the circuit board g and exposes the first circuit h.

  Next, as shown in FIG. 6E, a plating catalyst n is deposited on the surface of the resin film j, the surface of the circuit pattern k, the surface of the interlayer connection hole m, and the exposed surface of the first circuit h. From the viewpoint of electroless plating, which will be described later, it is not necessary to apply the plating catalyst n to the surface of the first circuit h, but the work can be facilitated by applying the plating catalyst n to the entire insulating layer i. Is achieved. Next, as shown in FIG. 6F, the resin film j is removed from the insulating layer i. Then, as shown in FIG. 6G, by subjecting the insulating layer i to electroless plating, an electroless plating film is formed in the portion of the circuit pattern k where the plating catalyst n remains, and the second electric circuit is formed on the insulating layer i. p is formed. In addition, by growing an electroless plating film from the first circuit h at the bottom of the interlayer connection hole m, the interlayer connection hole m is filled with a plating metal to form a metal column q. As a result, the second circuit p of the insulating layer i and the first circuit h of the circuit board g are interlayer-connected through the metal pillar q.

  However, if the conductor of the circuit pattern k portion and the interlayer connection hole m portion is simultaneously formed by electroless plating, the wiring groove in the circuit portion has a fine line width and a shallow depth. Since the hole for the part is also shallow, both of them complete the conductor formation in a short time, but the hole for the interlayer connection is larger than the line width of the wiring groove and the depth is deeper than the circuit part. It takes a long time to fill with plating metal. Therefore, when the electroless plating is completed at the time when the conductor formation of the circuit portion is completed, as illustrated in FIG. 6G, the metal filling of the interlayer connection hole is insufficient, and the connection between the circuit and the interlayer connection hole is poor. Cause. On the other hand, if electroless plating is continued until the interlayer connection holes are sufficiently filled with metal, the conductor formation in the circuit portion becomes excessive and short circuits or the like are likely to occur. In addition, it is conceivable to reduce the volume of the interlayer connection hole so that the metal filling of the interlayer connection hole can be completed in a short time. For this purpose, the depth of the interlayer connection hole can be reduced, or the interlayer connection hole can be reduced. It is proposed to reduce the diameter of the. However, the former is often difficult in designing a circuit board and is difficult to realize. In the latter, the contact area between the interlayer connection hole and the circuit is reduced, and the reliability of the interlayer connection is lowered. If the diameter of the interlayer connection hole is made smaller than or equal to the width of the circuit pattern wiring groove, the metal filling is completed in a short time. In addition to growing from the bottom, it also grows from the circuit pattern side, so voids are easily generated inside the metal pillar.

  The present invention is intended to solve the above-described problems when the additive method is applied when manufacturing a multilayer circuit board by the build-up method, and even if a fine circuit pattern and interlayer connection holes are mixed. Another object of the present invention is to provide a method for manufacturing a multilayer circuit board, in which the metal filling of the interlayer connection holes is sufficiently and satisfactorily performed and excessive conductor formation in the circuit portion can be avoided.

  That is, the method for manufacturing a multilayer circuit board according to the present invention is a method for manufacturing a multilayer circuit board having interconnected electrical circuits and interlayer connection holes, and the circuit board circuit on which the first electrical circuit is formed. A first insulating layer forming step of forming a first insulating layer on a forming surface; a hole forming step of forming a hole in the first insulating layer from an outer surface to expose the first electric circuit; A metal column forming step of forming a metal column by filling the hole with plating metal from an electric circuit, and forming a second insulating layer on the outer surface of the first insulating layer and the top of the metal column A step of forming a resin film on the outer surface of the second insulating layer, a predetermined depth not less than a total value of at least the thickness of the resin film and the thickness of the second insulating layer from the outer surface of the resin film And forming grooves and / or holes having a predetermined shape A circuit pattern forming process for forming a circuit pattern, a catalyst deposition process for depositing a plating catalyst on the surface of the resin film and the surface of the circuit pattern, a film removal process for removing the resin film from the second insulating layer, And, by applying electroless plating to the first insulating layer and the second insulating layer, a plating film is formed on the portion of the circuit pattern where the plating catalyst remains and the exposed portion of the metal pillar, thereby forming the first insulating layer. And a plating step of forming a second electric circuit in the second insulating layer and inter-layer-connecting the second electric circuit of the insulating layer and the first electric circuit of the circuit board via the metal pillars, Is provided.

  According to the above configuration, the first insulating layer forming step, the hole forming step, and the metal pillar forming step before forming the circuit pattern are previously filled with the plated metal only in the interlayer connection hole. Without worrying about conductor formation, the metal filling of the interlayer connection holes can be sufficiently performed over time. In addition, since the circuit pattern is not yet formed, the plating film does not grow from the circuit pattern side, and good metal filling with suppressed generation of voids is realized. Then, after the metal filling of the interlayer connection holes is completed, the second insulating layer forming step, the film forming step, the circuit pattern forming step, the catalyst deposition step, the film removing step, and the plating step are performed. Since the conductor formation of the circuit portion is performed by the additive method as described, a fine conductor can be accurately formed in a short time, and excessive formation of the conductor in the circuit portion is avoided. As described above, even when a fine circuit pattern and interlayer connection holes are mixed, a multilayer circuit board can be produced without any problem by the build-up method while applying the additive method satisfactorily.

  The “metal pillar” formed in the metal pillar forming step is not limited as long as it has a thickness larger than that of the conductor layer constituting the electric circuit and is a conductive convex portion protruding substantially perpendicular to the electric circuit. Is not particularly limited. For example, in addition to a columnar shape having a constant cross-sectional shape such as a cylinder or a prism, a truncated cone shape or a truncated pyramid shape whose cross-sectional shape changes in the length direction is also included.

  The “groove” of the circuit pattern formed in the circuit pattern forming step is mainly a groove for wiring, and the “hole” is, for example, a hole for an electrode pad portion. However, depending on the situation, it may be an interlayer connection hole (an interlayer connection hole different from the one that has been previously filled with metal).

  Further, according to the above configuration, the second insulating layer is formed on the outer surface of the first insulating layer, the resin film is formed on the outer surface of the second insulating layer, and at least the thickness of the resin film and the thickness of the second insulating layer Since the resin film is removed after the circuit pattern having a depth equal to or greater than the total value is formed, the second insulating layer is always processed and removed. Therefore, the bottom surface of the circuit pattern is located at a position dug down from the outer surface of the second insulating layer, and the conductor layer constituting the electric circuit is partially or entirely embedded in the outer surface of the second insulating layer. . As a result, the thickness of the conductor layer can be increased, and the mechanical strength of the circuit can be ensured. Further, the amount of protrusion of the conductor layer from the second insulating layer can be eliminated or reduced to protect the circuit, suppress the falling of the circuit from the insulating layer, and eliminate or reduce irregularities generated on the circuit formation surface. It becomes possible.

  In the present invention, in the circuit pattern forming step, the circuit pattern is formed so that the top of the metal pillar is exposed and protrudes from the bottom surface of the circuit pattern, and the second electric circuit formed so as to cover the top of the metal pillar It is preferable that this part is an electrode pad part. This is because the top portion of the metal pillar bites into the conductor layer of the pad portion, and the drop-off of the pad portion is effectively suppressed by the anchor effect, and a pad portion that can sufficiently withstand the weight of the mounted component is obtained.

  Moreover, in this invention, you may form a circuit pattern so that the top part of a metal pillar may be exposed and may not protrude from the bottom face of a circuit pattern at a circuit pattern formation process. In this case, it is possible to avoid the conductor layer formed on the top of the metal pillar from protruding from the outer surface of the insulating layer, and it is possible to eliminate the unevenness generated on the circuit forming surface.

  In that case, it is possible to prevent the top of the metal pillar from being exposed and protruding in the circuit pattern forming process by filling the plated metal up to the position which becomes the bottom surface of the circuit pattern in the metal pillar forming process. is there. That is, when the bottom surface of the circuit pattern coincides with the outer surface of the first insulating layer, the metal pillar may be grown to the outer surface of the first insulating layer. On the other hand, when the bottom surface of the circuit pattern is in a position dug down from the outer surface of the first insulating layer, the metal pillar is not grown to the outer surface of the first insulating layer, but is grown at a height earlier than that. It stops. Thereby, it can be easily achieved that the top of the metal pillar does not protrude from the bottom surface of the circuit pattern at the stage of the metal pillar forming process prior to the circuit pattern forming process.

  Alternatively, after the metal pillar forming step, the top of the metal pillar can be removed to the position that becomes the bottom surface of the circuit pattern, so that the top of the metal pillar can be exposed and not protruded in the circuit pattern forming process. It is. Accordingly, it is possible to reliably achieve the correction of the position of the top of the metal column so that the top of the metal column does not protrude from the bottom surface of the circuit pattern.

  In the present invention, in the metal column forming step, the hole can be filled with the plating metal by growing the plating film from the exposed first electric circuit by electroless plating. Since the electric circuit which is a conductor is used as a plating nucleus of electroless plating, a metal column can be rationally formed.

  In the present invention, in the metal column forming step, a plating catalyst is deposited on the surface of the first insulating layer, the inner wall surface of the hole, and the exposed surface of the first electric circuit. After electrolytic plating, electrolytic plating is performed to fill the holes with plating metal, and then the plating metal deposited on the outer surface side of the first insulating layer including the surface of the first insulating layer can be removed. Good. Since the electroless plating layer formed on the outer surface side of the first insulating layer including the surface of the first insulating layer is used as a power feeding layer necessary for electrolytic plating, a metal column can be rationally formed.

  In the present invention, the resin film is preferably a resin film that can be dissolved or removed from the insulating layer by dissolving or swelling with a predetermined liquid. By using such a resin film, the resin film can be easily and satisfactorily removed from the surface of the insulating layer. If the resin film is collapsed when removing the resin film, the plating catalyst deposited on the resin film will be scattered, and the scattered plating catalyst will be re-deposited on the insulating layer, and an unnecessary plating film will be formed on that part. There is a problem. Such a problem can be prevented because the resin film can be easily and satisfactorily removed from the surface of the insulating layer.

  And the multilayer circuit board of this invention is a multilayer circuit board manufactured by the above manufacturing methods. Therefore, even if a fine circuit pattern and an interlayer connection hole are mixed, the metal filling of the interlayer connection hole is sufficiently and satisfactorily performed, and the connection between the circuit and the interlayer connection hole is good. Excessive conductor formation in the portion is avoided, and a multilayer circuit board in which a short circuit or the like hardly occurs is obtained.

  According to the present invention, even if a fine circuit pattern and interlayer connection holes are mixed, a multilayer circuit board can be produced without any problem by the build-up method while applying the additive method satisfactorily. In addition, since an electric circuit embedded in the insulating layer can be obtained, it is possible to secure the mechanical strength of the circuit, protect the circuit, suppress the falling off of the circuit from the insulating layer, suppress unevenness generated on the circuit forming surface, etc. It is done.

It is a fragmentary top view for showing the structure of the electric circuit in the multilayer circuit board which concerns on embodiment of this invention, arrangement | positioning of the hole for interlayer connection, etc. FIG. FIG. 2 is an end view taken along line II of FIG. 1, and (A) a circuit board preparation step, (B) a first insulating layer formation step, and (C) a hole in the multilayer circuit board manufacturing method according to the first embodiment. Forming step, (D) metal column forming step, (E) second insulating layer forming step and film forming step, (F) circuit pattern forming step, (G) catalyst deposition step, (H) film removing step, and ( I) It is a figure which shows a plating process. It is an end elevation which meets the II line of Drawing 1, and (A) circuit board preparatory process in the manufacturing method of the multilayer circuit board concerning a 2nd embodiment, (B) 1st insulating layer formation process, (C) hole Forming step, (D) metal column forming step, (E) second insulating layer forming step and film forming step, (F) circuit pattern forming step, (G) catalyst deposition step, (H) film removing step, and ( I) It is a figure which shows a plating process. It is an end elevation which meets an II line of Drawing 1, and (A) circuit board preparation process in a manufacturing method of a multilayer circuit board concerning a 3rd embodiment, (B) 1st insulating layer formation process, (C) hole Forming step, (D) metal column forming step, (E) second insulating layer forming step and film forming step, (F) circuit pattern forming step, (G) catalyst deposition step, (H) film removing step, and ( I) It is a figure which shows a plating process. It is process drawing for demonstrating formation of the circuit of the circuit board by an additive method. FIG. 10 is a process diagram for explaining a problem when the additive method is applied when manufacturing a multilayer circuit board by a build-up method.

[First Embodiment]
FIG. 1 is a partial plan view for illustrating the configuration of the electric circuit 27 and the arrangement of the interlayer connection holes 21 (or the metal pillars 22) in the multilayer circuit board 1 according to the present embodiment. As shown in the drawing, in the present embodiment, the multilayer circuit board 1 in which the electric circuit 27 and the via hole which is the interlayer connection hole 21 are connected to each other is manufactured. The circuit 27 includes a wiring 27a having a fine line width and an electrode pad portion 27b. The electrode pad portion 27 b is provided so as to overlap the interlayer connection hole 21.

  The II line in FIG. 1 shows the cutting location of the end view of FIGS. In FIG. 2, reference numeral 10 is a circuit board, reference numeral 11 is a first electric circuit, reference numeral 20 is a first insulating layer, reference numeral 21 is an interlayer connection hole, reference numeral 22 is a metal pillar, reference numeral 23 is a second insulating layer, reference numeral 24. Is a resin film, 25 is a circuit pattern, 26 is a plating catalyst, 27 is a second electric circuit, and 30 is the entire insulating layer including the first insulating layer 20 and the second insulating layer 23. As shown in FIG. 2I, in the multilayer circuit board 1, the first electric circuit 11 formed on the circuit board 10 and the insulating layer 30 (the first insulating layer 20 and the second insulating layer 20 stacked on the circuit board 10). The second electrical circuit 27 formed in the insulating layer 23) is interlayer-connected through an interlayer connection hole 21 (or metal pillar 22) formed in the first insulating layer 20.

<Circuit board preparation process>
In the manufacturing method of the present embodiment, first, as shown in FIG. 2A, the circuit board 10 on which the first electric circuit 11 is formed is prepared (circuit board preparation step). In FIG. 2A, the first circuit 11 is placed on the upper surface of the circuit board 10, but may be embedded in the upper surface of the circuit board 10. Further, the method for forming the first circuit 11 is not limited here. For example, it may be formed by a conventionally known circuit forming method such as a subtractive method or an additive method. Further, the circuit board may be formed on only one side or may be formed on both sides. A multilayer circuit board may also be used.

  As the circuit board 10, various organic substrates conventionally used for manufacturing a multilayer circuit board can be used without any particular limitation. Specific examples of the organic substrate include substrates made of epoxy resin, acrylic resin, polycarbonate resin, polyimide resin, polyphenylene sulfide resin, polyphenylene ether resin, cyanate resin, benzoxazine resin, bismaleimide resin, and the like. The form of the circuit board 10 is not particularly limited, such as a sheet, a film, a prepreg, and a three-dimensional shaped molded body. The thickness of the circuit board 10 is also not particularly limited. For example, in the case of a sheet, a film, a prepreg, etc., the thickness is about 10 to 500 μm, preferably about 20 to 200 μm. In addition, the detailed description of the circuit board 10 is the same as the detailed description of the first insulating layer 20 described below.

<Insulating layer formation process>
Next, as shown in FIG. 2B, the first insulating layer 20 is formed on the upper surface (circuit forming surface) of the circuit board 10 on which the first circuit 11 is formed (first insulating layer forming step). The form of the first insulating layer 20 is not particularly limited. Specific examples include a sheet, a film, a prepreg, and a three-dimensional molded article formed by applying a resin solution. The thickness of the first insulating layer 20 is not particularly limited. Specifically, in the case of a sheet, film, or prepreg, for example, the thickness is preferably 10 to 200 μm, and more preferably about 20 to 100 μm. Further, the first insulating layer 20 may contain inorganic fine particles such as silica particles. The first insulating layer 20 can be formed, for example, by laminating a sheet, a film, or a prepreg on the upper surface of the circuit board 10, pressing and bonding, and curing, or by curing by heating and pressing. it can. The first insulating layer 20 can also be formed by applying a resin solution to the upper surface of the circuit board 10 and then curing it. In addition, a material to be an insulating layer may be put in using a mold and a frame mold, and pressed and cured to form a three-dimensional molded body, or a sheet, film, or prepreg is punched out. A three-dimensional shaped molded body or the like may be formed by laminating the hollowed material on the upper surface of the circuit board 10 and pressurizing and then curing, or curing by heating and pressing.

  As the first insulating layer 20, various organic substrates conventionally used for manufacturing a multilayer circuit board can be used without any particular limitation. Specific examples of organic substrates include those conventionally used in the manufacture of multilayer circuit boards, such as epoxy resins, acrylic resins, polycarbonate resins, polyimide resins, polyphenylene sulfide resins, polyphenylene ether resins, cyanate resins, benzoxazine resins, bis Examples include a substrate made of maleimide resin or the like.

  The epoxy resin is not particularly limited as long as it is an epoxy resin constituting various organic substrates that can be used for manufacturing a circuit board. Specifically, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, aralkyl epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol type epoxy resin, naphthalene type epoxy resin , Dicyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, alicyclic epoxy resins, and the like. Furthermore, the epoxy resin, nitrogen-containing resin, and silicone-containing resin that are brominated or phosphorus-modified to impart flame retardancy are also included. Moreover, as said epoxy resin and resin, said each epoxy resin and resin may be used independently, and may be used in combination of 2 or more type.

  Moreover, when comprising a base material with said each resin, in order to make it harden | cure, a hardening | curing agent is generally contained. The curing agent is not particularly limited as long as it can be used as a curing agent. Specific examples include dicyandiamide, phenolic curing agents, acid anhydride curing agents, aminotriazine novolac curing agents, and cyanate resins.

  As said phenol type hardening | curing agent, a novolak type, an aralkyl type, a terpene type etc. are mentioned, for example. Further examples include phosphorus-modified phenolic resins or phosphorus-modified cyanate resins for imparting flame retardancy. Moreover, as said hardening | curing agent, said each hardening | curing agent may be used independently, and may be used in combination of 2 or more type.

  Although not particularly limited, it is preferable to use a resin or the like that has a good laser light absorption rate in a wavelength region of 100 nm to 400 nm because a circuit pattern is formed by laser processing. For example, specifically, a polyimide resin or the like can be given.

  The insulating base material (insulating layer) may contain a filler. The filler may be inorganic fine particles or organic fine particles, and is not particularly limited. By containing the filler, the filler is exposed in the laser processed part, and it is possible to improve the adhesion between the plating due to the unevenness of the filler and the resin.

Specific examples of the material constituting the inorganic fine particles include aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), boron nitride (BN), aluminum nitride (AlN), silica (SiO ₂ ), High dielectric constant fillers such as barium titanate (BaTiO ₃ ) and titanium oxide (TiO ₂ ); magnetic fillers such as hard ferrite; magnesium hydroxide (Mg (OH) ₂ ), aluminum hydroxide (Al (OH) ₂ ), Antimony trioxide (Sb ₂ O ₃ ), antimony pentoxide (Sb ₂ O ₅ ), guanidine salts, zinc borate, molybdate compounds, zinc stannate, and other inorganic flame retardants; talc (Mg ₃ (Si ₄ O ₁₀₎ (OH) 2), barium sulfate (BaSO _4), calcium carbonate (CaCO _3), mica, and the like. As said inorganic fine particle, the said inorganic fine particle may be used independently, and may be used in combination of 2 or more type. Since these inorganic fine particles have high thermal conductivity, relative dielectric constant, flame retardancy, particle size distribution, color tone freedom, etc., when selectively exerting a desired function, appropriate blending and particle size design should be performed. And high filling can be easily performed. Although not particularly limited, it is preferable to use a filler having an average particle diameter equal to or smaller than the thickness of the insulating layer, more preferably 0.01 μm to 10 μm, and still more preferably a filler having an average particle diameter of 0.05 μm to 5 μm. It is good.

  The inorganic fine particles may be surface-treated with a silane coupling agent in order to improve dispersibility in the insulating base material. The insulating base material may contain a silane coupling agent in order to increase the dispersibility of the inorganic fine particles in the insulating base material. The silane coupling agent is not particularly limited. Specific examples include silane coupling agents such as epoxy silane, mercapto silane, amino silane, vinyl silane, styryl silane, methacryloxy silane, acryloxy silane, and titanate. As said silane coupling agent, the said silane coupling agent may be used independently, and may be used in combination of 2 or more type.

  The insulating base material may contain a dispersant in order to enhance the dispersibility of the inorganic fine particles in the insulating base material. The dispersant is not particularly limited. Specific examples include dispersants such as alkyl ether, sorbitan ester, alkyl polyether amine, and polymer. As said dispersing agent, the said dispersing agent may be used independently, and may be used in combination of 2 or more type.

  Specific examples of the organic fine particles include rubber fine particles.

  Further, for example, when prepreg is used as the circuit board 10 and the first insulating layer 20, the first insulating layer 20 is overlaid on the upper surface (circuit formation surface) of the circuit board 10, and is heated and pressed to be laminated and cured. May be.

  It should be noted that the type of material constituting the circuit board 10 and the type of resin, and the type of material constituting the first insulating layer 20 and the type of resin may be different from each other. However, from the viewpoint of satisfactorily adhering and laminating the circuit board 10 and the first insulating layer 20, it is preferable that the types be familiar with each other, and it is more preferable that the types are typically the same.

<Hole formation process>
Next, as shown in FIG. 2C, interlayer connection holes 21 are formed in the first insulating layer 20 from the upper surface (outer surface) by laser processing from the upper surface (outer surface) side of the first insulating layer 20 ( Hole formation step). At this time, the interlayer connection hole 21 reaches the first circuit 11 of the circuit board 10 and exposes the first circuit 11. In addition, the detailed description of the laser processing and the peripheral technology is the same as the detailed description of the laser processing and the peripheral technology described in other steps.

  Note that a smear (not shown) that is a resin residue of the first insulating layer 20 remains on the first circuit 11 exposed by the laser processing. Since smear causes conduction failure, it is preferably removed by desmear treatment. As the desmear treatment, for example, a known method such as dissolving and removing smear by immersing in a permanganic acid solution is used without limitation. However, the desmear process can be omitted depending on the situation.

<Metal pillar formation process>
Next, as shown in FIG. 2D, the interlayer connection hole 21 is filled with plating metal from the exposed first circuit 11 by electroless plating or electrolytic plating, and the metal column 22 is filled in the interlayer connection hole 21. (Metal pillar forming step). In the case of electroless plating, the first circuit 11 functions as a plating nucleus, and a plating film grows from the first circuit 11. On the other hand, in the case of electrolytic plating, a plating catalyst is applied to the surface of the first insulating layer 20, the inner wall surface of the hole 21, and the exposed surface of the first circuit 11, and electroless plating is applied to the plating catalyst applied portion. After the application, electrolytic plating is performed to fill the holes 21 with the plating metal, and thereafter, the plating metal deposited on the outer surface side of the first insulating layer 20 including the surface of the first insulating layer 20 is removed.

  The shape, size, interval and the like of the metal pillar 22 are not particularly limited. Specifically, for example, a metal column 22 having a substantially cylindrical shape and a height of about 5 to 200 μm and a bottom surface diameter of about 10 to 500 μm can be preferably realized. A metal column 22 having a prism shape, a truncated cone shape, or a truncated pyramid shape may be used.

  FIG. 2D shows a case where the metal column 22 has grown to the height of the outer surface (upper surface) of the first insulating layer 20 in this metal column forming step.

  According to such a method, the first circuit 11 and the second circuit 26 are formed before the second insulating layer 23 is formed in the second insulating layer forming step, which will be described later, and before the resin film 24 is formed in the film forming step. It is possible to form the interlayer connection hole 21 that connects the two layers with a sufficient amount of a good metal column 22 in which generation of voids is suppressed.

<Second insulating layer forming step>
Next, as shown in FIG. 2E, a second insulating layer 23 is formed on the outer surface of the first insulating layer 20 and the top of the metal pillar 22 (second insulating layer forming step). The second insulating layer 23 is the same as that of the first insulating layer 20. Specifically, examples of the second insulating layer 23 include a sheet, a film, a prepreg, and a three-dimensional molded body formed by applying a resin solution. The thickness of the second insulating layer 23 is not particularly limited. Specifically, in the case of a sheet, film, or prepreg, for example, it is preferably 3 to 50 μm, and more preferably about 5 to 40 μm. Further, the second insulating layer 23 may contain inorganic fine particles such as silica particles.

  The second insulating layer 23 may be formed by, for example, laminating a sheet, a film, and a prepreg on the outer surface of the first insulating layer 20 and pressurizing them, followed by curing, or the first insulating layer You may form by apply | coating a resin solution to the outer surface of 20, and making it harden | cure. Alternatively, a three-dimensional shaped molded body or the like may be formed by putting a material for the second insulating layer 23 using a mold, a frame mold, or the like, pressurizing, and curing.

  As the second insulating layer 23, various organic substrates conventionally used for manufacturing a multilayer circuit board can be employed without any particular limitation. Specific examples of organic substrates include those conventionally used in the manufacture of multilayer circuit boards, such as epoxy resins, acrylic resins, polycarbonate resins, polyimide resins, polyphenylene sulfide resins, polyphenylene ether resins, cyanate resins, benzoxazine resins, bis Examples include a substrate made of maleimide resin or the like. In addition, the detailed description of the second insulating layer 23 is the same as the detailed description of the first insulating layer 20 described above.

  It should be noted that the type of material and the type of resin that constitute the first insulating layer 20 and the type of material and the type of resin that constitute the second insulating layer 23 may be different from each other. However, from the viewpoint of satisfactorily adhering and laminating the first insulating layer 20 and the second insulating layer 23, it is preferable that the types be familiar with each other, and typically the same types are more preferable. .

<Film formation process>
Next, as shown in FIG. 2E, a resin film 24 is formed on the outer surface of the second insulating layer 23 (film formation process). The resin film (resist) 24 is not particularly limited as long as it can be removed by a film removal step described later. The resin film 24 is preferably a resin film that can be easily dissolved or removed from the surface of the second insulating layer 23 by dissolving or swelling with a predetermined liquid. Specifically, for example, a film made of a soluble resin that can be easily dissolved by an organic solvent or an alkaline solution, a film made of a swellable resin that can swell with a predetermined liquid (swelling liquid), and the like can be given. In addition, the swellable resin film does not substantially dissolve in a predetermined liquid, and not only a resin film that easily peels off from the surface of the second insulating layer 23 by swelling, but also in a predetermined liquid. Resin film that swells and dissolves at least in part and easily peels off from the surface of the second insulating layer 23 by the swelling and dissolution, or a predetermined liquid, and the second insulating layer by the dissolution A resin film that easily peels from the surface of 23 is also included. By using such a resin film, the resin film can be easily and satisfactorily removed from the surface of the insulating layer. If the resin film is collapsed when removing the resin film, the plating catalyst deposited on the resin film will be scattered, and the scattered plating catalyst will be re-deposited on the insulating layer, and an unnecessary plating film will be formed on that part. There is a problem. Such a problem can be prevented because the resin film can be easily and satisfactorily removed from the surface of the insulating layer.

  The method for forming the resin film 24 is not particularly limited. Specifically, for example, after applying a liquid material capable of forming the resin film 24 on the outer surface (upper surface) of the second insulating layer 23, a method of drying, or after applying the liquid material to the support substrate, Examples thereof include a method of transferring a resin film formed by drying onto the surface of the second insulating layer 23. Another method includes a method of bonding a resin film made of a resin film 24 formed in advance to the outer surface (upper surface) of the second insulating layer 23. The method for applying the liquid material is not particularly limited. Specifically, for example, conventionally known spin coating method, bar coater method and the like can be mentioned.

  As a material for forming the resin film 24, any resin can be used without particular limitation as long as it can be easily dissolved or removed from the surface of the second insulating layer 23 by dissolving or swelling with a predetermined liquid. . Preferably, a resin having a degree of swelling with respect to a predetermined liquid is 50% or more, more preferably 100% or more, and still more preferably 500% or more. In addition, when the degree of swelling is too low, the resin film tends to be difficult to peel.

  In addition, the swelling degree (SW) of the resin film can be calculated from the weight m (b) before swelling and the weight m (a) after swelling by “swelling degree SW = {(m (a) −m (b)) / m (b )} × 100 (%) ”.

  Such a resin film is formed by applying an elastomer suspension or emulsion to the surface of the second insulating layer 23 and then drying, or by applying an elastomer suspension or emulsion to the support substrate and then drying. The film can be easily formed by a method of transferring the film to the surface of the second insulating layer 23 or the like.

  Specific examples of the elastomer include diene elastomers such as a styrene-butadiene copolymer, acrylic elastomers such as an acrylate ester copolymer, and polyester elastomers. According to such an elastomer, a resin film having a desired swelling degree can be easily formed by adjusting the degree of crosslinking or gelation of the elastomer resin particles dispersed as a suspension or emulsion.

  Such a resin film is particularly preferably a film whose degree of swelling changes depending on the pH of the swelling liquid. In the case of using such a film, the liquid condition in the catalyst deposition process described later is different from the liquid condition in the film removal process described later, so that the resin is used at the pH in the catalyst deposition process. The film 24 maintains high adhesion to the second insulating layer 23, and the resin film 24 can be easily peeled and removed at the pH in the film removal step.

  More specifically, for example, the catalyst deposition step described later includes a step of treating in an acidic catalyst metal colloid solution having a pH in the range of 1 to 3, for example, and the coating removal step described later is alkaline in the range of pH 12 to 14. When the step of swelling the resin film in a solution is provided, the resin film has a swelling degree of 60% or less, further 40% or less with respect to the acidic catalyst metal colloid solution, and a swelling degree with respect to the alkaline solution of 50% or less. % Or more, preferably 100% or more, and more preferably 500% or more.

  Examples of such a resin film are used for a sheet formed from an elastomer having a predetermined amount of carboxyl groups, a dry film resist for patterning a printed wiring board (hereinafter sometimes referred to as “DFR”), and the like. Examples thereof include a sheet obtained by completely curing a photocurable alkali-developing resist, a thermosetting or alkali-developing sheet, and the like.

  Specific examples of the elastomer having a carboxyl group include diene elastomers such as a styrene-butadiene copolymer having a carboxyl group in the molecule by containing a monomer unit having a carboxyl group as a copolymerization component, and acrylic. Examples include acrylic elastomers such as acid ester copolymers, and polyester elastomers. According to such an elastomer, a resin film having a desired degree of alkali swelling can be formed by adjusting the acid equivalent, the degree of crosslinking or the degree of gelation of the elastomer dispersed as a suspension or emulsion. Moreover, the swelling degree with respect to the predetermined liquid used in a film removal process can be increased, and a resin film that dissolves in the liquid can be easily formed. The carboxyl group in the elastomer swells the resin film with respect to the alkaline aqueous solution and acts to peel the resin film from the surface of the second insulating layer 23. The acid equivalent is the polymer molecular weight per carboxyl group.

  Specific examples of the monomer unit having a carboxyl group include (meth) acrylic acid, fumaric acid, cinnamic acid, crotonic acid, itaconic acid, maleic anhydride, and the like.

  The content ratio of the carboxyl group in the elastomer having such a carboxyl group is preferably 100 to 2000, more preferably 100 to 800 in terms of acid equivalent. When the acid equivalent is too small (when the number of carboxyl groups is relatively large), the compatibility with a pretreatment solution for electroless plating is reduced due to a decrease in compatibility with a solvent or other composition. Tend. In addition, when the acid equivalent is too large (when the number of carboxyl groups is relatively small), the peelability with respect to the alkaline aqueous solution tends to decrease.

  The molecular weight of the elastomer is preferably 10,000 to 1,000,000, more preferably 20,000 to 500,000, and more preferably 20,000 to 60,000. When the molecular weight of the elastomer is too large, the peelability tends to decrease. When the molecular weight is too small, the viscosity decreases and it becomes difficult to maintain a uniform thickness of the resin film. There is also a tendency that the resistance to the treatment liquid also decreases.

  In addition, as DFR, for example, an acrylic resin, an epoxy resin, a styrene resin, a phenol resin, a urethane resin, or the like containing a predetermined amount of a carboxyl group is used as a resin component, and a photopolymerization initiator is included. A sheet of curable resin composition may be used. Specific examples of such DFR include a dry film of a photopolymerizable resin composition as disclosed in JP-A-2000-231190, JP-A-2001-201851, and JP-A-11-212262. Sheets obtained by curing, and commercially available as an alkali development type DFR, for example, UFG series manufactured by Asahi Kasei Kogyo Co., Ltd. may be mentioned.

  Furthermore, as other examples of the resin film, a resin containing a carboxyl group and containing rosin as a main component (for example, “NAZDAR229” manufactured by Yoshikawa Chemical Co., Ltd.) or a resin containing phenol as a main component (for example, LEKTRACHEM) Manufactured "104F").

  The resin film 24 may be formed by applying a resin suspension or emulsion on the surface of the second insulating layer 23 using a conventionally known application method such as a spin coat method or a bar coater method, and then drying. After the DFR formed in (1) is bonded to the surface of the second insulating layer 23 using a vacuum laminator or the like, it can be easily formed by curing the entire surface.

  For example, the thickness of the resin film 24 is preferably 10 μm or less, and more preferably 5 μm or less. Moreover, 0.1 micrometer or more is preferable and 1 micrometer or more is further more preferable. When the thickness is too thick, the accuracy tends to decrease when the fine circuit pattern 25 is formed by laser processing, machining, or the like. Moreover, when the thickness is too thin, it tends to be difficult to form the resin film 24 having a uniform thickness.

  In addition, as the resin film 24, for example, a resin film mainly composed of a resin (carboxyl group-containing acrylic resin) made of an acrylic resin having a carboxyl group with an acid equivalent of about 100 to 800 can also be used. .

  Further, in addition to the above, the following is also suitable as the resin film 23. That is, as a characteristic required for the resist material constituting the resin film, for example, (1) an insulating base material (circuit board, insulating layer, etc.) on which the resin film is formed is immersed in a catalyst deposition process described later. High resistance to liquid (plating nucleation chemical), (2) Easily remove resin film (resist) by the film removal process described later, for example, the process of immersing the insulating substrate on which the resin film is formed in alkali (3) High film formability, (4) Easy dry film (DFR) formation, (5) High storage stability, and the like. As the plating nucleation chemical solution, as will be described later, for example, in the case of an acidic Pd—Sn colloid catalyst system, all are acidic (for example, pH 1 to 3) aqueous solutions. Moreover, in the case of an alkaline Pd ion catalyst system, the catalyst imparting activator is a weak alkali (pH 8 to 12), and the others are acidic. From the above, it is necessary to withstand pH 1 to 11, and preferably pH 1 to 12, as the resistance to the plating nucleating solution. In addition, being able to withstand is that when a sample on which a resist is formed is immersed in a chemical solution, swelling and dissolution of the resist are sufficiently suppressed, and the resist plays a role as a resist. The immersion temperature is generally room temperature to 60 ° C., the immersion time is 1 to 10 minutes, and the resist film thickness is generally about 1 to 10 μm, but is not limited thereto. As described later, the alkali stripping chemical used in the film removal step is generally an aqueous NaOH solution or an aqueous sodium carbonate solution. Its pH is 11 to 14, and it is desirable that the resist film can be easily removed preferably at pH 12 to 14. The NaOH aqueous solution concentration is generally about 1 to 10%, the processing temperature is room temperature to 50 ° C., the processing time is 1 to 10 minutes, and the immersion or spray treatment is generally performed, but is not limited thereto. Since a resist is formed on an insulating material, film formability is also important. A uniform film formation without repelling or the like is necessary. Moreover, although it is made into a dry film for the simplification of a manufacturing process, reduction of material loss, etc., the flexibility of a film is required in order to ensure handling property. Also, a dry film resist is pasted on the insulating material with a laminator (roll, vacuum). The pasting temperature is room temperature to 160 ° C., and the pressure and time are arbitrary. Thus, adhesiveness is required at the time of pasting. For this reason, the resist formed into a dry film is generally used as a three-layer structure sandwiched by a carrier film and a cover film to prevent dust from adhering, but is not limited thereto. The best preservation is that it can be stored at room temperature, but it must also be refrigerated or frozen. As described above, it is necessary to prevent the composition of the dry film from being separated at low temperatures or to be cracked due to a decrease in flexibility.

  From the above viewpoint, as the resin film 24, (a) at least one monomer of carboxylic acid or acid anhydride having at least one polymerizable unsaturated group in the molecule, and (b) ( It may be a polymer resin obtained by polymerizing a) at least one monomer that can be polymerized with a monomer, or a resin composition containing this polymer resin. Known techniques include JP-A-7-281437, JP-A-2000-231190, JP-A-2001-201851, and the like. (A) As an example of the monomer, (meth) acrylic acid, fumaric acid, cinnamic acid, crotonic acid, itaconic acid, maleic anhydride, maleic acid half ester, butyl acrylate, etc. may be mentioned alone or Two or more types may be combined. Examples of the monomer (b) are generally non-acidic and have (1) a polymerizable unsaturated group in the molecule, but are not limited thereto. It is selected so as to maintain various properties such as resistance in the plating process and flexibility of the cured film. Specifically, methyl (meth) acrylate, ethyl (meth) acrylate, iso-propyl (meth) acrylate, n-butyl (meth) acrylate, sec-butyl (meth) acrylate, tert-butyl (meth) acrylate, 2 -There are hydroxylethyl (meth) acrylates and 2-hydroxylpropyl (meth) acrylates. Further, there are esters of vinyl alcohol such as vinyl acetate, (meth) acrylonitrile, styrene or polymerizable styrene derivatives. It can also be obtained by polymerization of only a carboxylic acid or acid anhydride having one polymerizable unsaturated group in the molecule. Furthermore, a monomer having a plurality of unsaturated groups can be selected as the monomer used for the polymer so that three-dimensional crosslinking can be performed. In addition, reactive functional groups such as epoxy groups, hydroxyl groups, amino groups, amide groups, and vinyl groups can be introduced into the molecular skeleton.

  When a carboxyl group is contained in the resin, the amount of the carboxyl group contained in the resin is preferably 100 to 2000, preferably 100 to 800, and more preferably 100 to 600 in terms of acid equivalent. If the acid equivalent is too low, the compatibility with the solvent or other composition is lowered and the resistance to the plating pretreatment solution is lowered. If the acid equivalent is too high, the peelability is lowered. Further, the composition ratio of the monomer (a) is preferably 5 to 70% by mass.

  The resin composition may contain the polymer resin as an essential component as a main resin (binder resin), and may contain at least one of oligomers, monomers, fillers, and other additives. The main resin is preferably a linear polymer having thermoplastic properties. In order to control fluidity and crystallinity, it may be branched by grafting. The molecular weight is about 1,000 to 500,000 in terms of weight average molecular weight, and preferably 5,000 to 50,000. When the weight average molecular weight is small, the flexibility of the film and the resistance to the plating nucleation solution (acid resistance) are lowered. On the other hand, when the molecular weight is large, the alkali peelability and the sticking property when a dry film is formed deteriorate. Furthermore, a crosslinking point may be introduced to improve resistance to plating nucleus chemicals, suppress thermal deformation during laser processing, and control flow.

  Any monomer or oligomer may be used as long as it is resistant to plating nucleation chemicals and can be easily removed with alkali. Further, in order to improve the sticking property of the dry film (DFR), it can be considered that it is used as a tackifier as a plasticizer. Further, it is conceivable to add a crosslinking agent in order to increase various resistances. Specifically, methyl (meth) acrylate, ethyl (meth) acrylate, iso-propyl (meth) acrylate, n-butyl (meth) acrylate, sec-butyl (meth) acrylate, tert-butyl (meth) acrylate, 2 -There are hydroxylethyl (meth) acrylates and 2-hydroxylpropyl (meth) acrylates. Further, there are esters of vinyl alcohol such as vinyl acetate, (meth) acrylonitrile, styrene or polymerizable styrene derivatives. It can also be obtained by polymerization of only a carboxylic acid or acid anhydride having one polymerizable unsaturated group in the molecule. Furthermore, a polyfunctional unsaturated compound may be included. Any of the above monomers or oligomers obtained by reacting the monomers may be used. In addition to the above monomers, it is possible to include two or more other photopolymerizable monomers. Examples of monomers include 1,6-hexanediol di (meth) acrylate, 1,4-cyclohexanediol di (meth) acrylate, polypropylene glycol di (meth) acrylate, polyethylene glycol di (meth) acrylate, polyoxyethylene Polyoxyalkylene glycol di (meth) acrylate such as polyoxypropylene glycol di (meth) acrylate, 2-di (p-hydroxyphenyl) propane di (meth) acrylate, glycerol tri (meth) acrylate, dipentaerythritol penta (meth) Acrylate, trimethylolpropane triglycidyl ether tri (meth) acrylate, bisphenol A diglycidyl ether tri (meth) acrylate, 2,2-bis (4-methacryloxy) Pointer ethoxyphenyl) propane, there is a polyfunctional (meth) acrylate containing urethane groups. Any of the above monomers or oligomers obtained by reacting the monomers may be used.

  The filler is not particularly limited, but silica, aluminum hydroxide, magnesium hydroxide, calcium carbonate, clay, kaolin, titanium oxide, barium sulfate, alumina, zinc oxide, talc, mica, glass, potassium titanate, wollastonite, sulfuric acid Magnesium, aluminum borate, an organic filler, etc. are mentioned. Moreover, since the preferable thickness of a resist is as thin as 0.1-10 micrometers, the thing with a small filler size is preferable. Although it is preferable to use a material having a small average particle size and cut coarse particles, the coarse particles can be crushed during dispersion or removed by filtration.

  Examples of other additives include a photopolymerizable resin (photopolymerization initiator), a polymerization inhibitor, a colorant (dye, pigment, coloring pigment), a thermal polymerization initiator, and a crosslinking agent such as epoxy and urethane.

  In the circuit pattern forming process to be described next, the resin film 23 is subjected to laser processing or the like. Therefore, it is necessary to impart a laser ablation property to the resist material. As the laser processing machine, for example, a carbon dioxide laser, an excimer laser, a UV-YAG laser, or the like is selected. These laser processing machines have various intrinsic wavelengths, and productivity can be improved by using a material having a high UV absorption rate for these wavelengths. Among them, the UV-YAG laser is suitable for microfabrication, and the laser wavelength is 3rd harmonic 355 nm and 4th harmonic 266 nm. Therefore, as a resist material (material of the resin film 24), these wavelengths are used. Therefore, it is desirable that the UV absorption rate is relatively high. The higher the UV absorption rate, the finer the processing of the resist 24 is, and the productivity can be improved. However, the present invention is not limited to this, and it may be better to select a resist material having a relatively low UV absorption rate. The lower the UV absorption rate, the more UV light passes through the resist 24. Therefore, the UV energy can be concentrated on the processing of the second insulating layer 23 and the first insulating layer 20 thereunder, and the insulating layers 20, 23 are processed. Particularly favorable results can be obtained when the material is difficult to form. Thus, it is preferable to design the resist material according to the ease of laser processing of the resist 24, the ease of laser processing of the insulating layers 20 and 23, and their relationship.

<Circuit pattern formation process>
Next, as shown in FIG. 2F, a total value (hereinafter referred to as “total thickness”) of at least the thickness of the resin film 24 and the thickness of the second insulating layer 23 from the upper surface (outer surface) of the resin film 24 may be described. ) The circuit pattern 25 is formed by forming grooves and / or holes having the above predetermined depth and predetermined shape (circuit pattern forming step). The circuit pattern 25 is formed by laser processing, cutting processing, embossing processing, or the like. The groove of the circuit pattern 25 is mainly a groove for the wiring 27a (see FIG. 1), and the hole of the circuit pattern 25 is, for example, a hole for the electrode pad portion 27b (see FIG. 1). Further, depending on the situation, the circuit pattern 25 may include an interlayer connection hole (an interlayer connection hole different from the hole 21 in which the metal column 22 has already been formed in the metal column forming step). In this case, when the circuit pattern 25 is formed by the total thickness, the first insulating layer 20 is not dug and the circuit pattern 25 is formed on the outer surface (upper surface) of the first insulating layer 20 as shown in FIG. 2F. Will be put on. On the other hand, when the circuit pattern 25 is formed exceeding the total thickness, as shown in FIG. 3F of the second embodiment and FIG. 4F of the third embodiment, the first insulating layer 20 is dug, The circuit pattern 25 is embedded in the outer surface (upper surface) of the first insulating layer 20.

  The width of the groove for the wiring 27a in the circuit pattern 25 is not particularly limited. When laser processing is used, a fine groove having a line width of 20 μm or less can be easily formed.

  The method for forming the circuit pattern 25 is not particularly limited. Specifically, cutting by laser processing, dicing processing, etc., embossing, etc. are used. In order to form the highly accurate fine circuit pattern 25, laser processing is preferable. According to laser processing, the digging depth and the like of the first insulating layer 20 can be easily adjusted by controlling the output (energy or power) of the laser. As the embossing, for example, embossing with a fine resin mold used in the field of nanoimprinting can be preferably used.

  By forming the predetermined circuit pattern 25 in this way, a portion where the electroless plating film is provided later and the second electric circuit 27 is formed is defined.

  In FIG. 3F showing the second embodiment, the top of the metal pillar 22 formed in the previous metal pillar forming process is exposed and protrudes from the bottom surface of the circuit pattern 25 in this circuit pattern forming process. The case where the circuit pattern 25 is formed is shown. As will be described later, when the first insulating layer 20 is dug by laser processing, the resin or the like constituting the first insulating layer 20 can be easily removed, but the plating metal constituting the metal pillar 22 is Caused by being difficult to remove.

<Catalyst deposition process>
Next, as shown in FIG. 2G, a plating catalyst 26 is deposited on the surface of the resin film 24 and the surface of the circuit pattern 25 (catalyst deposition step). That is, the plating catalyst 26 is deposited on the entire surface of the resin film 24 and the insulating layer 30 on which the circuit pattern 25 is formed and on the entire surface of the resin film 24 and the insulating layer 30 on which the circuit pattern 25 is not formed. In addition, from the viewpoint of electroless plating described later, it is not necessary to apply the plating catalyst 26 to the surface of the metal column 22, but the plating catalyst 26 is applied to the entire resin film 24 and the insulating layer 30. The work is facilitated. Here, the plating catalyst 26 is a concept including its precursor.

  The plating catalyst 26 is a catalyst that is applied in advance in order to form the plating film only in a portion where it is desired to form the electroless plating film in a plating process described later. The plating catalyst 26 can be used without particular limitation as long as it is known as a catalyst for electroless plating. Alternatively, the precursor of the plating catalyst 26 may be deposited in advance, and the plating catalyst 26 may be generated after the resin film 24 is removed. Specific examples of the plating catalyst 26 include, for example, metal palladium (Pd), platinum (Pt), silver (Ag), and the like, and precursors that generate these.

  Examples of the method of depositing the plating catalyst 26 include a method of treating with an acidic Pd—Sn colloid solution treated under acidic conditions of pH 1 to 3 and then treating with an acid solution. More specifically, the following methods can be mentioned.

First, the resin film 24 on which the circuit pattern 25 is formed and the oil adhering to the surface of the insulating layer 30 are washed with hot water in a surfactant solution (cleaner / conditioner) for a predetermined time. Next, if necessary, a soft etching treatment is performed with a sodium persulfate-sulfuric acid based soft etching agent. And it pickles further in acidic solutions, such as sulfuric acid aqueous solution of pH 1-2, and aqueous hydrochloric acid. Next, a pre-dip treatment is performed in which chloride ions are adsorbed on the surfaces of the resin film 24 and the insulating layer 30 by immersing in a pre-dip solution mainly containing a stannous chloride aqueous solution having a concentration of about 0.1%. Thereafter, Pd and Sn are aggregated and adsorbed by further dipping in an acidic catalytic metal colloid solution such as acidic Pd—Sn colloid having pH 1 to 3 containing stannous chloride and palladium chloride. Then, an oxidation-reduction reaction (SnCl ₂ + PdCl ₂ → SnCl ₄ + Pd ↓) is caused between the adsorbed stannous chloride and palladium chloride. As a result, metallic palladium as the plating catalyst 26 is deposited.

  In addition, as an acidic catalyst metal colloid solution, a well-known acidic Pd-Sn colloid catalyst solution etc. can be used, and the commercially available plating process using an acidic catalyst metal colloid solution may be used. Such a process is systematized and sold by, for example, Rohm & Haas Electronic Materials.

  By such a catalyst deposition process, the plating catalyst 26 can be deposited on the surface of the resin film 24 and the surface of the circuit pattern 25 as shown in FIG. 2G.

<Film removal process>
Next, as shown in FIG. 2H, the resin film 24 is removed from the insulating layer 30 (more specifically, the second insulating layer 23) (film removal step). That is, when the resin film 24 is made of a soluble resin, the resin film 24 is dissolved using an organic solvent or an alkaline solution and removed from the surface of the insulating layer 30. When the resin film 24 is made of a swellable resin, the resin film 24 is swollen using a predetermined liquid, and is peeled off from the surface of the insulating layer 30 and removed.

  According to this film removal step, the plating catalyst 26 can be left only on the surface of the insulating layer 30 where the circuit pattern 25 is formed. On the other hand, the plating catalyst 26 deposited on the surface of the resin film 24 is removed from the insulating layer 30 together with the resin film 24. Here, from the viewpoint of preventing the plating catalyst 26 removed from the insulating layer 30 from scattering and re-depositing on the surface of the insulating layer 30, the resin film 24 collapses apart when removed from the insulating layer 30. It is preferable that the whole can be removed without being continuous.

  As the liquid for dissolving or swelling the resin film 24, the resin film 24 is easily dissolved or removed from the insulating layer 30 without substantially decomposing or dissolving the circuit board 10, the insulating layer 30, and the plating catalyst 26. Any liquid that can be dissolved or swollen to the extent possible can be used without particular limitation. Such a resin film removing liquid can be appropriately selected depending on the type and thickness of the resin film 24. Specifically, for example, when a photocurable epoxy resin is used as the resist resin, an organic solvent, a resist remover in an alkaline aqueous solution, or the like is used. For example, when the resin film 24 is formed of an elastomer such as a diene elastomer, an acrylic elastomer, and a polyester elastomer, or as the resin film 24, (a) a polymerizable unsaturated group is included in the molecule. It is obtained by polymerizing at least one monomer of carboxylic acid or acid anhydride having at least one and at least one monomer that can be polymerized with (b) (a) monomer. In the case of a polymer resin to be produced, or a resin composition containing this polymer resin, or formed from the aforementioned carboxyl group-containing acrylic resin, for example, hydroxylation at a concentration of about 1 to 10% An aqueous alkali solution such as an aqueous sodium solution can be preferably used.

  In the case of using a plating process that is performed under acidic conditions as described above in the catalyst deposition step, the resin film 24 has a swelling degree of 60% or less, preferably 40% or less under acidic conditions. It is formed of an elastomer such as a diene elastomer, an acrylic elastomer, and a polyester elastomer that has a degree of swelling of 50% or more under alkaline conditions, or (a) polymerizable in the molecule. Polymerizing at least one monomer of carboxylic acid or acid anhydride having at least one unsaturated group and at least one monomer capable of polymerizing with (b) (a) monomer Or a resin composition containing this polymer resin, or the aforementioned carboxyl group-containing active polymer. It is preferably formed from Le resin. Such a resin film is easily dissolved or swelled by being immersed in an alkaline aqueous solution having a pH of 11 to 14, preferably a pH of 12 to 14, such as a sodium hydroxide aqueous solution having a concentration of about 1 to 10%. Then, it is removed by dissolution or peeling. In addition, in order to improve solubility or peelability, you may irradiate with an ultrasonic wave during immersion. Moreover, you may remove by peeling with a light force as needed.

  Examples of the method of removing the resin film 24 include a method of immersing the insulating layer 30 covered with the resin film 24 in a resin film removal liquid for a predetermined time. Moreover, in order to improve peeling removal property or melt | dissolution removal property, it is especially preferable to irradiate with an ultrasonic wave during immersion. In addition, when it is difficult to remove or remove, for example, it may be peeled off with a light force as necessary.

<Plating process>
Next, as shown in FIG. 2I, electroless plating is performed on the insulating layer 30 to form an electroless plating film on the portion of the circuit pattern 25 where the plating catalyst 26 remains and on the exposed portion of the metal pillar 22. A second electric circuit 27 is formed on the insulating layer 30 (that is, the first insulating layer 20 and the second insulating layer 23). At the same time, the second circuit 27 of the insulating layer 30 and the first circuit 11 of the circuit board 10 are interlayer-connected via the metal pillar 22 (plating process). By such electroless plating treatment, the electroless plating film is deposited with high precision only on the portion where the circuit pattern 25 is formed.

  As an electroless plating method, the insulating layer 30 partially coated with the plating catalyst 26 is immersed in an electroless plating solution, and an electroless plated film is deposited only on the portion where the plating catalyst 26 is deposited. Such a method can be used.

  Examples of the metal used for electroless plating include copper (Cu), nickel (Ni), cobalt (Co), and aluminum (Al). Of these, plating mainly composed of Cu is preferable because of its excellent conductivity. Moreover, when Ni is included, it is preferable from the point which is excellent in corrosion resistance and adhesiveness with a solder.

  The film thickness of the electroless plating film is not particularly limited. Specifically, for example, it is preferably about 0.1 to 10 μm, more preferably about 1 to 5 μm.

  Through the plating process, an electroless plating film is deposited only on the portion of the surface of the insulating layer 30 where the plating catalyst 26 remains. Therefore, the conductor layer can be formed with high precision only in the portion where the second circuit 27 is to be formed. On the other hand, the deposition of the electroless plating film on the portion where the circuit pattern 25 is not formed can be suppressed. Therefore, even when a plurality of fine wirings 27a having a narrow line width and a narrow pitch are formed, an unnecessary plating film does not remain between the adjacent wirings 27a. Therefore, the occurrence of a short circuit and the occurrence of migration can be suppressed.

  By such a plating process, the electroless plating film can be deposited only on the laser processed portion of the surface of the insulating layer 30. As a result, a second circuit 27 is newly formed on the surface of the insulating layer 30, and the second circuit 27 of the insulating layer 30 and the first circuit 11 of the circuit board 10 are connected to the interlayer connection hole 21 or the metal pillar. Interlayer connection is made via 22.

  Through such a process or by repeating, the multilayer circuit board 1 having the second circuit 27 on the surface of the insulating layer 30 as shown in FIG. 1 is manufactured. In the multilayer circuit board 1, the electrical circuits 11 and 27 and the interlayer connection holes 21 are connected to each other in each layer, and the electrical circuits 11 and 27 in each layer are connected to each other through the interlayer connection holes 21. Interlayer connection.

  By using the manufacturing method described in this embodiment, the film thickness and depth of the second circuit 27 can be freely adjusted by adjusting the depth of the circuit pattern 25 with respect to the insulating layer 30. For example, the second circuit 27 can be formed in a deep portion of the insulating layer 30, or the plurality of second circuits 27 can be formed at positions having different depths. Further, by forming the second circuit 27 in a deep portion of the insulating layer 30, the thick circuit 27 can be formed. A thick film circuit has a high cross-sectional area, and thus has high strength and electric capacity.

  In the manufacturing method of the present embodiment, only the interlayer connection holes 21 are filled with the plating metal in advance by the first insulating layer forming step, the hole forming step, and the metal pillar forming step before the circuit pattern 25 is formed. Without worrying about excessive conductor formation in the second circuit 27, the metal filling of the interlayer connection hole 21 can be sufficiently performed over time. In addition, since the circuit pattern 25 is not yet formed when the interlayer connection hole 21 is filled with metal, the plating film does not grow from the circuit pattern side, and good metal filling with suppressed generation of voids is achieved. Realize. Then, after the metal filling of the interlayer connection hole 21 is completed, the second insulating layer forming process, the film forming process, the circuit pattern forming process, the catalyst deposition process, the film removing process, and the plating process are performed by the additive method. Since the conductor of the circuit 27 is formed, a fine conductor can be formed with high accuracy in a short time, and excessive formation of the conductor in the second circuit 27 is avoided. As described above, even if the fine circuit pattern 25 and the interlayer connection hole 21 are mixed, the multilayer circuit board 1 can be manufactured without any trouble by the build-up method while applying the additive method satisfactorily.

  In the manufacturing method of the present embodiment, the second insulating layer 23 is formed on the outer surface of the first insulating layer 20, the resin film 24 is formed on the outer surface of the second insulating layer 23, and at least the thickness of the resin film 24 is Since the resin film 24 is removed after the circuit pattern 25 having a depth equal to or greater than the total value of the thickness of the second insulating layer 23 is formed, the portion of the circuit pattern 25 is always removed by processing the second insulating layer 23. Will be. Accordingly, the bottom surface of the circuit pattern 25 is located at a position dug down from the outer surface of the second insulating layer 23, and the conductor layer constituting the second circuit 27 is partially or entirely embedded in the outer surface of the second insulating layer 23. It will be in a state to be. As a result, the thickness of the conductor layer can be increased, and the mechanical strength of the second circuit 27 can be ensured. Further, the protruding amount of the conductor layer from the second insulating layer 23 can be eliminated or reduced, the second circuit 27 can be protected, the second circuit 27 can be prevented from falling off the insulating layer 30, and the circuit can be formed. It is possible to eliminate or reduce the unevenness generated on the surface.

  In the manufacturing method of this embodiment, the interlayer connection hole 21 can be filled with a plating metal by growing a plating film from the exposed first electric circuit 11 by electroless plating in the metal column forming step. it can. Since the electric circuit 11 which is a conductor is used for a plating nucleus of electroless plating, the metal pillar 22 can be rationally formed.

  In the manufacturing method of the present embodiment, the plating catalyst 25 is formed on the surface of the first insulating layer 20, the inner wall surface of the interlayer connection hole 21, and the exposed surface of the first electric circuit 11 in the metal column forming step. After the electroless plating is applied to the plating catalyst coating portion, the electroplating is performed to fill the interlayer connection hole 21 with the plating metal, and then the first insulating layer 20 including the surface of the first insulating layer 20 is deposited. The plating metal deposited on the outer surface side of the insulating layer 20 may be removed. Since the electroless plating layer formed on the outer surface side of the first insulating layer 20 including the surface of the first insulating layer 20 is used as a power feeding layer necessary for electrolytic plating, the metal pillars 22 can be rationally formed.

  In the manufacturing method of the present embodiment, the resin film 24 is a resin film that can be dissolved or removed from the second insulating layer 23 (or the insulating layer 30) by dissolving or swelling with a predetermined liquid. preferable. By using such a resin film 24, the resin film 24 can be easily and satisfactorily removed or removed from the surface of the second insulating layer 23. If the resin film 24 is collapsed when the resin film 24 is removed, the plating catalyst 26 deposited on the resin film 24 scatters, and the scattered plating catalyst 26 is re-deposited on the insulating layer 30 and is unnecessary in that portion. There is a problem that a thick plating film is formed. Since the resin film 24 can be easily and satisfactorily removed from the surface of the insulating layer 30, such a problem can be prevented.

  In the multilayer circuit board 1 manufactured by the manufacturing method of the present embodiment, even when the fine circuit pattern 25 and the interlayer connection hole 21 are mixed, the metal filling of the interlayer connection hole 21 is sufficiently and satisfactorily performed. Thus, the connection between the circuits 11 and 27 and the interlayer connection hole 21 is good, and excessive conductor formation in the circuit 27 portion is avoided, so that the multilayer circuit board 1 in which a short circuit or the like hardly occurs is obtained. Therefore, the multilayer circuit board 1 can be manufactured without any problem by the build-up method while applying the additive method satisfactorily. As a result, the multilayer circuit board 1 on which the electric circuit 27 with high shape accuracy is formed is provided. By using such a method of manufacturing the multilayer circuit board 1, the multilayer circuit board 1 used for applications such as an IC substrate, a printed wiring board for a mobile phone, a three-dimensional circuit board, etc., in which the width of the wiring 27a and the distance between the wirings 27a are narrow. Can be manufactured.

  In the method of manufacturing the multilayer circuit board, the fluorescent material is obtained by irradiating the surface to be inspected with ultraviolet light or near ultraviolet light after the above-described film removing step by containing the fluorescent material in the resin film 24. The film removal failure can be inspected using the luminescence from In the method for manufacturing a multilayer circuit board according to the present embodiment, the metal wiring 27a having an extremely small line width of the wiring 27a and an interval between the wirings 27a can be formed. In such a case, for example, there is a concern that the resin film 24 between the adjacent metal wirings 27a may remain without being completely removed. When the resin film 24 remains between the metal wirings 27a, a plating film is formed in that portion, which may cause migration or a short circuit. In such a case, the resin film 24 is made to contain a fluorescent substance, and after the film removal step, the film removal surface is irradiated with a predetermined light emission source so that only the portion where the film 24 remains is caused to emit light. Thus, it is possible to inspect the presence or absence of film removal failure and the location of film removal failure.

  The fluorescent substance that can be contained in the resin film 24 used in this inspection process is not particularly limited as long as it exhibits light emission characteristics when irradiated with light from a predetermined light source. Specific examples thereof include Fluoresceine, Eosine, Pyroline G, and the like.

  The portion where the light emission from the fluorescent substance is detected by this inspection process is the portion where the resin film 24 remains. Therefore, by removing the portion where light emission is detected, it is possible to suppress the formation of a plating film on that portion. Thereby, generation | occurrence | production of a migration or a short circuit can be suppressed beforehand.

[Second Embodiment]
A second embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol is used for the component which is the same as that of 1st Embodiment, or it corresponds, The description is abbreviate | omitted, and only the characteristic part of 2nd Embodiment is added.

  In the second embodiment, as shown in FIG. 3F, in the circuit pattern forming step, the circuit pattern 25 exceeds the total value of the thickness of the resin film 24 and the thickness of the second insulating layer 23 from the outer surface of the resin film 24. Is forming. Thereby, in the part of the circuit pattern 25, after the resin film 24 and the second insulating layer 23 are removed, the first insulating layer 20 is dug so that the bottom surface of the circuit pattern 25 is the first insulating layer 20. Located inward from the outer surface. In the second embodiment, as shown in FIG. 3F, in the circuit pattern forming process, the top of the metal pillar 22 formed in the metal pillar forming process of FIG. 3D protrudes from the bottom surface of the circuit pattern 25. A circuit pattern 25 is formed. This is because when the first insulating layer 20 is dug by laser processing, the resin or the like constituting the first insulating layer 20 is easily removed, but the plating metal constituting the metal pillar 22 is difficult to remove. To happen.

  In the manufacturing method of the present embodiment, in the circuit pattern forming step, the circuit pattern 25 is formed so that the top of the metal pillar 22 protrudes from the bottom surface of the circuit pattern 25, and the top of the metal pillar 22 is covered. Further, it is preferable that the portion of the second electric circuit 27 (see FIG. 3I) is an electrode pad portion 27b (see FIG. 1). The top portion of the metal pillar 22 bites into the conductor layer of the pad portion 27b, and the drop off of the pad portion 27b from the insulating layer 30 is effectively suppressed by the anchor effect, and the pad portion 27b that can sufficiently withstand the weight of the mounted component is obtained. Because.

[Third Embodiment]
A third embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol is used for the component which is the same as that of 1st Embodiment, or is equivalent, The description is abbreviate | omitted, and only the characteristic part of 3rd Embodiment is added.

  In the third embodiment, as shown in FIG. 4D, the metal column 22 does not grow to the height of the outer surface of the first insulating layer 20 in the metal column forming step. Instead, the metal pillar 22 is configured by growing a plating film up to a position (see FIG. 4F) that becomes the bottom surface of the circuit pattern 25. That is, the metal pillar 22 is not grown to the outer surface of the first insulating layer 20, but is stopped at a height before that. Thereby, it can be easily achieved that the top of the metal pillar 22 does not protrude from the bottom surface of the circuit pattern 25 at the stage of the metal pillar forming process prior to the circuit pattern forming process. Then, as shown in FIG. 4F, in the circuit pattern forming step, the circuit pattern 25 is formed so that the top of the metal pillar 22 does not protrude from the bottom surface of the circuit pattern 25. As a result, as shown in FIG. 4I, it is possible to avoid the conductor layer formed on the top of the metal pillar 22 from protruding from the outer surface of the second insulating layer 23 in the plating step, and the circuit 27 of the insulating layer 30. It is possible to eliminate or reduce unevenness generated on the formation surface. Therefore, even if the number of stacked layers increases, the unevenness generated on the circuit formation surface does not increase, and a fine circuit can be formed.

  Alternatively, as shown in FIG. 2D of the first embodiment, after the metal pillar 22 is grown to the height of the top surface of the first insulating layer 20 in the metal pillar forming step, the metal is made to the position that becomes the bottom surface of the circuit pattern 25. By removing the tops of the pillars 22 by, for example, soft etching or the like, the circuit pattern 25 is formed so that the tops of the metal pillars 22 do not protrude from the bottom surface of the circuit pattern 25 in the circuit pattern forming step, as shown in FIG. It is also possible. Thereby, it is possible to reliably achieve the correction of the position of the top of the metal column 22 so that the top of the metal column 22 does not protrude from the bottom surface of the circuit pattern 25.

  Hereinafter, the present invention will be described more specifically through examples. The scope of the present invention is not construed as being limited in any way by the following examples.

  (A) Circuit board preparation step: Prepare a circuit board (thickness: 500 μm) on which a predetermined electric circuit is formed by etching away the copper foil of a cured copper clad laminate (“R1515T” manufactured by Panasonic Electric Works Co., Ltd.) did.

  (B) 1st insulating layer formation process: The 1st insulating layer which consists of an epoxy resin sheet was laminated | stacked on the circuit formation surface of this circuit board. That is, bisphenol A type epoxy resin (“850S” manufactured by DIC Corporation), dicyandiamide (“DICY” manufactured by Nippon Carbide Industries Co., Ltd.) as a curing agent, and 2-ethyl-4-methyl as a curing accelerator. Imidazole (“2E4MZ” manufactured by Shikoku Kasei Kogyo Co., Ltd.), fused silica as inorganic filler (“FB1SDX” manufactured by Denki Kagaku Kogyo Co., Ltd.), and silane coupling agent (Momentive Performance Materials Japan GK) A sheet (thickness: 60 μm) made of a resin composition containing “A-187” manufactured by the manufacturer) and methyl ethyl ketone (MEK) and N, N-dimethylformamide (DMF) as a solvent is formed on the circuit forming surface of the circuit board. The PET sheet is placed on the outer surface of the sheet made of this resin composition. Rum (“TN100” manufactured by Toyobo Co., Ltd.) was placed, and this laminate was press-heated and bonded at 0.4 Pa and 100 ° C. for 1 minute, and then further bonded at 175 ° C. for 90 minutes. After the heat curing, the sheet was cured. Then, the laminated body which laminated | stacked the 1st insulating layer on the circuit board was obtained by peeling PET film.

  (C) Hole forming step: By performing laser processing on the first insulating layer from the outer surface, a hole having a diameter of 50 μm was formed on the first circuit, and the first circuit was exposed. Laser processing was performed using a laser beam irradiation apparatus (“MODEL5330” manufactured by ESI) equipped with a UV-YAG laser.

  (D) Metal column forming step: After forming the holes, the substrate was immersed in a sulfuric acid-based etching solution at 35 ° C. for 5 minutes, and the surface of the first circuit exposed by forming the holes in the substrate was subjected to acidic cleaner treatment. . Further, after washing with water, in order to form metal pillars at the hole forming portions of the substrate, the substrate was placed in an electroless copper plating solution (“SP-2” manufactured by Uemura Kogyo Co., Ltd.) at 70 ° C. for 7 to 8 hours. Was immersed and the plating was deposited and grown from the first electric circuit portion at the bottom of the hole to form a metal column.

  (E) Second insulating layer forming step and film forming step: Next, in the same manner as in the first insulating layer forming step, a second insulating layer (thickness: 10 μm) similar to the first insulating layer is replaced with the first insulating layer. It was formed by laminating on the outer surface of the insulating layer and the top of the metal pillar. Next, a spin coat method is used on the outer surface of the second insulating layer to form a styrene-butadiene copolymer (SBR) methyl ethyl ketone (MEK) suspension (manufactured by Nippon Zeon Co., Ltd., particle size 200 nm, solid content 15%). ) And dried at 80 ° C. for 30 minutes to form a 2 μm thick resin film.

  (F) Circuit pattern forming step: Next, a fine groove having a width of 20 μm and a depth of 15 μm was formed as a circuit pattern in a predetermined position by laser processing on the laminate on which the resin film was formed. For laser processing, MODEL 5330 manufactured by ESI equipped with a UV-YAG laser was used.

  (G) Catalyst deposition step: Next, the laser-processed laminate was immersed in a cleaner conditioner (C / N 3320) and then washed with water. And in order to suppress decomposition | disassembly of the tin- palladium colloid adhering, the pre-dip process was performed using PD404 (made by Shipley Far East Co., Ltd.). Then, it was immersed in a catalyst liquid (CAT44, manufactured by Shipley Far East Co., Ltd.), and palladium serving as the core of electroless copper plating was adsorbed to the laminate in which a resin film was formed in a tin-palladium colloid state. .

  (H) Film removal step: Next, the SBR film on the surface is swollen by immersing the laminate on which the tin-palladium colloid has been adsorbed in a 5% aqueous sodium hydroxide solution while being ultrasonically treated for 10 minutes. Thus, the resin film was peeled and removed. Next, the laminated body surface was irradiated with ultraviolet light. At this time, fluorescence emission was partially recognized by irradiation with ultraviolet light. The part where the fluorescent part was recognized was removed by rubbing with a cloth.

  (I) Plating process: Next, palladium nuclei were generated by immersing the laminate in an accelerator chemical (ACC19E, manufactured by Shipley Far East Co., Ltd.). Then, the laminate was immersed in an electroless plating solution (CM328A, CM328L, CM328C, manufactured by Shipley Far East Co., Ltd.) to perform an electroless copper plating process. Thereby, an electroless copper plating film having a thickness of 3 μm was deposited. Further, electroless copper plating (fill-up plating) was performed until the circuit groove was filled.

  When the surface of the laminate subjected to the electroless plating treatment as described above was observed with an SEM (scanning microscope), the metal wiring formed of the electroless plating film was formed with high precision in the laser-processed groove portion. It was confirmed that

  In addition, the swelling degree of the resin film was measured as follows. That is, the thickness is the same as the thickness formed on the epoxy resin substrate by applying the SBR suspension applied to form a resin film on the insulating base material on the release paper and drying at 80 ° C. for 30 minutes. A film having a thickness of 2 μm was formed. And what peeled the formed membrane | film | coat forcibly was made into the sample. And about 0.02 g of the obtained sample was weighed. The sample weight at this time is defined as a weight m ′ before swelling. The weighed sample was immersed in 10 ml of 5% aqueous sodium hydroxide solution at 20 ± 2 ° C. for 15 minutes. Then, centrifugation was performed at 1000 G for about 10 minutes using a centrifuge to remove moisture and the like attached to the sample. Then, the weight of the swollen sample after centrifugation is measured, and the weight after swelling is defined as m. From the obtained weight m ′ before swelling and weight m after swelling, the degree of swelling was calculated from the formula “degree of swelling SW = (m−m ′) / m ′ × 100 (%)”. Other conditions were performed in accordance with JIS L1015 8.27 (measurement method of alkali swelling degree). At this time, the degree of swelling obtained was about 750%.

DESCRIPTION OF SYMBOLS 1 Multilayer circuit board 10 Circuit board 11 1st electric circuit 20 1st insulating layer 21 Hole for interlayer connection 22 Metal pillar 23 2nd insulating layer 24 Resin film 25 Circuit pattern 26 Plating catalyst 27 2nd electric circuit 27a Wiring 27b Electrode pad Part 30 Insulating layer (whole insulating layer)

Claims (9)

A method of manufacturing a multilayer circuit board having electrical circuits and interlayer connection holes connected to each other,
A first insulating layer forming step of forming a first insulating layer on a circuit forming surface of a circuit board on which the first electric circuit is formed;
Forming a hole from the outer surface in the first insulating layer and exposing the first electric circuit;
A metal column forming step of filling the hole with plating metal from the exposed first electric circuit to form a metal column;
A second insulating layer forming step of forming a second insulating layer on the outer surface of the first insulating layer and the top of the metal pillar;
A film forming step of forming a resin film on the outer surface of the second insulating layer;
A circuit pattern is formed by forming a groove and / or a hole having a predetermined depth and a predetermined shape at least equal to or greater than the total value of the thickness of the resin film and the thickness of the second insulating layer from the outer surface of the resin film. Circuit pattern forming step to be formed,
A catalyst deposition step of depositing a plating catalyst on the surface of the resin film and the surface of the circuit pattern;
A film removing step of removing the resin film from the second insulating layer; and
By performing electroless plating on the first insulating layer and the second insulating layer, a plating film is formed on the portion of the circuit pattern where the plating catalyst remains and on the exposed portion of the metal pillar, and the first insulating layer and the second insulating layer A plating step of forming a second electric circuit in the second insulating layer and inter-connecting the second electric circuit of the insulating layer and the first electric circuit of the circuit board via the metal pillar;
A method for manufacturing a multilayer circuit board.   In the circuit pattern forming step, the top of the metal column is exposed from the bottom surface of the circuit pattern and the circuit pattern is formed so as to protrude, and the portion of the second electric circuit formed so as to cover the top of the metal column is an electrode. The method of manufacturing a multilayer circuit board according to claim 1, wherein the pad part is used for a pad.   2. The method of manufacturing a multilayer circuit board according to claim 1, wherein in the circuit pattern forming step, the circuit pattern is formed so that the top of the metal pillar is exposed from the bottom surface of the circuit pattern and does not protrude.   The multilayer circuit according to claim 3, wherein the top of the metal pillar is exposed and does not protrude in the circuit pattern forming process by filling the plating metal up to a position which becomes a bottom surface of the circuit pattern in the metal pillar forming process. A method for manufacturing a substrate.   4. The top of the metal pillar is exposed and does not protrude in the circuit pattern forming process by removing the top of the metal pillar to a position that becomes a bottom surface of the circuit pattern after the metal pillar forming process. Manufacturing method for multilayer circuit board.   6. The multilayer circuit board according to claim 1, wherein in the metal column forming step, the hole is filled with a plating metal by growing a plating film from the exposed first electric circuit by electroless plating. Manufacturing method.   In the metal column forming step, after the plating catalyst is deposited on the surface of the first insulating layer, the inner wall surface of the hole, and the exposed surface of the first electric circuit, electroless plating is performed on the plating catalyst deposition portion. The electrolytic plating is performed to fill the holes with a plating metal, and thereafter, the plating metal deposited on the outer surface side of the first insulating layer including the surface of the first insulating layer is removed. 2. A method for producing a multilayer circuit board according to item 1.   The method of manufacturing a multilayer circuit board according to claim 1, wherein the resin film is a resin film that can be dissolved or removed from the insulating layer by dissolving or swelling with a predetermined liquid.   The multilayer circuit board manufactured by the manufacturing method of any one of Claims 1-8.

Images