JP5347631B2 - Microcomputer - Google Patents

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JP5347631B2
JP5347631B2 JP2009076061A JP2009076061A JP5347631B2 JP 5347631 B2 JP5347631 B2 JP 5347631B2 JP 2009076061 A JP2009076061 A JP 2009076061A JP 2009076061 A JP2009076061 A JP 2009076061A JP 5347631 B2 JP5347631 B2 JP 5347631B2
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speed
clock
speed clock
unit
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JP2010231330A (en
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洋一 藤田
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株式会社デンソー
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Description

  The present invention relates to a microcomputer.

  Conventionally, a single-chip microcomputer has been proposed in Patent Document 1, for example. Specifically, in Patent Document 1, a main system clock signal (high-speed clock) for high-speed operation and a sub-system for low-speed operation are used to reduce the power consumption of a microcomputer (hereinafter referred to as a microcomputer). A proposal has been made that uses two oscillation circuits for generating a clock signal (low-speed clock).

  As a result, the microcomputer performs a high-speed operation using a high-speed clock during normal operation, and performs a low-speed operation using a low-speed clock during low consumption.

Japanese Unexamined Patent Publication No. 7-6155

  However, in the above conventional technology, if the microcomputer switches from high speed operation to low speed operation when the low speed clock is not stable due to a failure of the circuit that supplies the low speed clock, the microcomputer cannot operate normally due to the unstable low speed clock. As a result, there is a problem that the operation of the microcomputer stops.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a configuration capable of preventing the operation of the microcomputer from stopping when the low-speed clock used for the operation of the microcomputer is not stable.

In order to achieve the above object, according to the first aspect of the present invention, the determination unit (42, 43) that determines whether there is an abnormality in the low-speed clock by inputting the low-speed clock, and the determination unit (42, 43) A low-speed clock confirmation unit (40) having an output unit (44) that outputs an abnormal signal indicating an abnormal state of the low-speed clock when a clock abnormality is detected, and an abnormal signal is input from the low-speed clock confirmation unit (40) Then, a high-speed clock is input, and the high-speed clock is divided to generate a medium-high speed clock that is slower than the high-speed clock and faster than the low-speed clock, and the control units (50, 70 that use the medium-high speed clock for normal operation) And) .

According to this, since it is possible to detect the abnormality of the low-speed clock and notify the abnormality, it is possible to prevent the transition from the normal operation to the low-speed operation. Therefore, it is possible to prevent the microcomputer from stopping when the low-speed clock is not stable. Even if a low-speed clock abnormality is detected and the low-speed clock cannot be used, the medium-high speed clock can be generated using the high-speed clock, so that the operation of each function of the microcomputer can be continued. .

In the invention described in claim 2, the control unit (50, 70) is, when inputting the abnormality signal from the low-speed clock confirmation unit (40), and wherein the Turkey to prohibit the transition to low-speed operation from a normal operation To do.

  According to this, since the control unit (50, 70) prohibits the transition from the normal operation to the low-speed operation, the low-speed operation using the abnormal low-speed clock is not performed. Therefore, it is possible to prevent the operation of the microcomputer from stopping.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

1 is an overall configuration diagram of a microcomputer according to a first embodiment of the present invention. It is a block diagram of a low-speed clock confirmation part. It is a timing chart showing an example of operation of a microcomputer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The microcomputer shown in this embodiment is used, for example, in an ECU or the like mounted on a vehicle and operates with a battery.

  Further, the microcomputer shown in the present embodiment realizes a predetermined function by any one of a normal operation using a high-speed clock and a low-speed operation using a low-speed clock slower than the high-speed clock.

  Normal operation refers to high-speed operation that operates with a high-speed clock. On the other hand, the low-speed operation includes a low-consumption operation that operates with a low-speed clock and an intermittent operation that repeats a high-speed operation and a stop. Switching between high-speed operation and stop in intermittent operation is performed by a timer using a low-speed clock. Therefore, the intermittent operation is also included in the low speed operation using the low speed clock.

  The predetermined function of the microcomputer is the contents of the program built in the microcomputer, the contents of the program stored in the external storage medium, CPU, ROM, RAM, timer, analog to digital conversion, serial communication, input / output, etc. Point to.

  FIG. 1 is an overall configuration diagram of a microcomputer according to the present embodiment. As shown in this figure, the microcomputer 10 (hereinafter referred to as the microcomputer 10) includes a low-speed oscillation unit 20, a high-speed oscillation unit 30, a low-speed clock confirmation unit 40, a clock control unit 50, a timer 60, an intermittent control unit 70, And a functional unit 80.

  When receiving a low-speed clock generation command from the clock control unit 50, the low-speed oscillation unit 20 oscillates the low-speed oscillator 21 provided outside the microcomputer 10 to generate a low-speed clock. The low-speed oscillator 21 generates a signal on the order of kHz, for example, and is configured by, for example, a piezoelectric element such as CERALOCK (registered trademark) or crystal, a CR circuit, or the like.

  1 shows the low-speed oscillator 21 provided outside the microcomputer 10, the low-speed oscillator 21 may be built in the microcomputer 10. In this case, a CR oscillation circuit or the like can be employed as a circuit for causing the low-speed oscillator 21 to oscillate.

  When receiving a high-speed clock generation command from the clock control unit 50, the high-speed oscillation unit 30 oscillates a high-speed oscillator 31 provided outside the microcomputer 10 to generate a high-speed clock. The high-speed oscillator 31 generates a signal on the order of MHz, for example, and is formed by the above piezoelectric element.

  The low-speed clock confirmation unit 40 receives a low-speed clock from the low-speed oscillation unit 20 and confirms whether the low-speed clock is stable.

  FIG. 2 is a block diagram of the low-speed clock confirmation unit 40. As shown in this figure, the low-speed clock confirmation unit 40 includes a confirmation clock oscillation unit 41, a time measurement unit 42, a comparison unit 43, and an output unit 44.

  The confirmation clock oscillator 41 generates a confirmation clock that is slightly faster than the low-speed clock input from the low-speed oscillator 20 to the low-speed clock confirmation unit 40.

  The time measuring unit 42 receives a low-speed clock and a confirmation clock, and counts the number of confirmation clocks in one cycle of the low-speed clock at a predetermined time using the confirmation clock. For this reason, the time measuring unit 42 synchronizes the low-speed clock and the confirmation clock, and counts the number of confirmation clocks corresponding to an arbitrary period of the low-speed clock, for example. Then, the measurement result of the time measurement unit 42 is output to the comparison unit 43.

  The time measuring unit 42 receives a low-speed clock and a confirmation clock, and counts the number of low-speed clocks in a predetermined time using the confirmation clock. For this reason, the time measuring unit 42 synchronizes the low-speed clock and the confirmation clock, and counts the number of low-speed clocks corresponding to an arbitrary period of the confirmation clock, for example. Then, the measurement result of the time measurement unit 42 is output to the comparison unit 43.

  The comparison unit 43 determines whether there is an abnormality in the low-speed clock by comparing the measurement result of the time measurement unit 42 with the expected value. The expected value is a predetermined numerical range preset in the comparison unit 43, and is a value that will be measured if the low-speed clock is stable. That is, since it is abnormal if the number of low-speed clocks is too large or too small, it is determined that the low-speed clock is abnormal when the measurement result is not included in the expected value. When the measurement result is included in the expected value, it is determined that the low-speed clock is normal. The determination result of the comparison unit 43 is output to the output unit 44.

  The output unit 44 outputs a clock state indicating whether the low-speed clock is normal or abnormal. Specifically, when the low-speed clock abnormality is detected by the comparison unit 43, it is considered that the low-speed oscillator 21 has failed for some reason. Therefore, the output unit 44 outputs an abnormal signal indicating an abnormal state of the low-speed clock. To do. On the other hand, when the comparison unit 43 determines that the low-speed clock is normal, the output unit 44 outputs a normal signal indicating the normal state of the low-speed clock.

  The clock control unit 50 shown in FIG. 1 issues an oscillation / stop command to the low-speed oscillation unit 20 and the high-speed oscillation unit 30, and inputs the low-speed clock and the high-speed clock from the low-speed oscillation unit 20 and the high-speed oscillation unit 30, respectively. Are supplied to the functional unit 80. The clock control unit 50 also multiplies the low-speed clock and supplies it to the function unit 80 in response to a request from the function unit 80.

  Further, the clock control unit 50 performs the following operation while the normal signal is input from the low-speed clock confirmation unit 40. First, the clock control unit 50 causes the functional unit 80 to perform a normal operation (high-speed operation) by inputting a high-speed clock to the functional unit 80 in response to a request from the functional unit 80. Further, the clock control unit 50 causes the functional unit 80 to perform a low-consumption operation by inputting a low-speed clock to the functional unit 80 in response to a switching request from the functional unit 80.

  Further, the clock control unit 50 receives a high-speed oscillation / stop command from the intermittent control unit 70 and causes the high-speed oscillation unit 30 to oscillate / stop according to this command. As a result, the clock control unit 50 inputs the high-speed clock from the high-speed oscillation unit 30 and supplies the high-speed clock to the function unit 80 to operate the function unit 80 at high speed. Further, when the clock control unit 50 receives a command to stop the operation of the function unit 80 from the intermittent control unit 70, the clock control unit 50 stops the oscillation of the high-speed oscillation unit 30, stops the supply of the high-speed clock to the function unit 80, The operation of the function unit 80 is stopped.

  On the other hand, the clock control unit 50 performs the following operation while the abnormal signal is input from the low-speed clock confirmation unit 40. First, the clock control unit 50 prohibits the function unit 80 from transitioning from normal operation to low-speed operation. That is, the clock control unit 50 stops the supply of the low-speed clock to the function unit 80 so that the function unit 80 does not perform the low-consumption operation even when the function unit 80 requests to switch to the low-consumption operation. Therefore, the clock control unit 50 operates the functional unit 80 at high speed by inputting a high-speed clock to the functional unit 80.

  The clock control unit 50 divides the high-speed clock input from the high-speed oscillation unit 30 to generate a medium / high-speed clock that is slower than the high-speed clock and earlier than the low-speed clock. Is supplied to the functional unit 80. Since the function unit 80 also operates using a clock slower than the high-speed clock, the clock control unit 50 can also clock down the high-speed clock and supply it to the function unit 80 when an abnormality occurs in the low-speed clock. .

  When the clock control unit 50 is performing a low-consumption operation or an intermittent operation and receives an abnormal signal from the low-speed clock confirmation unit 40, the clock control unit 50 causes the function unit 80 to transition to a high-speed operation. That is, the functional unit 80 is operated at high speed by supplying a high-speed clock to the functional unit 80.

  The clock control unit 50 operates with the low-speed clock input from the low-speed oscillation unit 20, but receives the confirmation clock from the low-speed clock confirmation unit 40. When the clock state of the low-speed clock is abnormal, the confirmation clock is used urgently.

  The timer 60 inputs a low-speed clock from the low-speed oscillation unit 20 and counts a stop time of high-speed operation using the low-speed clock. Specifically, the timer 60 receives a setting command from the intermittent control unit 70, counts the stop time, and notifies the intermittent control unit 70 of the time-up when the stop time is counted.

  The intermittent control unit 70 operates the microcomputer 10 intermittently in response to a request from the function unit 80. The intermittent control unit 70 performs the following operation while the normal signal is input from the low-speed clock confirmation unit 40.

  That is, when there is a request for stopping the high-speed operation from the function unit 80, the intermittent control unit 70 makes a setting request for counting the stop time to the timer 60 and causes the timer 60 to count the stop time. Further, the intermittent control unit 70 instructs the clock control unit 50 to stop supplying the high-speed clock to the function unit 80. Thereby, the operation of the functional unit 80 stops. When the intermittent control unit 70 receives a time-up notification from the timer, the intermittent control unit 70 permits the operation of the functional unit 80 and instructs the clock control unit 50 to supply a high-speed clock to the functional unit 80.

  On the other hand, the intermittent control unit 70 prohibits the transition of the functional unit 80 to the intermittent operation even when the functional unit 80 requests intermittent control while the abnormal signal is input from the low-speed clock confirmation unit 40. Then, the intermittent control unit 70 outputs a command for causing the function unit 80 to supply a high-speed clock to the clock control unit 50.

  When an intermittent signal is input from the low-speed clock confirmation unit 40 while the intermittent control unit 70 operates the function unit 80 intermittently, the intermittent control unit 70 causes the function unit 80 to transition to high-speed operation. That is, the function unit 80 is operated at a high speed by giving an operation command to the function unit 80 and by giving the clock control unit 50 a command for supplying the function unit 80 with a high-speed clock.

  The intermittent control unit 70 operates with the low-speed clock input from the low-speed oscillation unit 20, but also receives the confirmation clock from the low-speed clock confirmation unit 40. When the clock state of the low-speed clock is abnormal, the confirmation clock is used urgently.

  The function unit 80 performs a predetermined operation using a high-speed clock or a low-speed clock input from the clock control unit 50. The function unit 80 is a part that executes timer, analog / digital conversion, serial communication, input / output, and the like by so-called software.

  In addition, a signal indicating the clock state of the low-speed clock is input from the low-speed clock confirmation unit 40 to the function unit 80. Therefore, when the function unit 80 recognizes the low-speed clock abnormality, the function unit 80 cancels the transition to the intermittent operation or the low-consumption operation, and requests the clock control unit 50 to supply the high-speed clock. As a result, the functional unit 80 performs a high-speed operation using the high-speed clock. The above is the overall configuration of the microcomputer 10 according to the present embodiment.

  Next, the operation of the microcomputer 10 will be described. Normally, the microcomputer 10 operates with a vehicle battery. For this reason, in order to reduce the current consumption of the microcomputer 10, the operation of the microcomputer 10 is changed between the normal time and the low time. During normal operation, high-speed operation is performed, and during low-speed operation, low-consumption operation or intermittent operation is performed.

  In such a normal operation of the microcomputer 10, the operation when the clock state of the low-speed clock becomes abnormal during the intermittent operation will be described with reference to the timing chart of FIG. FIG. 3 is a timing chart showing the state of the low-speed clock, the state of the confirmation clock, the clock state, and the state of the microcomputer 10.

  In addition, the confirmation clock generated by the confirmation clock oscillator 41 of the low-speed clock confirmation unit 40 does not fail, and the confirmation clock is always stable. Prior to time T1, the microcomputer 10 performs an intermittent operation that repeats a high-speed operation and a stop. Assume that during such an intermittent operation, an abnormality occurs in the low-speed clock due to a failure of the low-speed oscillator 21 at time T1. Here, it is assumed that the low-speed clock is no longer generated (no clock state).

  Then, as described above, the time measurement unit 42 of the low-speed clock confirmation unit 40 always measures the number of confirmation clocks in one cycle of the low-speed clock at a predetermined time using the confirmation clock, and the comparison unit 43 performs time measurement. The low-speed clock state is always determined using the measurement result of the measurement unit 42. Accordingly, when an abnormality occurs in the low-speed clock at time T1, the comparison unit 43 detects an abnormality in the low-speed clock at time T2 after a predetermined time has elapsed from time T1. That is, the time from time T1 to time T2 when an abnormality is detected corresponds to the time during which the number of confirmation clocks is counted and compared with the expected value.

  Thereafter, the output unit 44 receives the determination result of the comparison unit 43 and outputs an abnormal signal indicating that the low-speed clock is abnormal to the clock control unit 50, the intermittent control unit 70, and the function unit 80, respectively. Thereby, the clock control unit 50, the intermittent control unit 70, and the functional unit 80 prohibit the transition of the functional unit 80 to the intermittent operation.

  Specifically, the intermittent control unit 70 does not issue an instruction to stop the supply of the high-speed clock to the clock control unit 50 even if the functional unit 80 requests to stop the high-speed operation. Instructs to continue supplying the high-speed clock. Of course, the clock control unit 50 that has input the abnormal signal does not stop the supply of the high-speed clock to the function unit 80, and continues to supply the high-speed clock to the function unit 80 to keep the function unit 80 operating at high speed. Further, the function unit 80 stops the request for the intermittent operation to the intermittent control unit 70 in the software because the abnormal signal is input.

  As a result, as shown in FIG. 3, after the time T2, the intermittent operation indicated by the broken line is not performed in the state of the microcomputer 10, and the high speed operation is continued after the time T2. Therefore, the intermittent operation using the abnormal low-speed clock is not performed, and the operation of the microcomputer 10 is not stopped.

  In the above description, the case where an abnormality occurs in the low-speed clock during the intermittent operation has been described. However, the transition from the high-speed operation to the low-consumption operation is similarly prohibited. That is, even if the function unit 80 requests the clock control unit 50 to supply a low-speed clock to perform a low-consumption operation, the clock control unit 50 stops supplying the low-speed clock to the function unit 80, Supply a high-speed clock. On the other hand, the function unit 80 performs high-speed operation using a high-speed clock as software.

  In addition, when the operation of the functional unit 80 is stopped during the intermittent operation or when the low-speed clock is abnormal while the low-consumption operation is performed, switching to the high-speed operation is performed. That is, the intermittent control unit 70 instructs the clock control unit 50 to supply a high-speed clock, and the clock control unit 50 supplies the high-speed clock to the function unit 80. The function unit 80 stops the intermittent operation request to the intermittent control unit 70 and requests the clock control unit 50 to supply a high-speed clock for performing high-speed operation.

  As described above, when an abnormality occurs in the low-speed clock, the transition to the operation using the low-speed clock is prohibited. Then, the function unit 80 may request the medium high speed clock from the clock control unit 50. In this case, the clock control unit 50 divides the high-speed clock to generate a medium high-speed clock and supplies it to the function unit 80. Thereby, the function part 80 can perform each function using a medium-high-speed clock, and can perform operation | movement of each function of the microcomputer 10 continuously.

  As described above, the present embodiment is characterized in that the microcomputer 10 includes the low-speed clock confirmation unit 40 for determining the state of the low-speed clock.

  As described above, the microcomputer 10 has a built-in function capable of confirming the state where the low-speed clock is output, so that when the low-speed clock is not stable, the switching to the low-consumption operation is canceled or the low-consumption operation is being performed. When the low-speed clock is not stable, it can be forcibly switched to normal operation.

  That is, the abnormality of the low-speed clock can be detected and the abnormality can be notified to the intermittent control unit 70, the clock control unit 50, and the function unit 80, respectively, so that the microcomputer 10 does not transition from the normal operation to the low-speed operation. be able to. Therefore, it is possible to prevent the operation of the microcomputer 10 from being stopped by using the low-speed clock when the low-speed clock is not stable.

  As for the correspondence relationship between the description of the present embodiment and the description of the scope of claims, the portion constituted by the time measurement section 42 and the comparison section 43 corresponds to the determination section of the scope of claims, and the clock control section 50 And the part comprised by the intermittent control part 70 respond | corresponds to the control part of a claim.

(Other embodiments)
In the first embodiment, the expected value used in the comparison unit 43 of the low-speed clock confirmation unit 40 is a value set in the comparison unit 43 in advance. However, it can be changed by a command from the function unit 80, for example. Thereby, since an expected value can be set according to the frequency of the low-speed clock, the versatility of the microcomputer 10 can be enhanced.

  In the first embodiment, a signal indicating the clock state output from the low-speed clock confirmation unit 40 is input to the function unit 80. However, the fact that the function unit 80 has recognized the abnormality of the low-speed clock is externally applied. May be output. For example, the microcomputer 10 is provided with an external output terminal, and this terminal and the functional unit 80 are connected, and the abnormality of the low-speed clock can be transmitted to the user of the microcomputer 10 through this terminal. As a result, the microcomputer 10 and the low-speed oscillator 21 can be replaced.

DESCRIPTION OF SYMBOLS 10 Microcomputer 40 Low-speed clock confirmation part 42 Time measurement part 43 Comparison part 44 Output part 50 Clock control part 70 Intermittent control part

Claims (2)

  1. A microcomputer that realizes a predetermined function by any one of a normal operation using a high-speed clock and a low-speed operation using a low-speed clock slower than the high-speed clock,
    A determination unit (42, 43) for determining whether there is an abnormality in the low-speed clock by inputting the low-speed clock, and when the abnormality in the low-speed clock is detected by the determination unit (42, 43), A low-speed clock confirmation unit (40) having an output unit (44) for outputting an abnormal signal indicating an abnormal state ;
    When the abnormal signal is input from the low-speed clock confirmation unit (40), the high-speed clock is input, and the high-speed clock is divided to generate a medium-high-speed clock that is slower than the high-speed clock and faster than the low-speed clock. And a control unit (50, 70) using the medium high-speed clock for the normal operation .
  2. Wherein the control unit (50, 70), the low-speed clock check unit (40) upon receiving the abnormal signal from claim 1, wherein the benzalkonium prohibited the transition to the low-speed operation from the normal operation A microcomputer according to 1.
JP2009076061A 2009-03-26 2009-03-26 Microcomputer Active JP5347631B2 (en)

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JP2012147220A (en) * 2011-01-12 2012-08-02 Panasonic Corp Radio communication apparatus
JP5774344B2 (en) * 2011-03-30 2015-09-09 ラピスセミコンダクタ株式会社 Clock signal generation circuit
JP2013114589A (en) * 2011-11-30 2013-06-10 Seiko Epson Corp Micro-controller
JP6135445B2 (en) * 2013-10-16 2017-05-31 富士通セミコンダクター株式会社 Semiconductor integrated circuit and operation control method of semiconductor integrated circuit

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JP2854194B2 (en) * 1992-06-29 1999-02-03 三洋電機株式会社 Oscillation clock judgment device for microcomputer
JPH0635562A (en) * 1992-07-17 1994-02-10 Hitachi Seiko Ltd Abnormal operation preventing circuit for microcomputer
JP3895912B2 (en) * 2000-09-01 2007-03-22 矢崎総業株式会社 Control unit and multiplex communication system

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