JP2013114589A - Micro-controller - Google Patents

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Publication number
JP2013114589A
JP2013114589A JP2011262479A JP2011262479A JP2013114589A JP 2013114589 A JP2013114589 A JP 2013114589A JP 2011262479 A JP2011262479 A JP 2011262479A JP 2011262479 A JP2011262479 A JP 2011262479A JP 2013114589 A JP2013114589 A JP 2013114589A
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Prior art keywords
clock signal
circuit
microcontroller
abnormality
abnormality detection
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JP2011262479A
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Japanese (ja)
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Keisuke Nakamura
佳祐 中村
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Seiko Epson Corp
セイコーエプソン株式会社
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Priority to JP2011262479A priority Critical patent/JP2013114589A/en
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Abstract

PROBLEM TO BE SOLVED: To reliably prevent false operation.SOLUTION: A micro-controller comprises: an arithmetic circuit that is supplied with clock signals and operates; an oscillator circuit for generating a first clock signal; a PLL circuit for generating a second clock signal on the basis of a reference clock; an abnormality detection circuit for detecting abnormality of the second clock signal; a selection circuit that selects either the first clock signal or the second clock signal, supplies one thereof selected to the arithmetic circuit, selects the first clock signal at the time of power activation, switches from the first clock signal to the second clock signal in response to setting of a firmware in a case where the abnormality is not detected by the abnormality detection circuit and, in a case where the abnormality is detected by the abnormality detection circuit, does not perform switch over from the first clock signal to the second clock signal regardless of the setting of the firmware; and a status register for, in the case where the abnormality is detected by the abnormality detection circuit, notifying the arithmetic circuit that the switching over from the first clock signal to the second clock signal is not performed.

Description

  The present invention relates to a microcontroller.

  The microcontroller includes an arithmetic circuit that operates when supplied with a clock signal. Also, as such a microcontroller, two clock signals, a main clock and a spare clock, are prepared, and when the main clock stops for some reason, it is proposed to switch to the spare clock and continue the operation. (For example, refer to Patent Document 1).

JP-A-7-182065

In the above-described microcontroller, the standby clock was used when the main clock stopped, but the main clock becomes abnormal (for example, a frequency at which the arithmetic circuit does not operate) due to a setting error or the like during device development, for example. There is. In this case, if the main clock is used, the microcontroller may malfunction.
Therefore, an object of the present invention is to reliably prevent malfunction.

  A main invention for achieving the above object includes an arithmetic circuit that operates by being supplied with a clock signal, an oscillation circuit that generates a first clock signal, a PLL circuit that generates a second clock signal based on a reference clock, An abnormality detection circuit for detecting an abnormality of the second clock signal; and a selection circuit for selecting one of the first clock signal and the second clock signal and supplying the selected operation signal to the arithmetic circuit. When one clock signal is selected and no abnormality is detected by the abnormality detection circuit, the first clock signal is switched to the second clock signal according to the firmware setting, and an abnormality is detected by the abnormality detection circuit. In this case, a selection circuit that does not switch from the first clock signal to the second clock signal regardless of the setting of the firmware. A status register for notifying the arithmetic circuit that the switching from the first clock signal to the second clock signal has not been performed when an abnormality is detected by the abnormality detection circuit. This is a microcontroller.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

2 is a block diagram of the printer 1. FIG. 1 is a schematic cross-sectional view of an apparatus main body 2 of a printer 1. It is the schematic diagram which showed the raster line formed in each pass in the case of printing by 4 passes. It is a schematic diagram for demonstrating the movement of a head. 3 is a block diagram illustrating an example of a configuration of a sub-board 300. FIG. It is a block diagram which shows the structure of the microcontroller 400 in 1st Embodiment. It is a block diagram which shows the abnormality detection circuit 406 in 1st Embodiment. FIG. 6 is a flowchart showing the operation of the microcontroller 400 when the printer 1 is activated. It is a block diagram which shows the structure of the microcontroller 400 in 2nd Embodiment. It is a block diagram which shows abnormality detection circuit 406 'in 2nd Embodiment.

  At least the following matters will become clear from the description of the present specification and the accompanying drawings.

An arithmetic circuit that operates by being supplied with a clock signal, an oscillation circuit that generates a first clock signal, a PLL circuit that generates a second clock signal based on a reference clock, and an abnormality that detects an abnormality of the second clock signal A selection circuit for selecting one of the first clock signal and the second clock signal and supplying the selected one to the arithmetic circuit, wherein the first clock signal is selected at power-on, and the abnormality detection circuit If no abnormality is detected, the first clock signal is switched to the second clock signal according to the firmware setting. If an abnormality is detected by the abnormality detection circuit, the firmware setting is not affected. In addition, an abnormality is detected by the selection circuit that does not switch from the first clock signal to the second clock signal and the abnormality detection circuit. The case, microcontroller, characterized in that and a status register to inform the arithmetic circuit that switching from the first clock signal to the second clock signal is not performed becomes apparent.
According to such a microcontroller, when the second clock signal output from the PLL circuit becomes abnormal, the second clock signal is not supplied to the arithmetic circuit, so that the malfunction due to the arithmetic circuit is surely prevented. Can do.

In this microcontroller, the abnormality detection circuit may detect the presence or absence of abnormality of the second clock signal by monitoring an input voltage to the voltage controlled oscillator of the PLL circuit.
According to such a microcontroller, the abnormality of the second clock signal can be reliably detected.

In this microcontroller, the abnormality detection circuit includes a monitoring logic circuit to which the second clock signal is input, and the second clock is based on whether the monitoring logic circuit operates normally. The presence or absence of signal abnormality may be detected.
According to such a microcontroller, the abnormality of the second clock signal can be reliably detected.

In such a microcontroller, it is desirable to enable the abnormality detection circuit only when a debug flag indicating that an error occurring during the programming process of the microcontroller is debugged is in an on state.
According to such a microcontroller, the debugging efficiency can be improved.

  Such a microcontroller is preferably provided in an image forming apparatus that forms an image on a printing medium.

In this microcontroller, the image forming apparatus is located at a position away from the main board by a predetermined distance, and a replaceable consumable of the image forming apparatus is located at a position closer than the predetermined distance. It is desirable that the sub-board be disposed on the sub-board.
According to such a microcontroller, signal transmission between the main board and the consumable can be accurately performed.

In such a microcontroller, it is preferable to read / write data from / to a storage element provided in the consumable according to an instruction from the main board.
According to such a microcontroller, it is possible to reliably read and write data in the storage element.

  In the following embodiments, a description will be given by taking as an example a micro-controller provided in a lateral ink jet printer (hereinafter also referred to as printer 1). The printer 1 is an industrial large printer.

=== First Embodiment ===
First, a configuration example of the printer 1 will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of the printer 1. FIG. 2 is a schematic cross-sectional view of the apparatus main body 2 of the printer 1.
In the following description, the terms “vertical direction” and “front-rear direction” refer to the direction indicated by the arrow in FIG. In addition, the “left-right direction” refers to a direction orthogonal to the paper surface in FIG.
In the present embodiment, a description will be given using roll paper S (continuous paper) as a medium on which the printer 1 records an image.
As shown in FIG. 1, the printer 1 according to the present embodiment includes an apparatus main body 2 and an ink cartridge holder unit 3 disposed on the right side of the apparatus main body 2.

≪About the configuration example on the main unit side≫
As shown in FIGS. 1 and 2, the apparatus main body 2 of the printer 1 includes a transport unit 20 and a feeding unit 10 and a platen 29 along a transport path along which the transport unit 20 transports the roll paper S. And a winding unit 70, a head unit 30, a carriage unit 40, a controller 60 for controlling these units and controlling the operation as the printer 1, a detector group 50, and a power supply unit. 80.

  The feeding unit 10 feeds the roll paper S to the transport unit 20. The feeding unit 10 includes a winding shaft 18 around which the roll paper S is wound and rotatably supported, a relay roller 19 for winding the roll paper S fed from the winding shaft 18 and guiding the roll paper S to the transport unit 20; have.

  The transport unit 20 transports the roll paper S sent by the feeding unit 10 along a preset transport path. As shown in FIG. 2, the transport unit 20 includes a relay roller 21 that is positioned horizontally rearward with respect to the relay roller 19, a relay roller 22 that is positioned obliquely below the relay roller 21, and a relay roller 22. The first conveying roller 23 located obliquely upward (as viewed from the platen 29 in the direction in which the roll paper S is conveyed) and the rear (the rolled paper S is conveyed from the first conveying roller 23). 2, the second conveying roller 24 located downstream from the platen 29, the reversing roller 25 positioned vertically downward as viewed from the second conveying roller 24, and the rear as viewed from the reversing roller 25. A relay roller 26 and a delivery roller 27 positioned above the relay roller 26 are provided.

The relay roller 21 is a roller that winds the roll paper S sent from the relay roller 19 from the front and loosens it downward.
The relay roller 22 is a roller that winds the roll paper S sent from the relay roller 21 from the front and conveys it obliquely upward.

  The first transport roller 23 includes a first drive roller 23a driven by a motor (not shown), and a first driven roller 23b arranged to face the first drive roller 23a with the roll paper S interposed therebetween. have. The first transport roller 23 is a roller that pulls up the roll paper S slacked downward and transports it to the printing region R facing the platen 29. The first transport roller 23 temporarily stops transport during a period in which image recording is performed on a portion of the roll paper S on the printing region R. In addition, when the first driven roller 23b rotates as the first drive roller 23a rotates by the drive control of the controller 60, the transport amount of the roll paper S positioned on the platen 29 (the length of the portion of the roll paper) Is adjusted).

  As described above, the transport unit 20 has a mechanism for transporting the portion of the roll paper S wound between the relay rollers 21 and 22 and the first transport roller 23 by slacking downward. The slack of the roll paper S is monitored by the controller 60 based on a detection signal from a slack detection sensor (not shown). Specifically, when a portion of the roll paper S slackened between the relay rollers 21 and 22 and the first transport roller 23 is detected by the slack detection sensor, a tension of an appropriate magnitude is applied to the portion. Therefore, the transport unit 20 can transport the roll paper S in a relaxed state. On the other hand, when the portion of the roll paper S that has been loosened is not detected by the slack detection sensor, an excessive amount of tension is applied to the portion, and therefore the transport of the roll paper S by the transport unit 20 is temporarily performed. And the tension is adjusted to an appropriate level.

  The second transport roller 24 includes a second drive roller 24a driven by a motor (not shown), and a second driven roller 24b disposed to face the second drive roller 24a with the roll paper S interposed therebetween. have. The second transport roller 24 is a roller that transports the portion of the roll paper S on which the image is recorded by the head unit 30 in the horizontal rear direction along the support surface of the platen 29 and then transports it vertically downward. Thereby, the conveyance direction of the roll paper S is changed. The second driven roller 24b rotates as the second drive roller 24a is driven to rotate by the drive control of the controller 60, whereby the predetermined portion given to the portion of the roll paper S located on the platen 29 is obtained. Tension is adjusted.

The reversing roller 25 is a roller that winds the roll paper S sent from the second transport roller 24 from the upper front side and transports the rear obliquely upward.
The relay roller 26 is a roller that wraps the roll paper S sent from the reversing roller 25 from the lower front side and conveys it upward.
The feed roller 27 is configured to wind the roll paper S sent from the relay roller 26 from the lower front side and send it to the take-up unit 70.

  As described above, the roll paper S moves sequentially through the rollers, whereby a transport path for transporting the roll paper S is formed. The roll paper S is intermittently transported along the transport path in units of areas corresponding to the print areas R by the transport unit 20 (that is, one page worth of the roll paper S on the print area R). Each time image recording is performed, intermittent conveyance is performed).

  The platen 29 supports a portion of the roll paper S located in the printing region R on the transport path. As shown in FIG. 2, the platen 29 is provided in correspondence with the printing region R on the conveyance path, and in a region along the conveyance path between the first conveyance roller 23 and the second conveyance roller 24. Has been placed.

  The head unit 30 is for ejecting ink as an example of a liquid onto a portion of the roll paper S that has been fed into the printing region R on the transport path (on the platen 29) by the transport unit 20. The head unit 30 includes a head 31, a valve unit 34, and a cleaning unit 35.

  The head 31 has a nozzle row in which nozzles are arranged in the row direction on the lower surface thereof. In the present embodiment, each of colors such as yellow (Y), magenta (M), cyan (C), and black (K) has a nozzle row composed of a plurality of nozzles # 1 to #N. The nozzles # 1 to #N in each nozzle row are linearly arranged in a crossing direction that intersects the transport direction of the roll paper S (that is, the crossing direction is the above-described row direction). Each nozzle row is arranged in parallel with a space between each other along the transport direction.

  Each nozzle # 1 to #N is provided with a piezo element (not shown) as a drive element for ejecting ink droplets. When a voltage having a predetermined time width is applied between the electrodes provided at both ends of the piezoelectric element, the piezoelectric element expands according to the voltage application time and deforms the side wall of the ink flow path. As a result, the volume of the ink flow path contracts according to the expansion and contraction of the piezo element, and the ink corresponding to the contraction is ejected from the nozzles # 1 to #N of the respective colors as ink droplets.

  Further, as will be described later, the head 31 can reciprocate in the transport direction (that is, the front-rear direction) and the row direction (that is, the left-right direction).

  The valve unit 34 is for temporarily storing ink, and ink is supplied from an ink cartridge attached to a cartridge holder portion 310 of the ink cartridge holder unit 3 described later. The valve unit 34 is connected to the head 31 via an ink supply tube (not shown). For this reason, the head 31 can perform image recording by discharging the ink supplied from the valve unit 34 toward the portion of the roll paper S that has been transported from the nozzle onto the platen 29 and stopped. .

  The cleaning unit 35 is for cleaning the head 31. The cleaning unit 35 is provided at a home position (hereinafter referred to as HP, see FIG. 2), and includes a cap, a suction pump, and the like. When the head 31 (carriage 42) moves in the transport direction (front-rear direction) and is positioned on the HP, a cap (not shown) comes into close contact with the lower surface (nozzle surface) of the head 31. When the suction pump operates in such a state that the cap is in close contact, the ink in the head 31 is sucked together with the thickened ink and paper dust. In this way, the clogged nozzle recovers from the non-ejection state, thereby completing the head cleaning.

  The carriage unit 40 is for moving the head 31. The carriage unit 40 is supported so as to reciprocate in the transport direction (front-rear direction) along the carriage guide rail 41 and a carriage guide rail 41 extending in the transport direction (front-rear direction) (indicated by a two-dot chain line in FIG. 2). A carriage 42 and a motor (not shown).

  The carriage 42 is configured to move in the transport direction (front-rear direction) integrally with the head 31 by driving a motor (not shown). The carriage 42 is provided with a head guide rail (not shown) extending in the row direction (left-right direction). The head 31 is driven in the row direction (left-right direction) along the head guide rail by driving the motor. Configured to move to.

  The winding unit 70 is for winding the roll paper S (image-recorded roll paper) sent by the transport unit 20. The winding unit 70 is fed from the relay roller 71 that is rotatably supported and a relay roller 71 for winding the roll paper S sent from the feed roller 27 from the upper front side and transporting it obliquely downward. And a take-up drive shaft 72 for taking up the roll paper S.

  The controller 60 is a control unit for controlling the printer 1. As illustrated in FIG. 1, the controller 60 includes interface units 61 </ b> A and 61 </ b> B, a CPU 62, a memory 63, and a unit control circuit 64. The interface unit 61A is for transmitting and receiving data between the host computer 110, which is an external device, and the printer 1. The interface unit 61B is for transmitting and receiving data to and from the sub substrate 300 of the ink cartridge holder unit 3. The CPU 62 is an arithmetic processing unit for controlling the entire printer 1. The memory 63 is for securing an area for storing a program of the CPU 62, a work area, and the like. The CPU 62 controls each unit by the unit control circuit 64 in accordance with a program stored in the memory 63. The controller 60 is provided on the main board 200.

  The detector group 50 is for monitoring the situation in the printer 1. For example, a rotary encoder that is attached to a transport roller and used for control of transport of the medium, a sheet for detecting the presence or absence of the transported medium, and the like. There are a detection sensor, a linear encoder for detecting the position of the carriage 42 (or head 31) in the conveyance direction (front-rear direction), and the like.

  The power supply unit 80 is fixed to the apparatus main body 2. And it is connected to an outlet etc. via the electric cord etc. which are not illustrated. Note that the power supply unit 80 includes a power switch 81 that performs a power ON / OFF operation. When the power switch 81 is turned on, power is supplied to the printer 1.

≪About operation example of printer 1≫
As described above, the printer 1 according to the present embodiment includes the head 31 having a nozzle row in which nozzles are arranged in the row direction (left-right direction). Then, the controller 60 ejects ink from the nozzles while moving the head 31 in the transport direction (front-rear direction), and forms a raster line along the transport direction (front-rear direction). An image of one page is recorded on the roll paper S.

  Here, the controller 60 according to the present embodiment executes printing of a plurality of passes (two passes, four passes, etc.). That is, in order to increase the resolution of the image in the column direction, printing is performed by changing the position of the head 31 in the column direction little by little for each pass. In this embodiment, four-pass printing is executed. As an image forming method, for example, known interlace (microweave) printing is executed.

  This will be described more specifically with reference to FIG. FIG. 3 is a schematic diagram showing raster lines formed in each pass in a case of printing in 4 passes.

  A nozzle row (nozzles) of the head 31 is shown on the left side of FIG. 3, and a raster line is formed by ejecting ink from the nozzles while the head 31 (nozzle row) moves in the transport direction. . The position in the row direction of the head 31 (nozzle row) shown in the figure is the position in the first pass, and if the head 31 (nozzle row) moves in the transport direction while maintaining this position, one pass The printing of the eyes is executed, and five raster lines shown in the figure (raster line L1 written as pass 1 at the right end of the figure) are formed.

  Next, when the head 31 (nozzle row) moves in the row direction, and the head 31 (nozzle row) moves in the transport direction while maintaining the moved position, the second pass printing is executed, and FIG. The four raster lines (raster line L2 written with path 2 on the right end) are formed. Since interlace (microweave) printing is employed, the raster line L2 adjacent to the raster line L1 is formed by ink ejected from a nozzle different from the nozzle from which the ink forming the raster line L1 is ejected. Will be. Therefore, the moving distance of the head 31 (nozzle row) in the row direction is not a quarter of the distance between nozzles (eg, 1/180 inch) (1/180 × 1/4 = 1/720 inch), The distance is larger than this.

  Thereafter, by performing the same operation, printing of the third pass and the fourth pass is executed, and the remaining raster lines shown in the figure (raster line L3 and pass 4 written as pass 3 on the right end). Raster line L4) is formed. Thus, by forming raster lines in four passes, the resolution of the image in the column direction can be made four times (= 720 ÷ 180).

  In the present embodiment, so-called bidirectional printing is performed. That is, the movement direction of the head 31 (nozzle row) when the first pass and the third pass printing are performed is different from the movement direction of the head 31 (nozzle row) when the second pass, the fourth pass and the second print are performed. The reverse direction (detailed later).

  In the following, an image forming operation (in other words, an ink ejection operation) of the printer 1 will be described as an operation example of the printer 1, but the case of FIG. In the description, FIG. 3 is also referred to as needed).

<Example of Image Forming Operation of Printer 1>
Here, an example of the printing operation of the printer 1 will be described with reference to FIGS. FIG. 4 is a schematic diagram for explaining the movement of the head. Before explaining the printing operation, first, FIG. 4 will be described.

  FIG. 4 shows how the head moves during the printing process (that is, a series of processes related to image formation). Here, in order to make the description easy to understand, the description is made on the assumption that the number of heads 31 (and nozzle rows) is one instead of a plurality.

  For convenience, the head 31 is represented by a circle (there are a large circle and a small circle in the figure, but there is no meaning in distinguishing both), and the movement of the head is represented by an arrow. Here, the arrows pointing in the front-rear direction in the figure indicate the movement of the head in the transport direction, and the arrows pointing in the left-right direction indicate the movement of the head in the row direction. In addition, each arrow is provided with a reference numeral S1 to S10, which is a step number used in the description of the subsequent printing process.

  Further, there are step numbers to which pass 1 to pass 4 are attached, and these step numbers represent steps in which an image forming operation is executed by ejecting ink.

  Hereinafter, the printing process will be described with reference to FIGS. 3 and 4. The printing process is realized mainly by the controller 60. In particular, in the present embodiment, it is realized by the CPU 62 processing a program stored in the memory 63. And this program is comprised from the code | cord | chord for performing the various operation | movement demonstrated below.

  When the above-described intermittent roll paper S is transported and the roll paper S is stopped, a printing process for forming an image for one page on the portion of the roll paper S on the print region R is started.

  First, the controller 60 moves the carriage 42 (that is, each head) in the forward direction from the HP position (the direction from the upstream side to the downstream side in the direction in which the roll paper S is conveyed) (step S1).

  The controller 60 performs the first pass printing by causing the head to eject ink while continuing the movement of the head 31 in the forward direction (step S2). As a result, the raster line L1 (raster line of pass 1) shown in FIG. 6 is formed.

  When the head reaches the first folding position, the controller 60 moves the head in the column direction (step S3). In the present embodiment, the head is moved by the distance d.

  Thereafter, the controller 60 performs the second pass printing by causing the head to eject ink while moving the head in the backward direction (the direction from the downstream side to the upstream side in the direction in which the roll paper S is conveyed). (Step S4). As a result, the raster line L2 (raster line of pass 2) shown in FIG. 3 is formed.

  When the head reaches the second folding position, the controller 60 moves the head in the column direction (step S5). In the present embodiment, the head is moved by the distance d.

  Next, the controller 60 further performs the same processing as the processing from step S2 to step S4 (step S6 to step S8). In this process, the raster line L3 (raster line of pass 3) shown in FIG. 6 by the third pass printing (step S6) is changed to the raster line shown in FIG. 6 by the fourth pass printing (step S8). L4 (raster line of pass 4) is formed respectively. The controller 60 returns the position of the head in the row direction (step S9). That is, the head is moved by a distance 3d in the direction opposite to the direction in which the head has moved in steps S3, S5, and S7.

  Then, the controller 60 moves the head to the HP position (step S10), and ends the printing process for forming an image for one page. In this embodiment, image formation for one page is performed in four passes, but the present invention is not limited to this. For example, image formation for one page may be performed in two passes. In this embodiment, interlace (microweave) printing is performed, but the present invention is not limited to this. For example, band printing may be performed.

≪Ink cartridge holder unit configuration example≫
As shown in FIG. 1, the ink cartridge holder unit 3 includes a sub substrate 300 and a cartridge holder portion 310.

<About the cartridge holder>
The cartridge holder portion 310 is provided with cartridge holders H1 to H4 for detachably mounting ink cartridges containing ink. The ink and the ink cartridge in which the ink is stored correspond to a consumable item for the printer 1. Ink cartridges of various types (colors) of ink are detachably attached to the cartridge holders H1 to H4. The cartridge holders H1 to H4 correspond to the nozzle rows of the respective colors of the head 31. The ink of each ink cartridge mounted on the cartridge holders H1 to H4 is supplied to the valve unit 34 through an ink supply tube (not shown), and further supplied to the head 31 via an ink supply tube (not shown). For example, when the cartridge holder H1 corresponds to the cyan nozzle row of the head 31, by installing a cyan ink cartridge in the cartridge holder H1, cyan ink is supplied to the cyan nozzle row. .

  Thus, the head 31 discharges the ink supplied from each cartridge holder. In the present embodiment, as described above, an image is printed using four colors of ink of yellow (Y), magenta (M), cyan (C), and black (K). That is, any of the four color ink cartridges is mounted on the cartridge holders H1 to H4.

  The ink cartridge (not shown) includes a cartridge main body that contains ink therein, a substrate provided in the cartridge main body, and a storage element (also referred to as CSIC) provided on the substrate. The CSIC is an element for transferring various data to and from the printer 1 (controller 60) when an ink cartridge is mounted in the cartridge holders H1 to H4 of the cartridge holder unit 310, and is a non-volatile memory (for example, a flash memory). Memory) and other elements capable of storing data. The CSIC stores, for example, information indicating characteristics such as the color, density, and viscosity of ink stored in the cartridge, various print control programs, and the like. The ink cartridge is formed with a plurality of connection terminals electrically connected to the storage element exposed.

  On the other hand, the cartridge holders H1 to H4 of the cartridge holder portion 310 have a plurality of connection terminals (not shown) for electrically connecting to a plurality of connection terminals of the ink cartridge when the ink cartridge is mounted. Is formed.

  When the ink cartridge is mounted in the cartridge holders H1 to H4 of the cartridge holder portion 310, ink can be supplied from the ink cartridge to the head 31 of the apparatus main body 2 of the printer. Further, when the ink cartridge is mounted in the cartridge holders H1 to H4, the plurality of connection terminals of the ink cartridge and the plurality of connection terminals of the cartridge holders H1 to H4 are electrically connected to each other via the sub-substrate 300. Data can be exchanged between the main substrate 200 (controller 60) of the printer 1 and the storage element of the ink cartridge.

  As described above, when the ink cartridge is mounted on the cartridge holder portion 310 of the ink cartridge holder unit 3, the main board 200 (controller 60) can read data from the storage element of the ink cartridge via the sub board 300. Data can be written to the storage element of the ink cartridge.

<Sub-board>
In the case of a large-sized printer such as the printer 1 of the present embodiment, the position of the main substrate 200 and the cartridge holder unit 310 may be considerably separated. In this case, if the main board 200 and the cartridge holder 310 are directly electrically connected, the signal transmission distance becomes very long. For this reason, for example, a signal is lost, and there is a possibility that accurate communication cannot be performed. Therefore, in the present embodiment, the sub board 300 is provided between the main board 200 and the cartridge holder portion 310. The storage element (CSIC) of the cartridge is read or written from the main board 200 through the sub board 300. By providing the sub-board 300 in this manner, signal transmission between the main board 200 and the CSIC of the ink cartridge is stabilized.

FIG. 5 is a block diagram illustrating an example of the configuration of the sub-board 300.
A sub substrate 300 shown in FIG. 5 includes a microcontroller 400. The sub-board 300 includes an interface unit (not shown) for communicating with the main board 200 and the cartridge holder unit 310. In the present embodiment, the sub board 300 is provided in the ink cartridge holder unit 3. In other words, it is located at a certain distance from the main substrate 200 and is located at a position (shorter than the certain distance) near the cartridge holder portion 310 (in other words, the ink cartridge).

≪About the structure of the microcontroller≫
FIG. 6 is a block diagram showing an example of the configuration of the microcontroller 400 in the first embodiment.
As shown in FIG. 6, the microcontroller 400 of the first embodiment includes an internal oscillation circuit 401, an inverter 402, a PLL circuit 403, a selector 404, a CPU core 405, an abnormality detection circuit 406, and a selection control circuit. 407.

The internal oscillation circuit 401 generates and outputs a clock signal having a predetermined frequency (hereinafter referred to as a first clock signal) by an internal oscillator (not shown).
The inverter 402 constitutes an oscillation circuit that generates a reference clock together with the external oscillation element 330 provided on the sub-board 300 (outside the microcontroller 400). For example, a crystal oscillator is used for the external oscillation element 330.

  A PLL (Phase Locked Loop) circuit 403 generates a clock signal (hereinafter referred to as a second clock signal) based on an oscillation clock (reference clock) of the external oscillation element 330. Details of the PLL circuit 403 will be described later.

  The selector 404 selects either the first clock signal output from the internal oscillation circuit 401 or the second clock signal output from the PLL circuit 403 and supplies it to the CPU core 405 as a system clock.

  The CPU core 405 performs various numerical calculations, information processing, device control, and the like according to programs, and includes an arithmetic circuit 415 that performs logical operations and control, and a storage circuit 416 that stores programs, data, and the like (for example, flash memory). And RAM). In addition, the storage circuit 416 includes a setting register 417 and a status register 418.

  The abnormality detection circuit 406 detects the presence or absence of an abnormality (such as an abnormality in the clock frequency) of the second clock signal generated by the PLL circuit 403. Details of the abnormality detection circuit 406 will be described later.

  The selection control circuit 407 is for controlling the selection of the selector 404 based on the detection result of the abnormality detection circuit 406 and the setting of the setting register 417 (in other words, controlling the switching of the clock signal). In the present embodiment, the selector 404 and the selection control circuit 407 correspond to a selection circuit.

<About PLL circuit>
As shown in FIG. 6, the PLL circuit 403 includes a 1 / n frequency dividing circuit 410, a phase comparison circuit 411, a low-pass filter (hereinafter also referred to as LPF) 412, and a voltage controlled oscillator (hereinafter also referred to as VCO) 413. And a 1 / m frequency dividing circuit 414.

  The 1 / n frequency dividing circuit 410 generates a frequency signal (referred to as a third clock signal) obtained by dividing the oscillation clock (reference clock) of the external oscillation element 330 by 1 / n and outputs it to the phase comparison circuit 411. For example, when n = 10, the output frequency is 1 MHz when the input frequency is 10 MHz.

  The phase comparison circuit 411 includes a third clock signal output from the 1 / n frequency dividing circuit 410 and a second clock output from the PLL circuit 403 (more specifically, a 1 / m frequency dividing circuit 414 described later). Phase comparison of signals is performed, and the phase difference is output in the form of voltage (or current).

  The LPF 412 is, for example, an RC integration circuit having a resistor and a capacitor, and smoothes the AC voltage component (high frequency component) of the output voltage of the phase comparison circuit 411 by removing it with the capacitor.

  A VCO (Voltage Controlled Oscillator) 413 outputs a frequency signal (pulse signal) corresponding to the input voltage. For example, a higher frequency signal is output as the input voltage is higher, and a lower frequency signal is output as the input voltage is lower. As described above, the VCO 413 generates a frequency signal having an oscillation frequency corresponding to the voltage from the LPF 412 and outputs the frequency signal to the 1 / m frequency dividing circuit 414. As the VCO 413, a crystal oscillator (not shown), an oscillator using lithium tantalate (LiTaO3), or the like can be applied.

  The 1 / m divider circuit 414 is a circuit having the same configuration as the 1 / n divider circuit 410, generates a clock signal (second clock signal) obtained by dividing the output signal of the VCO 413 by 1 / m, and selects the selector 404. And output to the phase comparison circuit 411.

  Next, the operation of the PLL circuit 403 will be described. Phase comparison between the output of the 1 / n frequency divider 410 (third clock signal) and the output of the 1 / m frequency divider 414 (second clock signal) based on a reference signal input from the outside is performed. This is performed by the phase comparison circuit 411. Then, the phase comparison circuit 411 outputs this phase difference component as a pulsed phase difference signal.

  Next, the phase difference signal is input to the VCO 413 after the high frequency component is blocked by the LPF 412. The VCO 413 outputs a frequency signal (pulse signal) corresponding to the input voltage, and the frequency signal is divided by the 1 / m divider circuit 414 and output as a second clock signal, and is also fed back to the phase comparator circuit 411 ( Feedback loop).

  In this way, the PLL circuit 403 generates the second clock signal based on the external reference clock. The second clock signal can be set to a required frequency by setting the 1 / n frequency dividing circuit 410 and the 1 / m frequency dividing circuit 414 (that is, setting the values of “n” and “m”). is there. In the present embodiment, the second clock signal generated by the PLL circuit 403 is used as the main clock.

<About the abnormality detection circuit>
FIG. 7 is a block diagram showing an example of the abnormality detection circuit 406 in the first embodiment.
The abnormality detection circuit 406 of the first embodiment includes an upper limit voltage comparator 421, a lower limit voltage comparator 422, and an OR circuit (OR circuit) 423.

  The input voltage to the VCO 413 is applied to the non-inverting input (+ terminal: not shown) of the upper limit voltage comparator 421, and the upper limit voltage is applied to the inverting input (− terminal: not shown). The upper limit voltage comparator 421 outputs a high level voltage (hereinafter also referred to as H level) if the voltage of the non-inverting input (+ terminal) is higher than the voltage of the inverting input (− terminal). In other words, if the input voltage to the VCO 413 is higher than the upper limit voltage, an H level voltage is output. On the other hand, if the voltage at the non-inverting input (+ terminal) is lower than the voltage at the inverting input (−terminal), a low level voltage (hereinafter also referred to as L level) is output.

  The lower limit voltage is applied to the non-inverting input (+ terminal: not shown) of the lower limit voltage comparator 422, and the input voltage to the VCO 413 is applied to the inverting input (− terminal: not shown). The lower limit voltage comparator 422 outputs an H level voltage if the voltage of the non-inverting input (+ terminal) is higher than the voltage of the inverting input (−terminal). In other words, if the input voltage to the VCO 413 is lower than the lower limit voltage, an H level voltage is output. On the other hand, if the voltage at the non-inverting input (+ terminal) is lower than the voltage at the inverting input (−terminal), an L level voltage is output.

  The OR circuit 423 outputs an H level if at least one of the outputs of the upper limit voltage comparator 421 and the lower limit voltage comparator 422 is at an H level, and both outputs of the upper limit voltage comparator 421 and the lower limit voltage comparator 422 are at an L level. If it is level, L level is output.

  With the above configuration, when the output of the abnormality detection circuit 406 is at the H level, an abnormality has occurred in at least one of the upper limit voltage and the lower limit voltage. On the other hand, when the output of the abnormality detection circuit 406 is at L level, no abnormality has occurred in either the upper limit voltage or the lower limit voltage. As described above, the abnormality detection circuit 406 of the first embodiment monitors the input voltage to the VCO 413. Whether or not an abnormality has occurred in the second clock signal can be determined based on whether the output level is H level or L level.

<Selection control circuit>
The selector 404 receives two clock signals, a clock signal (first clock signal) output from the internal oscillation circuit 401 and a clock signal (second clock signal) output from the PLL circuit 403. The selector 404 selects one of the two clock signals and outputs it as the system clock of the CPU core 405.

As described above, the selection control circuit 407 is for controlling the selection of the clock signal of the selector 404.
The selection control circuit 407 of the present embodiment controls the selector 404 to select the first clock signal when the power supply is activated (that is, when the power switch 81 is turned on).

  Thereafter, when the output of the abnormality detection circuit 406 is at L level (that is, when it is detected that no abnormality has occurred), the selection control circuit 407 has a timing according to the firmware setting (setting of the setting register 417). Thus, the selector 404 switches the selection so that the selector 404 selects the second clock signal.

  On the other hand, when the output of the abnormality detection circuit 406 is H level (that is, when it is detected that an abnormality has occurred), the selection control circuit 407 selects the selector regardless of the firmware setting (setting register 417 setting). The selection of 404 is not switched. That is, the selector 404 remains selected with the first clock signal and does not switch to the second clock signal.

  At this time, the status register 418 stores that the output of the abnormality detection circuit 406 is at the H level, and notifies the arithmetic circuit 415 that the system clock has not been switched by the selector 404. Thereby, the arithmetic circuit 415 performs, for example, a response corresponding to a case where the clock signal is not switched.

<Operation at startup>
The microcontroller 400 of this embodiment is provided with a flag (hereinafter referred to as a debug flag) indicating whether or not programming debugging is being performed. The abnormality detection circuit 406 is set to be effective only when the debug flag is set (in the on state). Debugging is an operation for finding and correcting errors such as bugs and defects in a computer program and making the operation conform to specifications. For example, when developing the device (printer 1), if the ratio of frequency division between the 1 / n divider circuit 410 and the 1 / m divider circuit (value of n and m) is wrong, the frequency becomes abnormally low or abnormal. The VCO 413 does not oscillate due to a high frequency, or the arithmetic circuit 415 subsequent to the PLL circuit 403 does not operate normally. If the selection of the selector 404 is switched to the output side of the PLL circuit 403 in this state, the debugging will be hung, and there is a possibility that the debugging operation cannot be performed thereafter. In addition, it takes time to notice this setting (setting of the values of n and m), and there is a possibility that the debugging efficiency is lowered. In the present embodiment, by checking the status register 418 at the time of debugging, an abnormality in the second clock signal can be easily noticed, and debugging efficiency can be improved.

FIG. 8 is a flowchart showing an example of the operation of the microcontroller 400 when the printer 1 is activated.
First, when the power is turned on (that is, the power switch 81 is turned on) (S101), the selection control circuit 407 of the microcontroller 400 causes the selector 404 to select the first clock signal (S102). That is, the first clock signal is supplied from the selector 404 to the CPU core 405 as the system clock.

Next, the microcontroller 400 determines whether or not a debug flag is set (S103). When the debug flag is not set (NO in S103), the microcontroller 400 disables the abnormality detection circuit 406 (S104), and the selection control circuit 407 sets the firmware (specifically, the setting register 417). Accordingly, the selection of the selector 404 is switched from the first clock signal to the second clock signal (S105).
On the other hand, if it is determined in step S103 that the debug flag is set (YES in S103), the microcontroller 400 enables the abnormality detection circuit 406 (S106) and determines whether or not an abnormality is detected (S107). ). If no abnormality is detected (NO in S107), specifically, if the output of the abnormality detection circuit 406 is at L level, step S105 is executed.

  When an abnormality is detected (YES in S107), specifically, when the output of the abnormality detection circuit 406 is at the H level, the selection control circuit 407 sends the first clock signal to the selector 404 regardless of the firmware setting. The switching from the second clock signal to the second clock signal is not executed (S108). Further, the status register 418 of the CPU core 405 stores that the output of the abnormality detection circuit 406 is at the H level (that is, the abnormality is detected in the second clock signal) (S109). Based on the information in the status register 418, the arithmetic circuit 415 recognizes that the first clock signal is not switched to the second clock signal. Then, the arithmetic circuit 415 performs a response in response to, for example, a case where the clock signal is not switched.

  As described above, in this embodiment, the abnormality detection circuit 406 is enabled only during programming debugging. This abnormality detection circuit 406 makes it easy to specify the cause of abnormality during debugging, and debugging efficiency can be improved.

  As described above, the microcontroller 400 according to the present embodiment is based on the arithmetic circuit 415 of the CPU core 405 that operates by being supplied with the clock signal, the internal oscillation circuit 401 that generates the first clock signal, and the reference clock. A PLL circuit 403 that generates a second clock signal, an abnormality detection circuit 406 that detects an abnormality of the second clock signal, and selects either the first clock signal or the second clock signal to be sent to the CPU core 405 as a system clock A selection circuit (a selector 404 and a selection control circuit 407) is provided.

  Then, the selection circuit selects the first clock signal as the system clock at the time of power activation, and switches from the first clock signal to the second clock signal according to the firmware setting when the abnormality detection circuit 406 detects no abnormality. ing. On the other hand, when an abnormality is detected by the abnormality detection circuit 406, switching from the first clock signal to the second clock signal is not performed regardless of the firmware setting. The status register 418 stores information indicating that an abnormality has been detected by the abnormality detection circuit 406 (in other words, information indicating that the clock signal has not been switched), and notifies the arithmetic circuit 415 of the information. .

  By doing so, for example, even when the second clock signal becomes an abnormal frequency due to a setting mistake in the value of n and the value of m during programming debugging, the first clock signal is changed to the second clock signal. Since switching is not performed, it is possible to reliably prevent malfunction. Further, by checking the status register 418, it can be recognized that the second clock signal is abnormal. For this reason, it becomes easy to identify the cause of abnormality during debugging, and debugging efficiency can be improved.

=== Second Embodiment ===
FIG. 9 is a block diagram showing the configuration of the microcontroller 400 in the second embodiment. In FIG. 8, the same components as those in the first embodiment (FIG. 6) are denoted by the same reference numerals and description thereof is omitted. The microcontroller 400 of the second embodiment has an abnormality detection circuit 406 ′. The output of the 1 / m frequency dividing circuit 414 (that is, the second lock signal) is input to the abnormality detection circuit 406 ′.

FIG. 10 is a block diagram illustrating an example of the configuration of the abnormality detection circuit 406 ′ in the second embodiment.
As shown in the figure, the abnormality detection circuit 406 ′ includes a D flop flop (D-FF) 431, a delay circuit 432, and a toggle operation confirmation circuit 433. These circuits constitute a logic circuit for monitoring the second clock signal.

The output of the delay circuit 432 is input to the D input of the D flip-flop 431. The output of the 1 / m frequency dividing circuit 414 (that is, the second clock signal) is input to CK. If the D input is “H level” when the second clock signal rises, the Q output becomes “H level” and / Q becomes “L level”. On the other hand, if the D input is “L level” when the second clock signal rises, the Q output becomes “L level” and / Q becomes 1 “H level”. This is a circuit that creates a delay of a predetermined time in transmission without changing the waveform.

  The toggle operation confirmation circuit 433 receives the output of the internal oscillation circuit 401 (that is, the first clock signal) and the output of the delay circuit 432. Then, the toggle operation confirmation circuit 433 detects whether the output of the delay circuit 432 is switched between the H level and the L level in the cycle of the first clock signal (whether the toggle operation is performed). For example, if one of the H level and L level continues as the second clock signal, it does not function as the system clock of the CPU core 405. Therefore, when the H level or the L level continues for a predetermined number of times, it can be detected that the second clock signal is abnormal. The toggle operation check circuit 433 outputs a signal indicating an abnormality (for example, an H level signal) when the output of the delay circuit 432 continues at H level or L level continuously in the cycle of the first clock signal. On the other hand, when the level is switched between the H level and the L level (when the toggle operation is confirmed), a signal indicating that no abnormality is detected (for example, an L level signal) is output. The output of the toggle operation confirmation circuit 433 becomes the output of the abnormality detection circuit 406 ′.

  Since the operation at the time of starting up the printer 1 is the same as that in the first embodiment (FIG. 8), the description thereof is omitted.

=== Other Embodiments ===
Although a printer or the like as one embodiment has been described, the above embodiment is for facilitating the understanding of the present invention, and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof. In particular, the embodiments described below are also included in the present invention.

<About the printer>
In the above-described embodiment, the printer is a lateral type printer, but is not limited thereto. For example, a transport operation for transporting the print medium in the transport direction, and a dot that forms dots on the print medium by ejecting ink from the nozzles of the head while moving the head in the movement direction (direction intersecting the transport direction) It may be a printer (so-called serial printer) that forms an image by repeating the forming operation. Further, for example, a printer (so-called line printer) that forms an image by discharging UV ink from a head provided on a transport path while transporting a print medium in the transport direction may be used.

<About nozzle>
In the above-described embodiment, ink is ejected using a piezoelectric element (piezo element). However, the method for discharging the liquid is not limited to this. For example, other methods such as a method of generating bubbles in the nozzle by heat may be used.

<Sub-board>
In the above-described embodiment, one sub-board corresponds to four ink cartridges (in other words, CSIC), but is not limited thereto. For example, it may correspond to three or less ink cartridges, or may correspond to five or more ink cartridges. Further, the number of sub-substrates (microcontrollers 400) may be two or more.

<About the abnormality detection circuit>
The configuration of the abnormality detection circuit 406 (406 ′) is not limited to the above-described embodiment, and any other configuration may be used as long as the abnormality of the second clock signal can be detected.

1 Printer, 2 Device body, 3 Ink cartridge holder unit,
10 Feeding unit, 18 winding shaft, 19 relay roller,
20 transport unit, 21 relay roller, 22 relay roller,
23 1st conveyance roller, 23a 1st drive roller, 23b 1st driven roller,
24 second conveying roller, 24a second driving roller, 24b second driven roller,
25 reverse roller, 26 relay roller, 27 feed roller, 29 platen,
30 head units, 31 heads, 34 valve units,
35 Cleaning unit, 40 Carriage unit, 41 Guide rail,
42 carriage, 50 detector groups, 60 controllers,
61 interface unit, 62 CPU, 63 memory, 64 unit control circuit,
70 winding unit, 71 relay roller, 72 winding drive shaft,
80 power supply unit, 81 power switch,
110 host computer, 200 main board, 300 sub board,
310 Cartridge holder, 330 External oscillation element,
400 microcontroller, 401 internal oscillation circuit, 402 inverter,
403 PLL circuit, 404 selector, 405 CPU core, 406 abnormality detection circuit,
407 selection control circuit, 410 1 / n frequency dividing circuit, 411 phase comparison circuit,
412 LPF, 413 VCO, 414 1 / m frequency divider,
415 arithmetic circuit, 416 storage circuit, 417 setting register,
418 Status register, 421 Upper limit voltage comparator,
422 Lower limit voltage comparator, 423 OR circuit, 431 D flip-flop,
432 delay circuit, 433 toggle operation confirmation circuit

Claims (7)

  1. An arithmetic circuit that operates by being supplied with a clock signal;
    An oscillation circuit for generating a first clock signal;
    A PLL circuit that generates a second clock signal based on a reference clock;
    An abnormality detection circuit for detecting an abnormality of the second clock signal;
    A selection circuit that selects one of the first clock signal and the second clock signal and supplies the selected one to the arithmetic circuit;
    Select the first clock signal at power-up,
    If no abnormality is detected by the abnormality detection circuit, the first clock signal is switched to the second clock signal according to the firmware setting,
    A selection circuit that does not switch from the first clock signal to the second clock signal regardless of the setting of the firmware when an abnormality is detected by the abnormality detection circuit;
    A status register that informs the arithmetic circuit that switching from the first clock signal to the second clock signal has not been performed when an abnormality is detected by the abnormality detection circuit;
    A microcontroller characterized by comprising
  2. The microcontroller of claim 1,
    The abnormality detection circuit detects the presence or absence of abnormality of the second clock signal by monitoring an input voltage to the voltage controlled oscillator of the PLL circuit;
    A microcontroller characterized by that.
  3. The microcontroller of claim 1,
    The abnormality detection circuit includes a monitoring logic circuit to which the second clock signal is input, and detects whether the second clock signal is abnormal based on whether the monitoring logic circuit operates normally. To
    A microcontroller characterized by that.
  4. The microcontroller according to any one of claims 1 to 3,
    Enable the abnormality detection circuit only when a debug flag indicating that an error occurred during the programming process of the microcontroller is on.
    A microcontroller characterized by that.
  5. A microcontroller according to any one of claims 1 to 4,
    Provided in an image forming apparatus for forming an image on a printing medium;
    A microcontroller characterized by that.
  6. The microcontroller according to claim 5, wherein
    The image forming apparatus includes:
    A main board,
    The main substrate is a position away from the predetermined distance, and the replaceable consumable of the image forming apparatus is a sub-board disposed at a position closer than the predetermined distance;
    Have
    A microcontroller provided on the sub-board.
  7. The microcontroller according to claim 6, wherein
    In response to an instruction from the main board, read / write data to / from a storage element provided in the consumable,
    A microcomputer controller characterized by that.
JP2011262479A 2011-11-30 2011-11-30 Micro-controller Withdrawn JP2013114589A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08235015A (en) * 1995-02-27 1996-09-13 Mitsubishi Electric Corp Processor device and processor fault diagnostic method
JP2001344039A (en) * 2000-03-31 2001-12-14 Seiko Epson Corp Information processor and method for controlling the same and control program of the same
JP2005332245A (en) * 2004-05-20 2005-12-02 Fujitsu Ltd Information processor, and medium storage device using the same
JP2007116627A (en) * 2005-10-24 2007-05-10 Canon Inc Image forming apparatus
JP2008153910A (en) * 2006-12-18 2008-07-03 Fujitsu Ltd System clock supplier, and frequency shift deciding method of reference oscillator
JP2010231330A (en) * 2009-03-26 2010-10-14 Denso Corp Microcomputer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08235015A (en) * 1995-02-27 1996-09-13 Mitsubishi Electric Corp Processor device and processor fault diagnostic method
JP2001344039A (en) * 2000-03-31 2001-12-14 Seiko Epson Corp Information processor and method for controlling the same and control program of the same
JP2005332245A (en) * 2004-05-20 2005-12-02 Fujitsu Ltd Information processor, and medium storage device using the same
JP2007116627A (en) * 2005-10-24 2007-05-10 Canon Inc Image forming apparatus
JP2008153910A (en) * 2006-12-18 2008-07-03 Fujitsu Ltd System clock supplier, and frequency shift deciding method of reference oscillator
JP2010231330A (en) * 2009-03-26 2010-10-14 Denso Corp Microcomputer

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