JP6135445B2 - Semiconductor integrated circuit and operation control method of semiconductor integrated circuit - Google Patents

Description

  The present disclosure relates to a semiconductor integrated circuit and an operation control method of the semiconductor integrated circuit.

  In recent years, counterfeit goods by dead copy of integrated circuits have been distributed. For example, obtaining a regular semiconductor device, extracting circuit information by analyzing the wiring and circuit element structure of each layer of the semiconductor device with an electron micrograph, and manufacturing a counterfeit semiconductor device based on the circuit information Can do. Such a counterfeit product is advantageous in price competition because it does not require development costs, and it takes away the share of the regular product.

JP 2006-5486 A JP 2009-284428 A

  In view of the above, there is a demand for a semiconductor integrated circuit in which a counterfeit product does not operate even if a counterfeit product is manufactured by analyzing the structure.

  A semiconductor integrated circuit includes an internal circuit and a ferroelectric capacitor, operates with a power supply voltage, and oscillates at an oscillation frequency according to a capacitance value of the ferroelectric capacitor and the power supply voltage, and the oscillation A frequency sensor that outputs a determination result obtained by determining a frequency value, and an operation control circuit that controls whether the internal circuit is operable according to the determination result when the power supply voltage is a predetermined voltage value; including.

  According to at least one embodiment, there is provided a semiconductor integrated circuit in which a counterfeit product does not operate even if a counterfeit product is manufactured by analyzing the structure.

It is a figure which shows the voltage dependence of the capacitance value of a capacitive element. It is a figure which shows an example of a structure of the oscillator containing a paraelectric capacitor. It is a figure which shows an example of the voltage dependence of the oscillation frequency of the oscillator shown in FIG. It is a figure which shows an example of a structure of the oscillator containing a ferroelectric capacitive element. FIG. 5 is a diagram illustrating an example of voltage dependency of an oscillation frequency of the oscillator illustrated in FIG. 4. It is a figure which shows an example of a structure of a semiconductor integrated circuit. It is a figure which shows the voltage dependence characteristic of the oscillation frequency of the oscillator which oscillates based on a ferroelectric capacitor element, and the voltage dependence characteristic of the oscillation frequency of the oscillator which oscillates based on a paraelectric capacitor element. It is a figure which shows an example of the operation | movement sequence at the time of power activation of a semiconductor integrated circuit. It is a figure which shows an example of the circuit structure of a voltage sensor. It is a figure which shows an example of the circuit structure of a frequency sensor. It is a figure which shows an example of a structure of a switched capacitor circuit. It is a figure which shows another example of a structure of a semiconductor integrated circuit. It is a figure which shows the voltage dependence characteristic of the oscillation frequency of the oscillator which oscillates based on a ferroelectric capacitor element, and the voltage dependence characteristic of the oscillation frequency of the oscillator which oscillates based on a paraelectric capacitor element. It is a figure which shows the voltage dependence characteristic of the oscillation frequency of the oscillator which oscillates based on a ferroelectric capacitor element, and the voltage dependence characteristic of the oscillation frequency of the oscillator which oscillates based on a paraelectric capacitor element. It is a figure which shows an example of the operation | movement sequence at the time of power activation of a semiconductor integrated circuit. It is a figure which shows another example of a structure of a semiconductor integrated circuit. It is a figure which shows an example of the operation | movement sequence at the time of power activation of a semiconductor integrated circuit. It is a figure which shows an example of a structure and operation | movement of a booster circuit. It is a figure which shows another example of a structure of a semiconductor integrated circuit. It is a figure which shows an example of the operation | movement sequence at the time of power activation of a semiconductor integrated circuit. It is a figure which shows another example of a structure of a semiconductor integrated circuit. It is a figure which shows an example of the operation | movement sequence at the time of power activation of a semiconductor integrated circuit. It is a figure which shows an example of a structure and operation | movement of a booster circuit. It is a figure which shows an example of the circuit structure of a voltage sensor. It is a figure which shows an example of the circuit structure of a frequency sensor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings used in the present application, the same or corresponding components are referred to by the same or corresponding numerals, and the description thereof will be omitted as appropriate.

  FIG. 1 is a diagram illustrating the voltage dependence of the capacitance value of the capacitive element. In FIG. 1, the horizontal axis indicates the voltage applied between the two electrodes of the capacitive element, and the vertical axis indicates the relative capacitance value. A characteristic curve 501 indicates the voltage dependency characteristic of the capacitance value of the paraelectric capacitor, and a characteristic curve 502 indicates the voltage dependency characteristic of the capacitance value of the ferroelectric capacitor. Each characteristic curve plots a value obtained by dividing the capacitance value at each voltage by the reference capacitance value, with the capacitance value at a voltage of 1.0 V as the reference capacitance value.

  As can be seen from FIG. 1, the capacitance value of the paraelectric capacitor is substantially constant regardless of the voltage value in the voltage range of 0.8V to 3.3V. On the other hand, the capacitance value of the ferroelectric capacitor element changes so that the capacitance value decreases as the voltage value increases in the voltage range of 0.8V to 3.3V.

  FIG. 2 is a diagram illustrating an example of a configuration of an oscillator including a paraelectric capacitor. The oscillator 10 shown in FIG. 2 includes inverters 11 to 13, a paraelectric capacitor 14, a paraelectric capacitor 15, and a resistor 16. The inverters 11 to 13 are connected in cascade, and the output of the last stage inverter 13 is connected to the input of the first stage inverter 11 via the resistance element 16. The output of the inverter 12 is connected to one end of the paraelectric capacitor 15. The other end of the paraelectric capacitor 15 is connected to the ground via the paraelectric capacitor 14. The inverters 11 to 13 operate with the power supply voltage VDD. That is, the amplitude of the signal output from the inverters 11 to 13 is an amplitude corresponding to the power supply voltage VDD.

  The time required for the output voltage of the inverter 12 to rise or fall and become higher or lower than the input threshold value of the inverter 13 at the next stage is the capacitance value of the paraelectric capacitor 15 (and the paraelectric capacitor 14). And depends on the power supply voltage VDD. Accordingly, the oscillator 10 oscillates at an oscillation frequency corresponding to the capacitance value of the paraelectric capacitor 15 and the power supply voltage VDD.

  FIG. 3 is a diagram illustrating an example of voltage dependency of the oscillation frequency of the oscillator illustrated in FIG. In FIG. 3, the horizontal axis represents the power supply voltage VDD, and the vertical axis represents the oscillation frequency of the oscillator 10. In the example shown in FIG. 3, as indicated by the characteristic curve 17, the oscillation frequency increases as the voltage increases in the voltage range of 0.5V to 2.5V, but the increase rate of the oscillation frequency decreases as the voltage increases. Thus, the oscillation frequency is substantially constant at a voltage of 1.5 V or more.

  FIG. 4 is a diagram illustrating an example of the configuration of an oscillator including a ferroelectric capacitor. The oscillator 20 shown in FIG. 4 includes inverters 21 to 23, a paraelectric capacitor 24, a ferroelectric capacitor 25, and a resistor 26. The inverters 21 to 23 are connected in cascade, and the output of the last stage inverter 23 is connected to the input of the first stage inverter 21 via the resistance element 26. The output of the inverter 22 is connected to one end of the ferroelectric capacitor 25. The other end of the ferroelectric capacitor 25 is connected to the ground via the paraelectric capacitor 24. The inverters 21 to 23 operate with the power supply voltage VDD. That is, the amplitude of the signal output from the inverters 21 to 23 is an amplitude corresponding to the power supply voltage VDD.

  The time required for the output voltage of the inverter 22 to rise or fall and become higher or lower than the input threshold value of the inverter 23 in the next stage is the capacitance value of the ferroelectric capacitor 25 (and the paraelectric capacitor 24). And depends on the power supply voltage VDD. Therefore, the oscillator 20 oscillates at an oscillation frequency corresponding to the capacitance value of the ferroelectric capacitor 25 and the power supply voltage VDD.

  FIG. 5 is a diagram showing an example of the voltage dependence of the oscillation frequency of the oscillator shown in FIG. In FIG. 5, the horizontal axis indicates the power supply voltage VDD, and the vertical axis indicates the oscillation frequency of the oscillator 20. In the example shown in FIG. 5, as indicated by the characteristic curve 27, the oscillation frequency of the oscillator 20 increases as the voltage increases in a voltage range of about 0.5 to 1.0 V, and from about 1.0 V to 1.V. In the voltage range of about 7V, the voltage drops as the voltage increases. Further, in the voltage range of about 1.7 V to 2.5 V, the oscillation frequency increases as the voltage increases. Since the capacitance value of the ferroelectric capacitive element 25 changes depending on the voltage applied to the capacitive element, the voltage dependence of the oscillation frequency shown in FIG. 5 uses the paraelectric capacitive element 15 shown in FIG. The oscillation frequency of the oscillator has completely different characteristics from the voltage dependency.

  FIG. 6 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit. A semiconductor integrated circuit 30 shown in FIG. 6 includes an oscillator 20, a voltage sensor 31, a frequency sensor 32, an IC reset generation circuit 33, and an internal circuit (logic unit). In FIG. 6 and subsequent figures, the boundary between each circuit or functional block shown in each box and another circuit or functional block basically indicates a functional boundary, and is a physical location. Separation, electrical signal separation, control logic separation, and the like. Each circuit or functional block may be one hardware module physically separated to some extent from another block, or one function in a hardware module physically integrated with another block May be shown.

  The oscillator 20 has the circuit configuration shown in FIG. 4, and may have, for example, voltage dependency of the oscillation frequency shown in FIG. The oscillator 20 includes a ferroelectric capacitor 25, operates at the power supply voltage VDD, and oscillates at an oscillation frequency corresponding to the capacitance value of the ferroelectric capacitor 25 and the power supply voltage VDD. The frequency sensor 32 outputs a frequency determination result FDET1 obtained by determining the value of the oscillation frequency of the oscillator 20. The IC reset generation circuit 33 controls the operation of the internal circuit 34 according to the frequency determination result FDET1 when the power supply voltage VDD is a predetermined voltage value.

  The internal circuit 34 is a circuit portion for executing main functions of the semiconductor integrated circuit 30. For example, if the semiconductor integrated circuit 30 is a circuit that provides predetermined data processing as a main function, the internal circuit 34 is a circuit portion that executes the data processing. In order to control whether the internal circuit 34 can operate, it is not essential to use a reset signal. For example, whether to operate the internal circuit 34 may be controlled by controlling on and off of the power supplied to the internal circuit 34.

  More specifically, the frequency sensor 32 receives the voltage detection result VDET1 of the voltage sensor 31, and determines whether or not the oscillation frequency of the oscillator 20 is equal to or higher than a predetermined threshold when the voltage detection result VDET1 is asserted. You may judge. Thereby, the frequency sensor 32 outputs the frequency determination result FDET1 when the power supply voltage VDD has a predetermined voltage value. For example, the frequency determination result FDET1 may be asserted when the oscillation frequency of the oscillator 20 is equal to or higher than a predetermined threshold, and may be negated in other cases. The frequency sensor 32 does not need to receive the voltage detection result VDET1 of the voltage sensor 31, and determines whether the oscillation frequency of the oscillator 20 is equal to or higher than a predetermined threshold regardless of the state of the voltage detection result VDET1. Good.

  The voltage sensor 31 receives the power supply voltage VDD, asserts the voltage detection result VDET1 when the power supply voltage VDD is a predetermined voltage value, and negates the voltage detection result VDET1 when the power supply voltage VDD is other than the predetermined voltage value. It may be in a state. Here, the predetermined voltage value may be a specific voltage value (for example, 1.8 V), or a specific voltage value that allows a certain variation range (for example, ± 0.2 V) (for example, 1.8 V). It may be. In the latter case, the voltage detection result VDET1 is asserted only when the power supply voltage VDD exists within a range near a specific voltage value (for example, a range of 1.6 V to 2.0 V).

  The IC reset generation circuit 33 controls the operation of the internal circuit 34 according to the value of the frequency determination result FDET1 when the voltage detection result VDET1 is asserted. For example, the IC reset generation circuit 33 receives the frequency determination result FDET1 that is obtained when the oscillator 20 includes the ferroelectric capacitor 25 under the condition that the power supply voltage VDD is a predetermined voltage value. RESET may be negated to release the reset. In response to the release of the asserted state of the reset signal RESET (release of the reset state), the internal circuit 34 may start operation. The IC reset generation circuit 33 asserts the reset signal RESET when the frequency determination result FDET1 that is obtained when the oscillator 20 includes the ferroelectric capacitor 25 is not supplied under the condition that the power supply voltage VDD is a predetermined voltage value. The state may be maintained (reset state is maintained). When the asserted state of the reset signal RESET is maintained, the internal circuit 34 cannot start operation.

  FIG. 7 is a diagram showing a voltage dependency characteristic of the oscillation frequency of the oscillator 20 that oscillates based on the ferroelectric capacitor element 25 and a voltage dependency characteristic of the oscillation frequency of the oscillator that oscillates based on the paraelectric capacitor element. In FIG. 7, a characteristic curve 37 is a curve showing the voltage dependence characteristic of the oscillation frequency of the oscillator 20 provided in the semiconductor integrated circuit 30. A characteristic curve 36 has the same circuit configuration as that of the oscillator 20, but shows a voltage dependence characteristic of the oscillation frequency of an oscillator in which the ferroelectric capacitor 25 is replaced by a paraelectric capacitor 15 having the same size. It is. That is, when the semiconductor integrated circuit 30 is reverse-engineered to manufacture the same circuit, the oscillation frequency of the oscillator corresponding to the oscillator 20 in the semiconductor integrated circuit manufactured by replacing the ferroelectric capacitor with a paraelectric capacitor. Has the characteristic shown in the characteristic curve 36 of FIG. In the example shown in FIG. 7, the characteristic curve 37 is the same as the characteristic curve 27 shown in FIG.

  As can be seen by comparing the characteristic curve 36 and the characteristic curve 37 in FIG. 7, for example, the oscillation frequency is completely different at a point where the power supply voltage VDD is 1.8V. In the case of an oscillator that oscillates based on a paraelectric capacitor, the oscillation frequency is 170 MHz or more in the vicinity of the power supply voltage 1.8 V, as shown by the characteristic curve 36. On the other hand, in the case of the oscillator 20 that oscillates based on the ferroelectric capacitor 25, the oscillation frequency is 5.0 MHz in the vicinity of the power supply voltage 1.8V, as shown by the characteristic curve 36 (or the characteristic curve 27 in FIG. 5). It is as follows.

  Therefore, by determining whether or not the oscillation frequency is 5.0 MHz or less in the vicinity of the power supply voltage 1.8V (for example, the power supply voltage VDD is in the range of 1.7V to 1.9V), the semiconductor integrated circuit 30 It can be determined whether or not it is a counterfeit product. When the oscillation frequency is 5.0 MHz or higher, it is determined that the product is a counterfeit product, and the IC reset generation circuit 33 maintains the reset signal RESET (maintains the reset state). Thereby, it is possible to prevent the circuit of the imitation product from operating. Note that a semiconductor device including a ferroelectric capacitor cannot be manufactured in a factory that manufactures a semiconductor by a normal semiconductor process. In order to manufacture a semiconductor device including a ferroelectric capacitor element, it is necessary to make a large investment and to provide necessary facilities, and such a semiconductor device cannot be easily manufactured.

  FIG. 8 is a diagram illustrating an example of an operation sequence when the semiconductor integrated circuit 30 is turned on. 8 and the subsequent drawings, the execution order of each step described in the flowchart is merely an example, and the technical scope intended by the present application is not limited to the described execution order. For example, even if it is described in the present application that the B step is executed after the A step, it is not only possible to execute the B step after the A step, but also the A step after the B step. It may be physically and logically possible to perform. In this case, if all the results affecting the processing of the flowchart are the same regardless of the order in which the steps are executed, for the purpose of the technique disclosed in the present application, the A step is followed by the B step. It is obvious that may be executed. Even if it is described in the present application that the B step is executed after the A step, it is not intended to exclude the obvious case as described above from the technical scope intended by the present application. The obvious case naturally falls within the technical scope intended by the present application.

  In step S1 of FIG. 8, the power supply of the semiconductor integrated circuit 30 is turned on. At this time, the power supply voltage VDD applied to the semiconductor integrated circuit 30 is, for example, 1.8V. In step S2, the voltage sensor 31 determines the power supply voltage VDD. The voltage sensor 31 asserts the voltage detection result VDET1 when the power supply voltage VDD is in the range of 1.7V to 1.9V, and negates the voltage detection result VDET1 when the power supply voltage VDD is in the other range. To. When the power supply voltage VDD is not in the range of 1.7V to 1.9V, step S2 is repeated until the power supply voltage VDD is in the range of 1.7V to 1.9V.

  When the power supply voltage VDD is in the range of 1.7V to 1.9V, the process proceeds to step S3, and the frequency sensor 32 determines the oscillation frequency of the oscillator 20. The frequency sensor 32 asserts the frequency determination result FDET1 when the oscillation frequency of the oscillator 20 is, for example, 5.0 MHz or less, and sets the frequency determination result FDET1 to the negated state when the oscillation frequency of the oscillator 20 is higher than 5.0 MHz. To do.

  When the frequency determination result FDET1 is in the negated state, the process proceeds to step S4, and the IC reset generation circuit 33 does not release the reset state by maintaining the reset signal asserted state. When the frequency determination result FDET1 is in the asserted state, the process proceeds to step S5, where the IC reset generation circuit 33 negates the reset signal to cancel the reset state.

  FIG. 9 is a diagram illustrating an example of a circuit configuration of the voltage sensor. The voltage sensor shown in FIG. 9 includes a bias circuit 40, a voltage dividing circuit 41, a BGR (Band Gap Reference) circuit 42, and a comparator circuit 43. The bias circuit 40 includes a PMOS transistor 44 and a resistance element 45. The voltage dividing circuit 41 includes resistance elements 46 and 47.

  The bias circuit 40 generates a predetermined bias voltage and applies the bias voltage to the comparator circuit 43. The voltage dividing circuit 41 divides the power supply voltage VDD according to the resistance values of the resistance elements 46 and 47 and applies the divided voltage to the inverting input of the comparator circuit 43. The BGR circuit 42 generates a reference potential having a constant voltage (for example, 1.21 V) regardless of the power supply voltage VDD, and applies the generated reference potential to the non-inverting input of the comparator circuit 43. The comparator circuit 43 generates a HIGH output when the divided voltage is lower than the reference potential, and generates a LOW output when the divided voltage is higher than the reference potential. The output of the comparator circuit 43 can be used as the voltage determination result VDET.

  The voltage sensor circuit of FIG. 9 is a circuit in which the voltage determination result VDET changes from HIGH to LOW when the power supply voltage rises above a predetermined voltage value. If another voltage sensor having the same configuration as that shown in FIG. 9 is provided and the resistance values of the resistance elements 46 and 47 of the voltage dividing circuit 41 are different from those of the voltage sensor shown in FIG. A power supply voltage different from the voltage sensor shown can be detected.

  For example, the voltage sensor shown in FIG. 9 is HIGH when the voltage voltage VDD is equal to or lower than the first voltage (eg, 1.7 V), and becomes LOW when the voltage voltage VDD is higher than the first voltage. A voltage determination result VDET is generated. Further, the second voltage determination is performed by another voltage sensor, which is HIGH when the voltage voltage VDD is equal to or lower than the second voltage (for example, 1.9 V) and becomes LOW when the voltage voltage VDD is higher than the second voltage. Result VDET is generated. If the AND logic of the inverted value of the first voltage determination result VDET generated in this way and the second voltage determination result VDET is obtained, the output of the AND logic is that the power supply voltage VDD is in the range of 1.7V to 1.9V. Only the signal becomes HIGH. The signal thus generated can be used as the voltage determination result VDET1 that is the output of the voltage sensor 31 shown in FIG.

  FIG. 10 is a diagram illustrating an example of a circuit configuration of the frequency sensor. The frequency sensor 32 illustrated in FIG. 10 includes a bias circuit 50, a low-pass filter 51, a voltage dividing circuit 52, a switched capacitor circuit (SW_CAP) 53, and a comparator circuit 54. The bias circuit 50 includes a PMOS transistor 55 and a resistance element 56. The low pass filter 51 includes a resistance element 57 and a capacitance element 58. Voltage dividing circuit 52 includes resistance elements 59 and 60.

  FIG. 11 is a diagram illustrating an example of the configuration of the switched capacitor circuit 53. The switched capacitor circuit 53 includes PMOS transistors 61 and 62, NMOS transistors 63 and 64, an inverter 65, a capacitive element 66, and a resistive element 67. The transfer gate composed of the PMOS transistor 61 and the NMOS transistor 63 and the transfer gate composed of the PMOS transistor 62 and the NMOS transistor 64 are alternately conducted according to the clock signal CLK. As a result, the capacitive element 66 is repeatedly charged and discharged, and a voltage corresponding to the frequency of the clock signal CLK is generated as the output SO. An oscillation signal of the oscillator 20 shown in FIG. 6 is applied as the clock signal CLK.

  The bias circuit 50 generates a predetermined bias voltage and applies the bias voltage to the comparator circuit 54. The low-pass filter 51 removes a high-frequency component of the output SO of the switched capacitor circuit 53 to generate a signal having a substantially constant voltage value corresponding to the oscillation frequency of the oscillator 20. Apply to inverting input. The voltage dividing circuit 52 divides the power supply voltage VDD according to the resistance values of the resistance elements 59 and 60, and applies the divided voltage to the inverting input of the comparator circuit 54. The comparator circuit 54 receives the voltage determination result VDET (VDET1 in the example of FIG. 6) as an enable signal, and may operate only when the voltage determination result VDET is in an asserted state (for example, HIGH). The comparator circuit 54 generates a HIGH output when a signal having a voltage value corresponding to the oscillation frequency of the oscillator 20 is higher than the divided voltage, and a signal having a voltage value corresponding to the oscillation frequency of the oscillator 20 is generated after the voltage division. A LOW output is generated when the voltage is equal to or lower than the voltage of the first voltage. The output of the comparator circuit 43 can be used as the frequency determination result FDET.

  The frequency sensor shown in FIG. 10 is LOW when the oscillation frequency of the oscillator 20 is equal to or lower than a predetermined frequency (for example, 5.0 MHz), and becomes HIGH when the oscillation frequency of the oscillator 20 becomes higher than the predetermined frequency. Generate FDET. This frequency determination result FDET may be used as the frequency determination result FDET1 shown in FIG.

  FIG. 12 is a diagram illustrating another example of the configuration of the semiconductor integrated circuit. A semiconductor integrated circuit 30A shown in FIG. 12 includes an oscillator 20, voltage sensors 31A and 31B, frequency sensors 32A and 32B, an IC reset generation circuit 33A, and an internal circuit (logic unit) 34.

  The oscillator 20 has the circuit configuration shown in FIG. 4, and may have, for example, voltage dependency of the oscillation frequency shown in FIG. The oscillator 20 includes a ferroelectric capacitor 25, operates at the power supply voltage VDD, and oscillates at an oscillation frequency corresponding to the capacitance value of the ferroelectric capacitor 25 and the power supply voltage VDD. The frequency sensors 32A and 32B output frequency determination results FDET1 and FDET2 obtained by determining the value of the oscillation frequency of the oscillator 20. The IC reset generation circuit 33A controls the operation of the internal circuit 34 according to the frequency determination results FDET1 and FDET2 when the power supply voltage VDD is a predetermined voltage value.

  More specifically, the predetermined voltage value is at least two different voltage values, and the frequency determination results are at least two different frequency determination results FDET1 and FDET2. The IC reset generation circuit 33A controls the operation of the internal circuit 34 according to at least two different frequency determination results FDET1 and FDET2 in the case where the power supply voltage VDD has the at least two different voltage values.

  In the semiconductor integrated circuit 30A of FIG. 12, the at least two different voltage values are obtained by changing the power supply voltage VDD with time. Specifically, the externally applied power supply voltage VDD is temporally changed for the semiconductor integrated circuit 30A.

  The voltage sensor 31A asserts the voltage determination result VDET1 when the power supply voltage VDD is in the range of, for example, 0.9V to 1.1V, and negates the voltage determination result VDET1 otherwise. The voltage sensor 31B asserts the voltage determination result VDET2 when the power supply voltage VDD is in the range of 1.7 V to 1.9 V, for example, and negates the voltage determination result VDET2 otherwise. The voltage sensors 31A and 31B may have a circuit configuration similar to that of the voltage sensor 31 in the semiconductor integrated circuit 30 illustrated in FIG.

  For example, the frequency sensor 32A determines whether or not the oscillation frequency of the oscillator 20 is 5 MHz or higher when the power supply voltage VDD is in a range of 0.9 V to 1.1 V, for example, and a frequency determination indicating a result of the determination. The result FDET1 is output. For example, the frequency sensor 32B determines whether or not the oscillation frequency of the oscillator 20 is 4.5 MHz or less when the power supply voltage VDD is in a range of 1.7 V to 1.9 V, for example, and indicates the result of the determination. The frequency determination result FDET2 is output. The frequency sensors 32A and 32B may have the same circuit configuration as the frequency sensor 32 in the semiconductor integrated circuit 30 shown in FIG.

  FIG. 13 is a diagram showing a voltage dependency characteristic of the oscillation frequency of the oscillator 20 that oscillates based on the ferroelectric capacitor 25 and a voltage dependency characteristic of the oscillation frequency of the oscillator that oscillates based on the paraelectric capacitor element. In FIG. 13, a characteristic curve 71 is a curve showing the voltage dependence characteristic of the oscillation frequency of the oscillator 20 provided in the semiconductor integrated circuit 30A. The characteristic curve 72 has the same circuit configuration as that of the oscillator 20, but is a curve showing the voltage dependence characteristics of the oscillation frequency of the oscillator in which the ferroelectric capacitor 25 is replaced by a paraelectric capacitor. This oscillator using a paraelectric capacitor is designed to oscillate at substantially the same oscillation frequency as that of the oscillator 20 using the ferroelectric capacitor 25 when the power supply voltage VDD is in the vicinity of 1.8V. ing. However, when the power supply voltage VDD is in the vicinity of 1.0 V, the oscillation frequency indicated by the characteristic curve 71 and the oscillation frequency indicated by the characteristic curve 72 are greatly different. Therefore, even if there is no difference in the oscillation frequency between the genuine product and the imitation product when the power supply voltage VDD is in the vicinity of 1.8V, if the oscillation frequency is determined in the vicinity of the power supply voltage VDD of 1.0V, the imitation product is imitated. The product can be distinguished from the product.

  FIG. 14 is a diagram illustrating a voltage dependence characteristic of the oscillation frequency of the oscillator 20 that oscillates based on the ferroelectric capacitor 25 and a voltage dependence characteristic of the oscillation frequency of the oscillator that oscillates based on the paraelectric capacitor. In FIG. 14, a characteristic curve 71 is a curve showing the voltage dependence characteristic of the oscillation frequency of the oscillator 20 provided in the semiconductor integrated circuit 30A. The characteristic curve 73 has the same circuit configuration as that of the oscillator 20, but is a curve showing the voltage dependence characteristics of the oscillation frequency of an oscillator in which the ferroelectric capacitor 25 is replaced by a paraelectric capacitor. This oscillator using a paraelectric capacitor is designed to oscillate at substantially the same oscillation frequency as that of the oscillator 20 using the ferroelectric capacitor 25 when the power supply voltage VDD is in the vicinity of 1.0V. ing. However, when the power supply voltage VDD is in the vicinity of 1.8 V, the oscillation frequency indicated by the characteristic curve 71 and the oscillation frequency indicated by the characteristic curve 73 are greatly different. Therefore, even if there is no difference in oscillation frequency between the regular product and the imitation product when the power supply voltage VDD is near 1.0 V, if the oscillation frequency is determined in the vicinity of the power supply voltage VDD of 1.8 V, the imitation product is imitated. The product can be distinguished from the product.

  FIG. 15 is a diagram illustrating an example of an operation sequence when the semiconductor integrated circuit 30A is powered on. In step S10, the power supply of the semiconductor integrated circuit 30A is turned on. At this time, the power supply voltage VDD applied to the semiconductor integrated circuit 30A is, for example, 1.0V. In step S11, the voltage sensor 31A determines the power supply voltage VDD. The voltage sensor 31A asserts the voltage detection result VDET1 when the power supply voltage VDD is in the range of 0.9V to 1.1V, and negates the voltage detection result VDET1 when the power supply voltage VDD is in the other range. To. When the power supply voltage VDD is not in the range of 0.9V to 1.1V, step S11 is repeated until the power supply voltage VDD is in the range of 0.9V to 1.1V.

  When the power supply voltage VDD is in the range of 0.9V to 1.1V, the process proceeds to step S12, and the frequency sensor 32A determines the oscillation frequency of the oscillator 20. The frequency sensor 32A asserts the frequency determination result FDET1 when the oscillation frequency of the oscillator 20 is, for example, 5.0 MHz or more, and sets the frequency determination result FDET1 to the negated state when the oscillation frequency of the oscillator 20 is lower than 5.0 MHz. To do.

  When the frequency determination result FDET1 is in the negated state, the process proceeds to step S13, and the IC reset generation circuit 33A does not cancel the reset state by maintaining the asserted state of the reset signal. When the frequency determination result FDET1 is asserted, the process proceeds to step S14.

  In step S14, the power supply voltage VDD applied from the outside to the semiconductor integrated circuit 30A is increased. The power supply voltage VDD applied to the semiconductor integrated circuit 30A after the rise is, for example, 1.8V. In step S15, the voltage sensor 31B determines the power supply voltage VDD. The voltage sensor 31B asserts the voltage detection result VDET2 when the power supply voltage VDD is in the range of 1.7V to 1.9V, and negates the voltage detection result VDET2 when the power supply voltage VDD is in the other range. To. When the power supply voltage VDD is not in the range of 1.7V to 1.9V, step S15 is repeated until the power supply voltage VDD is in the range of 1.7V to 1.9V.

  When the power supply voltage VDD is in the range of 1.7V to 1.9V, the process proceeds to step S16, and the frequency sensor 32B determines the oscillation frequency of the oscillator 20. The frequency sensor 32B asserts the frequency determination result FDET2 when the oscillation frequency of the oscillator 20 is 4.5 MHz or less, for example, and sets the frequency determination result FDET2 to the negated state when the oscillation frequency of the oscillator 20 is higher than 4.5 MHz. To do.

  When the frequency determination result FDET2 is in the negated state, the process proceeds to step S17, and the IC reset generation circuit 33A does not release the reset state by maintaining the asserted state of the reset signal. When the frequency determination result FDET2 is in the asserted state, the process proceeds to step S18, and the IC reset generating circuit 33A negates the reset signal to cancel the reset state.

  FIG. 16 is a diagram illustrating still another example of the configuration of the semiconductor integrated circuit. In FIG. 16, the same or corresponding elements as those of FIG. 12 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. A semiconductor integrated circuit 30B shown in FIG. 16 includes oscillators 20A and 20B, voltage sensors 31A and 31B, frequency sensors 32A and 32B, an IC reset generation circuit 33B, an internal circuit (logic unit) 34, and a booster circuit 81.

  Each of the oscillators 20A and 20B has the circuit configuration shown in FIG. 4, and may have, for example, voltage dependency of the oscillation frequency shown in FIG. The booster circuit 81 functions as a voltage generation circuit that generates a second power supply voltage VDC having a voltage value different from that of the first power supply voltage VDD based on the first power supply voltage VDD. The oscillator 20A operates with the first power supply voltage VDD. The oscillator 20B operates with the second power supply voltage VDC. The frequency sensor 32A outputs a frequency determination result FDET1 obtained by determining the value of the oscillation frequency of the oscillator 20A. The frequency sensor 32B outputs a frequency determination result FDET2 obtained by determining the value of the oscillation frequency of the oscillator 20B. Further, the IC reset generation circuit 33B controls whether the internal circuit 34 can operate according to the frequency determination results FDET1 and FDET2 when the power supply voltage is a predetermined voltage value.

  More specifically, the predetermined voltage value is at least two different voltage values, and the frequency determination results are at least two different frequency determination results FDET1 and FDET2. The at least two different voltage values are a voltage value of the first power supply voltage VDD and a voltage value of the second power supply voltage VDC.

  The voltage sensor 31A asserts the voltage determination result VDET1 when the power supply voltage VDD is in the range of, for example, 0.9V to 1.1V, and negates the voltage determination result VDET1 otherwise. The voltage sensor 31B asserts the voltage determination result VDET2 when the power supply voltage VDD is in the range of, for example, 1.8V to 2.2V, and negates the voltage determination result VDET2 otherwise. The voltage sensors 31A and 31B may have a circuit configuration similar to that of the voltage sensor 31 in the semiconductor integrated circuit 30 illustrated in FIG.

  For example, the frequency sensor 32A determines whether or not the oscillation frequency of the oscillator 20 is 5 MHz or higher when the power supply voltage VDD is in a range of 0.9 V to 1.1 V, for example, and a frequency determination indicating a result of the determination. The result FDET1 is output. For example, the frequency sensor 32B determines whether or not the oscillation frequency of the oscillator 20 is 4.5 MHz or less when the power supply voltage VDD is in the range of 1.8 V to 2.2 V, for example, and indicates the result of the determination. The frequency determination result FDET2 is output. The frequency sensors 32A and 32B may have the same circuit configuration as the frequency sensor 32 in the semiconductor integrated circuit 30 shown in FIG.

  FIG. 17 is a diagram illustrating an example of an operation sequence at the time of power-on of the semiconductor integrated circuit 30B. In step S20, the power supply of the semiconductor integrated circuit 30B is turned on. At this time, the power supply voltage VDD applied to the semiconductor integrated circuit 30B is, for example, 1.0V. When the power is turned on in step S20, the process of step S21 and the process of step S24 are executed in parallel.

  In step S21, the voltage sensor 31A determines the power supply voltage VDD. The voltage sensor 31A asserts the voltage detection result VDET1 when the power supply voltage VDD is in the range of 0.9V to 1.1V, and negates the voltage detection result VDET1 when the power supply voltage VDD is in the other range. To. When the power supply voltage VDD is not in the range of 0.9V to 1.1V, step S21 is repeated until the power supply voltage VDD is in the range of 0.9V to 1.1V.

  When the power supply voltage VDD falls within the range of 0.9V to 1.1V, the process proceeds to step S22, and the frequency sensor 32A determines the oscillation frequency of the oscillator 20A. The frequency sensor 32A asserts the frequency determination result FDET1 when the oscillation frequency of the oscillator 20A is, for example, 5.0 MHz or more, and sets the frequency determination result FDET1 to the negated state when the oscillation frequency of the oscillator 20A is lower than 5.0 MHz. To do.

  When the frequency determination result FDET1 is in the negated state, the process proceeds to step S23, and the IC reset generation circuit 33A does not release the reset state by maintaining the reset signal asserted state. When the frequency determination result FDET1 is in the asserted state, the process proceeds to step S28.

  In step S24 executed in parallel with step S21, the booster circuit 81 boosts the power supply voltage VDD twice to generate the power supply voltage VDC. After boosting, the power supply voltage VDC is 2.0V, for example. In step S25, the voltage sensor 31B determines the power supply voltage VDC. The voltage sensor 31B asserts the voltage detection result VDET2 when the power supply voltage VDC is in the range of 1.8V to 2.2V, and negates the voltage detection result VDET2 when the power supply voltage VDC is in the other range. To. When the power supply voltage VDC is not in the range of 1.8V to 2.2V, step S25 is repeated until the power supply voltage VDC is in the range of 1.8V to 2.2V.

  When the power supply voltage VDC is in the range of 1.8V to 2.2V, the process proceeds to step S26, and the frequency sensor 32B determines the oscillation frequency of the oscillator 20B. The frequency sensor 32B asserts the frequency determination result FDET2 when the oscillation frequency of the oscillator 20B is 4.5 MHz or less, for example, and sets the frequency determination result FDET2 to the negated state when the oscillation frequency of the oscillator 20B is higher than 4.5 MHz. To do.

  When the frequency determination result FDET2 is in the negated state, the process proceeds to step S27, and the IC reset generation circuit 33A does not release the reset state by maintaining the reset signal asserted state. When the frequency determination result FDET2 is asserted, the process proceeds to step S28.

  In step S28, the IC reset generation circuit 33B negates the reset signal to cancel the reset state. That is, the power supply voltage VDD is in the range of 0.9V to 1.1V, the power supply voltage VDC is in the range of 1.8V to 2.2V, and both the frequency determination result FDET1 and the frequency determination result FDET2 are both. When asserted, the reset state is released.

  FIG. 18 is a diagram illustrating an example of the configuration and operation of the booster circuit 81. As illustrated in FIG. 18A or 18B, the booster circuit 81 includes switch circuits S1 to S3 and capacitive elements C1 and C2. The switch circuits S1 to S3 may be controlled by, for example, a clock signal generated by an oscillator having the same configuration as the oscillator 10 shown in FIG. As shown in FIG. 18A, in the first period, the switch circuits S1 and S3 are turned on and off, respectively, and the switch circuit S2 is connected to the ground potential VSS side. Further, as shown in FIG. 18B, in the second period, the switch circuits S1 and S3 are turned off and turned on, and the switch circuit S2 is connected to the power supply potential VDD side. The first period and the second period appear alternately in synchronization with the clock signal.

  In the first period, the capacitive element C1 is charged, and the voltage between the terminals of the capacitive element C1 becomes the voltage VDD. In the second period, the terminal of the capacitor C1 connected to the VSS (= 0V) side during the first period is connected to VDD. As a result, in the second period, the potential of the other terminal of the capacitor C1 is 2 × VDD. Therefore, a voltage twice as high as VDD is applied between both terminals of the capacitive element C2, the capacitive element C2 is charged, and the voltage between the terminals of the capacitive element C2 becomes twice as high as the voltage VDD. Thereby, the booster circuit 81 generates a voltage VDC having a voltage value that is twice the power supply voltage VDD.

  FIG. 19 is a diagram showing still another example of the configuration of the semiconductor integrated circuit. 19, the same or corresponding elements as those of FIG. 12 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. A semiconductor integrated circuit 30C shown in FIG. 19 includes oscillators 10 and 20, voltage sensors 31A and 31B, frequency sensors 32A and 32B, an IC reset generation circuit 33C, and an internal circuit (logic unit) 34.

  The oscillator 10 has the circuit configuration shown in FIG. 2, and may have voltage dependency of the oscillation frequency shown in FIG. 3, for example. The oscillator 10 includes a paraelectric capacitor 15, operates at the power supply voltage VDD, and oscillates at an oscillation frequency corresponding to the capacitance value of the paraelectric capacitor 15 and the power supply voltage VDD. The oscillator 20 has the circuit configuration shown in FIG. 4, and may have, for example, voltage dependency of the oscillation frequency shown in FIG. The oscillator 20 includes a ferroelectric capacitor 25, operates at the power supply voltage VDD, and oscillates at an oscillation frequency corresponding to the capacitance value of the ferroelectric capacitor 25 and the power supply voltage VDD.

  The frequency sensor 32A outputs a frequency determination result FDET1 obtained by determining the value of the oscillation frequency of the oscillator 20. The frequency sensor 32B outputs a frequency determination result FDET2 obtained by determining the value of the oscillation frequency of the oscillator 10. The IC reset generation circuit 33C controls the operation of the internal circuit 34 according to the frequency determination results FDET1 and FDET2 when the power supply voltage is a predetermined voltage value.

  More specifically, the predetermined voltage value is at least two different voltage values obtained by temporally changing the power supply voltage VDD. Further, the IC reset generation circuit 33C controls whether the internal circuit 34 can operate according to the frequency determination result FDET1 and the frequency determination result FDET2 at each of the at least two different voltage values.

  The voltage sensor 31A asserts the voltage determination result VDET1 when the power supply voltage VDD is in the range of, for example, 0.9V to 1.1V, and negates the voltage determination result VDET1 otherwise. The voltage sensor 31B asserts the voltage determination result VDET2 when the power supply voltage VDD is in the range of 1.7 V to 1.9 V, for example, and negates the voltage determination result VDET2 otherwise. The voltage sensors 31A and 31B may have a circuit configuration similar to that of the voltage sensor 31 in the semiconductor integrated circuit 30 illustrated in FIG.

  The frequency sensor 32A determines whether or not the oscillation frequency of the oscillator 20 is in the vicinity of 5.7 MHz (for example, within ± 0.2 MHz) when the power supply voltage VDD is in the range of 0.9 V to 1.1 V, for example. A frequency determination result FDET1 indicating the determination result is output. The frequency sensor 32A determines whether or not the oscillation frequency of the oscillator 20 is in the vicinity of 4.0 MHz (for example, within ± 0.2 MHz) when the power supply voltage VDD is outside the range of 0.9V to 1.1V. A frequency determination result FDET1 indicating the determination result is output. In any determination, the frequency determination result may be HIGH, for example, when the determination result is affirmative, and the frequency determination result may be LOW, when the determination result is negative.

  The frequency sensor 32B determines whether or not the oscillation frequency of the oscillator 10 is in the vicinity of 4.0 MHz (for example, within ± 0.2 MHz) when the power supply voltage VDD is in a range of 1.7 V to 1.9 V, for example. The frequency determination result FDET2 indicating the determination result is output. The frequency sensor 32B determines whether or not the oscillation frequency of the oscillator 10 is in the vicinity of 5.7 MHz (for example, within ± 0.2 MHz) when the power supply voltage VDD is outside the range of 1.7 V to 1.9 V. The frequency determination result FDET2 indicating the determination result is output. In any determination, the frequency determination result may be HIGH, for example, when the determination result is affirmative, and the frequency determination result may be LOW, when the determination result is negative.

  The IC reset generation circuit 33C compares the oscillation frequency of the oscillator 10 with the oscillation frequency of the oscillator 20 when the power supply voltage VDD is in the range of 0.9 V to 1.1 V, for example. Specifically, the IC reset generation circuit 33C may compare the frequency determination result FDET1 and the frequency determination result FDET2 instead of comparing the oscillation frequencies as they are. The IC reset generation circuit 33C further compares the oscillation frequency of the oscillator 10 with the oscillation frequency of the oscillator 20 when the power supply voltage VDD is in the range of 1.7 V to 1.9 V, for example. Specifically, the IC reset generation circuit 33C may compare the frequency determination result FDET1 and the frequency determination result FDET2 instead of comparing the oscillation frequencies as they are.

  When the oscillator 10 has the voltage dependence characteristic of the oscillation frequency shown in FIG. 3 and the oscillator 20 has the voltage dependence characteristic of the oscillation frequency shown in FIG. 5, the power supply voltage VDD is in the range of 0.9V to 1.1V. The frequency determination results FDET1 and FDET2 are HIGH and LOW, respectively. In addition, when the power supply voltage VDD is in the range of 1.7V to 1.9V, both the frequency determination results FDET1 and FDET2 are HIGH. As described above, the semiconductor integrated circuit 30C is designed such that one of two different voltage values (or voltage ranges) has the same two oscillation frequencies, and the other has the two oscillation frequencies different from each other. .

  When the same circuit is manufactured by reverse engineering the semiconductor integrated circuit 30C, when the ferroelectric capacitor is replaced with a paraelectric capacitor, the two oscillators corresponding to the oscillators 10 and 20 have their oscillation frequencies. The voltage dependency characteristics are the same. Therefore, if two oscillation frequencies are the same in one of two different voltage values (or voltage ranges), the two oscillation frequencies are also the same in the other. For example, when the frequency determination results FDET1 and FDET2 are both HIGH in the range of the power supply voltage VDD of 1.7V to 1.9V, the frequency determination results FDET1 and FDET2 are in the range of the power supply voltage VDD of 0.9V to 1.1V. Both should be LOW.

  FIG. 20 is a diagram illustrating an example of an operation sequence when the semiconductor integrated circuit 30C is powered on. In step S30, the power supply of the semiconductor integrated circuit 30C is turned on. At this time, the power supply voltage VDD applied to the semiconductor integrated circuit 30C is, for example, 1.0V.

  In step S31, the voltage sensor 31A determines the power supply voltage VDD. The voltage sensor 31A asserts the voltage detection result VDET1 when the power supply voltage VDD is in the range of 0.9V to 1.1V, and negates the voltage detection result VDET1 when the power supply voltage VDD is in the other range. To. When the power supply voltage VDD is not in the range of 0.9V to 1.1V, step S31 is repeated until the power supply voltage VDD is in the range of 0.9V to 1.1V.

  When the power supply voltage VDD is in the range of 0.9V to 1.1V, the process proceeds to step S32, and the frequency sensors 32A and 32B determine the oscillation frequencies of the oscillators 20 and 10, respectively. Based on the frequency determination results FDET1 and FDET2 output from the frequency sensors 32A and 32B, the IC reset generation circuit 33C determines whether or not the oscillation frequencies of the two oscillators match.

  In step S33, the power supply voltage VDD applied from the outside to the semiconductor integrated circuit 30C is increased. The power supply voltage VDD applied to the semiconductor integrated circuit 30C after the rise is, for example, 1.8V. In step S34, the voltage sensor 31B determines the power supply voltage VDD. The voltage sensor 31B asserts the voltage detection result VDET2 when the power supply voltage VDD is in the range of 1.7V to 1.9V, and negates the voltage detection result VDET2 when the power supply voltage VDD is in the other range. To. When the power supply voltage VDD is not in the range of 1.7V to 1.9V, step S34 is repeated until the power supply voltage VDD is in the range of 1.7V to 1.9V.

  When the power supply voltage VDD is in the range of 1.7V to 1.9V, the process proceeds to step S35, and the frequency sensors 32A and 32B determine the oscillation frequencies of the oscillators 20 and 10, respectively. Based on the frequency determination results FDET1 and FDET2 output from the frequency sensors 32A and 32B, the IC reset generation circuit 33C determines whether or not the oscillation frequencies of the two oscillators match.

  In step S36, whether the IC reset generation circuit 33C satisfies the condition that the two oscillation frequencies coincide in one of the two voltage ranges and the two oscillation frequencies differ in the other of the two voltage ranges. Determine whether or not. If this condition is not satisfied, the IC reset generation circuit 33C does not cancel the reset state by maintaining the reset signal asserted state in step S37. If the above condition is satisfied, the process proceeds to step S38.

  In step S38, the IC reset generation circuit 33C negates the reset signal to cancel the reset state. That is, when the two oscillation frequencies coincide with each other in one of the two voltage ranges and the two oscillation frequencies are different from each other in the other of the two voltage ranges, the reset state is released.

  FIG. 21 is a diagram showing still another example of the configuration of the semiconductor integrated circuit. A semiconductor integrated circuit 30D shown in FIG. 21 includes an oscillator 20, an IC reset generation circuit 33D, an internal circuit (logic unit) 34, a booster circuit 82, a voltage sensor 83, and a frequency sensor 84.

  The oscillator 20 has the circuit configuration shown in FIG. 4, and may have, for example, voltage dependency of the oscillation frequency shown in FIG. The frequency sensor 84 outputs a frequency determination result FDET obtained by determining the value of the oscillation frequency of the oscillator 20. The IC reset generation circuit 33D controls the operation of the internal circuit 34 according to the frequency determination result FDET when the power supply voltage VDC is a predetermined voltage value.

  More specifically, the frequency sensor 84 receives the voltage detection result VDET of the voltage sensor 83, and determines the magnitude relationship between the oscillation frequency of the oscillator 20 and a predetermined threshold when the voltage detection result VDET is in an asserted state. It's okay. As a result, the frequency sensor 84 outputs the frequency determination result FDET when the power supply voltage VDC is a predetermined voltage value.

  The voltage sensor 31 receives the power supply voltage VDC, asserts the voltage detection result VDET when the power supply voltage VDC is a predetermined voltage value, and negates the voltage detection result VDET when the power supply voltage VDC is other than the predetermined voltage value. It may be in a state. Here, the predetermined voltage value may be a specific voltage value (for example, 1.8 V), or a specific voltage value that allows a certain variation range (for example, ± 0.2 V) (for example, 1.8 V). It may be.

  The predetermined voltage value may be at least two different voltage values. That is, the voltage sensor 31 is, for example, a range in the vicinity of the first voltage value (for example, a range of 0.9 V to 1.1 V) or a range in the vicinity of the second voltage value (for example, a range of 1.8 V to 2.2 V). The voltage detection result VDET may be set to the asserted state only when the power supply voltage VDC exists in (). Which range of the power supply voltage VDC in the range near the first voltage value and the range near the second voltage value is detected may be controlled by the control signal MD1 from the IC reset generation circuit 33D. Further, the frequency sensor 84 determines the frequency using different threshold values for the range in the vicinity of the first voltage value and the range in the vicinity of the second voltage value based on the control signal MD1 from the IC reset generation circuit 33D. Operation may be performed.

  The booster circuit 81 functions as a voltage generation circuit that generates a power supply voltage VDC based on an external input voltage VDD. The booster circuit 81 may generate at least two different voltage values as predetermined voltage values of the power supply voltage VDC by temporally changing the power supply voltage VDC.

  The IC reset generation circuit 33D controls the operation of the internal circuit 34 according to the value of the frequency determination result FDET when the voltage detection result VDET is in the asserted state. This frequency determination result FDET may be at least two different determination results. The IC reset generation circuit 33D may control whether the internal circuit 34 can operate according to at least two different determination results in the case where the power supply voltage VDC has the above-described at least two different voltage values. For example, the first frequency determination result when the power supply voltage VDC is in the range of 0.9V to 1.1V, and the second frequency determination result when the power supply voltage VDC is in the range of 1.8V to 2.2V. Based on the above, the IC reset generation circuit 33D may control whether the internal circuit 34 can operate.

  FIG. 22 is a diagram illustrating an example of an operation sequence when the semiconductor integrated circuit 30D is powered on. In step S40, the power supply of the semiconductor integrated circuit 30D is turned on. At this time, the power supply voltage VDD applied to the semiconductor integrated circuit 30D is, for example, 1.0V. At this time, the control signal MD1 output from the IC reset generation circuit 33D is LOW.

  In step S41, the booster circuit 82 generates the power supply voltage VDC based on the power supply voltage VDD. In this case, the booster circuit 82 outputs the input voltage VDD of 1.0 V as it is as the power supply voltage VDC of 1.0 V without executing the boosting operation.

  In step S42, the voltage sensor 83 determines the power supply voltage VDC. When the control signal MD1 is LOW, the voltage sensor 83 asserts the voltage detection result VDET when the power supply voltage VDC is in the range of 0.9V to 1.1V, and the power supply voltage VDC is in the other range. The voltage detection result VDET is negated. When the power supply voltage VDC is not in the range of 0.9V to 1.1V, step S42 is repeated until the power supply voltage VDC is in the range of 0.9V to 1.1V.

  When the power supply voltage VDC is in the range of 0.9 V to 1.1 V, the process proceeds to step S43, and the frequency sensor 84 determines the oscillation frequency of the oscillator 20. When the control signal MD1 is LOW, the frequency sensor 84 asserts the frequency determination result FDET when the oscillation frequency of the oscillator 20 is 5.0 MHz or more, and when the oscillation frequency of the oscillator 20 is lower than 5.0 MHz. The frequency determination result FDET is negated.

  When the frequency determination result FDET is in the negated state, the process proceeds to step S44, and the IC reset generation circuit 33D does not release the reset state by maintaining the asserted state of the reset signal. When the frequency determination result FDET is in the asserted state, the process proceeds to step S45.

  In step S45, the IC reset generation circuit 33D changes the control signal MD1 from LOW to HIGH. As a result, the voltage value of the power supply voltage VDC is changed, and the voltage detection range of the voltage sensor 83 and the frequency determination level of the frequency sensor 84 are changed.

  In step S46, the booster circuit 82 boosts the power supply voltage VDD twice to generate the power supply voltage VDC. After boosting, the power supply voltage VDC is 2.0V, for example. In step S47, the voltage sensor 83 determines the power supply voltage VDC. When the control signal MD1 is HIGH, the voltage sensor 83 asserts the voltage detection result VDET when the power supply voltage VDC is in the range of 1.8V to 2.2V, and the power supply voltage VDC is in the other range. The voltage detection result VDET is negated. When the power supply voltage VDC is not in the range of 1.8V to 2.2V, step S47 is repeated until the power supply voltage VDC is in the range of 1.8V to 2.2V.

  When the power supply voltage VDC is in the range of 1.8V to 2.2V, the process proceeds to step S48, and the frequency sensor 84 determines the oscillation frequency of the oscillator 20. When the control signal MD1 is HIGH, the frequency sensor 84 asserts the frequency determination result FDET when the oscillation frequency of the oscillator 20 is 4.5 MHz or less, and when the oscillation frequency of the oscillator 20 is higher than 4.5 MHz. The frequency determination result FDET is negated.

  When the frequency determination result FDET is in the negated state, the process proceeds to step S49, and the IC reset generation circuit 33D does not release the reset state by maintaining the reset signal asserted state. When the frequency determination result FDET is in the asserted state, the process proceeds to step S50.

  In step S50, the IC reset generation circuit 33D negates the reset signal to cancel the reset state. That is, the frequency determination result FDET is in the asserted state when the power supply voltage VDC is in the range of 0.9V to 1.1V, and the frequency determination result FDET is in the asserted state when the power supply voltage VDC is in the range of 1.8V to 2.2V. At some point, the reset state is released.

  FIG. 23 is a diagram illustrating an example of the configuration and operation of the booster circuit 82. Similarly to the booster circuit 81 shown in FIGS. 18A and 18B, the booster circuit 82 includes switch circuits S1 to S3 and capacitive elements C1 and C2. In the booster circuit 82, as with the booster circuit 81, the switch circuits S1 to S3 may be controlled by a clock signal generated by an oscillator having the same configuration as that of the oscillator 10 shown in FIG. However, in the case of the booster circuit 82, unlike the booster circuit 81, the operations of the switch circuits S1 to S3 are also controlled by the control signal MD1 from the IC reset generation circuit 33D.

  FIG. 23A shows the operation of the switch circuits S1 to S3 when the control signal MD1 is LOW. When the control signal MD1 is LOW, both the switch circuits S1 and S3 are conductive, and the switch circuit S2 is connected to the power supply potential VDD side. As a result, the input voltage VDD is output as it is as the power supply voltage VDC.

  FIGS. 23B and 23C show the operation of the switch circuits S1 to S3 when the control signal MD1 is HIGH. When the control signal MD1 is HIGH, the connection states of the switch circuits S1 to S3 are switched in synchronization with the clock signal. The boosting operation of the booster circuit 82 shown in FIGS. 23B and 23C is the same as that of the booster circuit 81 shown in FIGS. 18A and 18B, and the description thereof is omitted.

  FIG. 24 is a diagram illustrating an example of a circuit configuration of the voltage sensor. 24, the same or corresponding elements as those of FIG. 9 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. The voltage sensor shown in FIG. 24 is different from the voltage sensor shown in FIG. 9 in that a resistance element 91 and a PMOS transistor 92 are provided. When the control signal MD1 is LOW, the PMOS transistor 92 is turned on, and the circuit detects the same voltage value as the voltage sensor shown in FIG. When the control signal MD1 is HIGH, the PMOS transistor 92 is turned off, and as a result, the resistance element 91 is added in series with the resistance elements 46 and 47. As a result, the voltage value applied to the inverting input of the comparator circuit 43 (the voltage value generated by the voltage dividing circuit 41) changes, and the circuit detects a voltage value different from that of the voltage sensor shown in FIG. Based on the same principle, the voltage sensor 83 can also change the voltage range to be detected by changing the voltage generated by the voltage dividing circuit in accordance with the control signal MD1.

  FIG. 25 is a diagram illustrating an example of a circuit configuration of the frequency sensor. 25, the same or corresponding elements as those of FIG. 10 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. The frequency sensor shown in FIG. 25 is different from the frequency sensor shown in FIG. 10 in that a resistance element 93 and a PMOS transistor 94 are provided. When the control signal MD1 is LOW, the PMOS transistor 94 is turned on, and the circuit detects the same frequency as the frequency sensor shown in FIG. When the control signal MD1 is HIGH, the PMOS transistor 94 becomes non-conductive, and as a result, the resistance element 93 is added in series with the resistance elements 59 and 60. As a result, the voltage value applied to the inverting input of the comparator circuit 54 (the voltage value generated by the voltage dividing circuit 52) changes, and the circuit detects a frequency different from that of the frequency sensor shown in FIG. In this way, in the frequency sensor 84, the frequency to be detected can be changed by changing the voltage generated by the voltage dividing circuit in accordance with the control signal MD1.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

DESCRIPTION OF SYMBOLS 10 Oscillator 20 Oscillator 31, 31A, 31B Voltage sensor 32, 32A, 32B Frequency sensor 33, 33A, 33B, 33C, 33D IC reset generation circuit 34 Internal circuit 81 Boost circuit 82 Boost circuit 83 Voltage sensor 84 Frequency sensor

Claims (9)

Internal circuitry,
An oscillator that includes a ferroelectric capacitor, operates at a power supply voltage, and oscillates at an oscillation frequency according to a capacitance value of the ferroelectric capacitor and the power supply voltage;
A frequency sensor that outputs a determination result obtained by determining the value of the oscillation frequency;
A semiconductor integrated circuit including an operation control circuit that controls whether or not the internal circuit operates according to the determination result when the power supply voltage is a predetermined voltage value;   The predetermined voltage value is at least two different voltage values, the determination result is at least two different determination results, and the operation control circuit has each of the case where the power supply voltage is the at least two different voltage values. The semiconductor integrated circuit according to claim 1, wherein whether or not the internal circuit is operable is controlled according to the at least two different determination results.   The semiconductor integrated circuit according to claim 2, wherein the at least two different voltage values are obtained by temporally changing the power supply voltage. A voltage generation circuit for generating a second power supply voltage having a voltage value different from the first power supply voltage based on the first power supply voltage;
The oscillator is
A first oscillator operating at the first power supply voltage;
A second oscillator operating at the second power supply voltage,
The frequency sensor is
A first frequency sensor for outputting a first determination result obtained by determining a value of an oscillation frequency of the first oscillator;
A second frequency sensor that outputs a second determination result obtained by determining a value of an oscillation frequency of the second oscillator,
The at least two different voltage values are the first power supply voltage and the second power supply voltage, and the at least two different determination results are the first determination result and the second determination result. Item 3. A semiconductor integrated circuit according to Item 2. A paraelectric capacitor, further including an oscillator that operates at the power supply voltage and oscillates at an oscillation frequency according to a capacitance value of the paraelectric capacitor and the power supply voltage;
The frequency sensor is
A first frequency sensor that outputs a first determination result obtained by determining a value of an oscillation frequency of the oscillator including the ferroelectric capacitor;
A second frequency sensor that outputs a second determination result obtained by determining a value of an oscillation frequency of the oscillator including the paraelectric capacitor,
The predetermined voltage value is at least two different voltage values obtained by temporally changing the power supply voltage, and the operation control circuit performs the first determination at each of the at least two different voltage values. 2. The semiconductor integrated circuit according to claim 1, wherein whether or not the internal circuit is operable is controlled according to a result and the second determination result. A voltage generation circuit for generating the power supply voltage based on an external input voltage;
The voltage generation circuit generates at least two different voltage values as the predetermined voltage value of the power supply voltage by temporally changing the power supply voltage,
The determination result is at least two different determination results, and the operation control circuit is configured to change the internal circuit according to the at least two different determination results in the case where the power supply voltage is the at least two different voltage values. 2. The semiconductor integrated circuit according to claim 1, which controls whether or not the operation is possible. Oscillate an oscillator that oscillates at an oscillation frequency according to the capacitance value of the ferroelectric capacitor and the power supply voltage,
Obtain a determination result obtained by determining the value of the oscillation frequency,
A method of controlling an operation of a semiconductor integrated circuit, comprising the steps of controlling whether or not an internal circuit can operate according to the determination result when the power supply voltage is a predetermined voltage value. The predetermined voltage value is at least two different voltage values, and the determination result is at least two different determination results;
The step of controlling whether or not the operation can be performed controls whether or not the internal circuit can operate according to the at least two different determination results in the case where the power supply voltage has the at least two different voltage values, respectively. 8. An operation control method for a semiconductor integrated circuit according to item 7. Generating the at least two different voltage values by varying the power supply voltage over time;
Oscillating the oscillator comprises oscillating the oscillator at at least two different oscillation frequencies based on the at least two different voltage values;
9. The operation control method for a semiconductor integrated circuit according to claim 8, wherein the step of obtaining the determination result determines values of the at least two different oscillation frequencies to generate the at least two different determination results.

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