JP2009253729A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mechanism which can control a power supply voltage of a logic circuit having a delay function by directly utilizing a signal detected from the logic circuit. <P>SOLUTION: The invention relates to a semiconductor integrated circuit device including a logic circuit, a delay characteristic detection circuit which outputs a detection signal of a frequency according to a change in delay of the logic circuit, a resistive element having a resistance value changing according to the detection signal, a reference voltage generating circuit which outputs a reference voltage according to a change in the resistance value of the resistive element, and a voltage supply circuit which outputs the reference voltage to the logic circuit and the delay characteristic detection circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a power supply voltage generation circuit.

  In semiconductor integrated circuit devices such as ICs and LSIs, logic circuits in the devices have variations in delay time. For this reason, for example, when performing in-phase transfer between flip-flops, it is necessary to ensure normal operation for the path with the maximum delay time and the path with the minimum delay time of the logic circuit. Thus, the variation in the delay time of the circuit becomes a restriction on the design of the apparatus. In recent years, with the progress of the manufacturing process of semiconductor integrated circuits, the variation in characteristics of miniaturized semiconductors has increased. Along with this variation, the variation in delay time is also increasing, and the above problems are becoming more serious.

  A technique for ensuring such variations in circuit delay time is disclosed in Patent Document 1. FIG. 7 shows a configuration of the integrated circuit device 1 disclosed in Patent Document 1. As shown in FIG. 7, the integrated circuit 1 includes a counter 2, a comparator 3, a latch circuit 4, an integrator 5, a voltage control circuit 6, an integrated circuit 7, and an output transistor Q8. The integrated circuit 7 has a ring oscillator 9. The voltage control circuit 6 is a differential amplifier, and includes transistors Q11 to Q13 and resistance elements R11 and R12. A node between the resistor element R12 and the transistor Q12 is connected to the base of the output transistor Q8.

The integrated circuit device 1 detects the delay of the integrated circuit 7 with the ring oscillator 9. The detection result is compared with a reference value by the counter 2 and the comparator 3. The comparison result is sent to the voltage control circuit 6 and the power supply voltage supplied to the integrated circuit 7 is changed. The delay time is adjusted by changing the voltage.
JP 60-1111528 A

  In the technique of Patent Document 1, the output of the ring oscillator 9 for detecting the delay is once put in the counter 2 and further processed by the latch circuit 4 and the integrator 5, and then the power supply voltage of the integrated circuit 7 is controlled. Therefore, the technology of Patent Decentralization 1 has problems such as a very complicated circuit configuration for adjusting the delay time and a large circuit scale. Therefore, in order to reduce the circuit scale, there is a demand for a mechanism that controls the power supply voltage by directly using the signal detected from the ring oscillator 9.

  The present invention includes a logic circuit, a delay characteristic detection circuit that outputs a detection signal having a frequency corresponding to a change in delay of the logic circuit, a first resistance element whose resistance value changes in accordance with the detection signal, The semiconductor integrated circuit device includes a reference voltage generation circuit that outputs a reference voltage according to a change in the resistance value of the resistance element, and a voltage supply circuit that outputs the reference voltage to the logic circuit and the delay characteristic detection circuit.

  According to the present invention, the resistance value of the first resistance element can be changed using the detection signal whose frequency changes in accordance with the change in the delay of the logic circuit, and the reference voltage is changed by the change in the resistance value. be able to.

  According to the present invention, it is possible to reduce the size of a circuit for delay control of a logic circuit.

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows an example of the configuration of a semiconductor integrated circuit device according to this embodiment. As shown in FIG. 1, the semiconductor integrated circuit device 100 includes a logic circuit 110, an amplifier 120, resistance elements R1 to R3, and a switched capacitor SC1. The logic circuit 110 has a ring oscillator 130 inside.

  The resistance elements R1 and R2 are connected in series between the power supply voltage terminal VDD and the ground voltage terminal GND. Resistance elements R1 and R2 are connected at node A. The resistor element R3 has one terminal connected to the node A and the other terminal connected to the switched capacitor SC1. This resistance element R3 gives an offset to the resistance of a switched capacitor SC1 to be described later. However, if it is not necessary to add an offset, the resistance element R3 may be reduced. A capacitive element C2 is connected between the node A and the ground voltage terminal GND. The capacitive element C2 has a role of a low-pass filter that prevents a high-frequency signal component from entering the input terminal of the amplifier 120.

  For convenience, the symbol “R1” or the like of the resistance element indicates the resistance element name and also indicates the resistance value of the resistance element. The power supply voltage terminal VDD supplies the power supply voltage VDD, and the ground voltage terminal GND supplies the ground voltage GND.

  FIG. 2 shows the configuration of the switched capacitor SC1. As shown in FIG. 2, the switched capacitor SC1 includes a PMOS transistor Tr1, an NMOS transistor Tr2, and a capacitive element C1. The PMOS transistor Tr1 and the NMOS transistor Tr2 constitute an inverter. The PMOS transistor Tr1 has a source connected to the resistor element R3 and a drain connected to the node B. The NMOS transistor Tr2 has a source connected to the ground voltage terminal GND and a drain connected to the node B. An output signal Sosc from a ring oscillator 130 described later is input to the gates of the PMOS transistor Tr1 and the NMOS transistor Tr2. Capacitance element C1 has one terminal connected to node B and the other terminal connected to ground voltage terminal GND. Hereinafter, the source of the PMOS transistor Tr1 is the a terminal of the switched capacitor SC1, the gates of the PMOS transistor Tr1 and the NMOS transistor Tr2 are the b terminal, and the source of the NMOS transistor Tr2 is the c terminal.

  The amplifier 120 includes a differential amplifier 140 and an output transistor Tr3. The differential amplifier 140 has one input terminal connected to the node A, the other terminal connected to the node C, and an output terminal connected to the base of the output transistor Tr3. Here, the differential amplifier 140 may have a generally known general configuration. For example, the same configuration as that of the voltage control circuit 6 described in the related art may be used. Since the operation and the like of such a differential amplifier are known, the description thereof is omitted.

  The output transistor Tr3 has a collector connected to the power supply voltage terminal VDD, an emitter connected to the node C, and a base connected to the output terminal of the differential amplifier 140. The voltage at the node C is fed back to the differential amplifier 140. Therefore, the differential amplifier 140 compares the potentials of the nodes A and C and adjusts the output voltage Vout of the output transistor Tr3 based on the comparison result. For example, when the voltage at the node A increases, the output voltage Vout also increases, and when the voltage decreases, the output voltage Vout also decreases. This output voltage Vout, that is, the voltage at the node C is supplied to the logic circuit 110.

  The logic circuit 110 performs a predetermined logic operation with the voltage Vout supplied from the node C which is a power supply node. As described above, the logic circuit 110 includes the ring oscillator 130. An example of the configuration of the ring oscillator 130 is shown in FIG. As shown in FIG. 3, the ring oscillator 130 connects the odd-numbered inverters Iv <b> 1 to Ivn in a ring shape. Therefore, it oscillates at a period corresponding to the delay time of the circuit on this annular signal propagation path. The ring oscillator 130 also operates with the voltage Vout supplied from the node C. Therefore, ring oscillator 130 outputs a signal having an oscillation period corresponding to voltage Vout supplied from node C to switched capacitor SC1. Therefore, for example, when the voltage Vout decreases, the delay time of the combinational circuit group constituting the ring oscillator 130 increases, and the oscillation frequency decreases. On the contrary, when the voltage Vout increases, the delay time of the combinational circuit group constituting the ring oscillator 130 is reduced, and the oscillation frequency is increased.

  Here, the ring oscillator 130 is configured inside the logic circuit 110 that performs a predetermined logic operation. For this reason, the ambient temperature, power supply voltage, etc. of the logic circuit 110 can be made common. Further, since the manufacturing variation in the manufacturing process is also common, the ring oscillator 130 also has a delay variation similar to the delay variation of the circuit group constituting the logic circuit 110. Therefore, there is a strong correlation between the delay time of the logic circuit 110 and the delay time of the ring oscillator 130 in the logic circuit 110. Therefore, the delay time of the logic circuit 110 can be indirectly monitored by monitoring the oscillation frequency of the signal Sosc output from the ring oscillator 130.

  Next, the operation of the semiconductor integrated circuit device 100 according to the present embodiment will be described below. First, the operation of the switched capacitor SC1 will be described. Switched capacitor SC1 operates as a variable resistor whose resistance value decreases in proportion to the frequency of output signal Sosc from ring oscillator 130. The operation will be described below. Here, the frequency of the output signal Sosc of the ring oscillator 130 is fosc, the capacitance of the capacitive element C1 is Csc, and the voltage at the terminal a is Va.

First, when a low potential level signal is input to the terminal b, the PMOS transistor Tr1 is turned on and the NMOS transistor Tr2 is turned off. Therefore, the voltage Va is supplied to the other terminal of the capacitive element C1 connected to the node B. For this reason, the charge according to the voltage Va is charged in the capacitive element C1. Conversely, when a high potential level signal is input to the terminal b, the PMOS transistor Tr1 is turned off and the NMOS transistor Tr2 is turned on. Therefore, the ground voltage GND is supplied to the other terminal of the capacitive element C1 connected to the node B. For this reason, the capacitive element C1 is discharged. As described above, when the output signal Sosc of the ring oscillator 130 is input to the terminal b, the PMOS transistor Tr1 and the NMOS transistor Tr2 are alternately turned on and off in response to the output signal Sosc. Thereby, the capacitive element C1 also repeats charging / discharging. Here, if the capacitive element C1 is completely charged / discharged by turning on / off the PMOS transistor Tr1 and the NMOS transistor Tr2, the charge of Csc × Va flows from the terminal a of the switched capacitor SC1 to the terminal c. This operation is repeated fosc times per second. Therefore, a charge of fosc × Csc × Va flows through the switched capacitor SC1 per second. This is the same as a current of fosc × Csc × Va [A] flowing through the switched capacitor SC1. Therefore, this switched capacitor SC1 can be regarded as a resistance element having a resistance value represented by the following formula (1).

式（２）に式（１）を代入すると、式（３）となる。

この式（３）において、抵抗値Ｒ１〜Ｒ３、容量Ｃｓｃ、電源電圧ＶＤＤは固定値である。よって、変数である周波数ｆｏｓｃが高くなるにつれノードＡの電圧Ｖｒｅｆが減少することがわかる。反対に周波数ｆｏｓｃが低くなるにつれノードＡの電圧Ｖｒｅｆが増加する。このような電圧Ｖｒｅｆが差動増幅器１４０の一方の入力端子に入力される。よって、これに合わせ、アンプ１２０の出力電圧であるノードＣの電圧Ｖｏｕｔも変化する。 Next, the voltage Vref of the node A is obtained using the resistance value Rsc of the switched capacitor SC1. First, the combined resistance R3 + Rsc of the resistance element R3 and the resistance Rsc of the switched capacitor SC1 is in parallel with the resistance element R2. Further, a combined resistance of these resistance elements R2, R3, and Rsc is connected in series with the resistance element R1 between the power supply voltage VDD and the ground voltage. Therefore, the voltage Vref at the node A is a voltage obtained by dividing the power supply voltage VDD by the resistance element R1 and the combined resistance of the resistance elements R2, R3, and Rsc. The following equation (2) shows the voltage Vref of the node A.

Substituting equation (1) into equation (2) yields equation (3).

In this equation (3), the resistance values R1 to R3, the capacitance Csc, and the power supply voltage VDD are fixed values. Therefore, it can be seen that the voltage Vref at the node A decreases as the variable frequency fosc increases. On the contrary, the voltage Vref of the node A increases as the frequency fosc decreases. Such a voltage Vref is input to one input terminal of the differential amplifier 140. Accordingly, the voltage Vout at the node C, which is the output voltage of the amplifier 120, also changes accordingly.

  Here, as described above, the frequency fosc of the output signal Sosc of the ring oscillator 130 changes according to the voltage Vout. Therefore, the relationship between the frequency fosc and the change in the voltage at the node C due to the above operation will be described with reference to FIG. FIG. 5 shows changes over time in the frequency fosc of the output signal Sosc of the ring oscillator 130, the resistance value Rsc of the switched capacitor SC1, the voltage Vref of the node A, and the voltage Vout of the node C. A diagram schematically showing the waveform of the output signal Sosc of the ring oscillator 130 is shown above the frequency fosc.

  As shown in FIG. 5, first, at time t1, the output voltage Vout from the amplifier 120 is high and the delay of the ring oscillator 130 is small, so the frequency fosc is high. For this reason, in the period T1, since the frequency fosc is high, the resistance value Rsc of the switched capacitor SC1 decreases. Further, as the resistance value Rsc decreases, the voltage Vref at the node A also decreases. As a result, the voltage Vout at the node C decreases following the decrease in the voltage Vref.

  When the voltage Vout decreases, the delay of the ring oscillator 130 that operates using the voltage Vout as a power supply voltage increases, and the oscillation frequency fosc begins to decrease. For this reason, the resistance value Rsc of the switched capacitor SC1 also starts to rise. For this reason, the voltage Vref similarly starts to rise. As a result, the voltage Vout at the node C starts to rise following the voltage Vref.

  In the period T2, since the frequency fosc decreases, the resistance value Rsc of the switched capacitor SC1 increases. Furthermore, as the resistance value Rsc increases, the voltage Vref at the node A also increases. As a result, the voltage Vout at the node C rises following the rise in the voltage Vref.

  When the voltage Vout increases, the delay of the ring oscillator 130 that operates using the voltage Vout as a power supply voltage decreases, and the oscillation frequency fosc begins to increase. For this reason, the resistance value Rsc of the switched capacitor SC1 also starts to drop. Similarly, the voltage Vref starts to drop. As a result, the voltage Vout at the node C starts to drop following the voltage Vref.

  Thereafter, the same operation is performed, and eventually the voltage Vout converges to a voltage at which the ring oscillator 130 operates with a predetermined delay time. By operating the logic circuit 110 with such a voltage Vout, variation in delay time in the circuit is reduced, and stable circuit operation can be ensured. Furthermore, in order to secure an operation margin of the circuit, it is not necessary to supply more voltage than necessary to the logic circuit 110, and power consumption can be reduced.

  A simple graph of the change of the amplitude of the voltage Vout with time is shown in FIG. Here, the increase in the amplitude at time t2 shown in FIG. 6 indicates a case where the ambient temperature of the logic circuit 110 changes and the delay time of the logic circuit 110 changes again, for example. In this manner, the delay of the logic circuit 110 and the ring oscillator 130 also changes depending on changes in the surrounding conditions such as temperature. However, even in such a case, in the semiconductor integrated circuit device 100 of the present embodiment, the voltage Vout is controlled by the above-described operation in accordance with the change in the surrounding state such as the temperature. For this reason, the variation in delay time in the circuit is reduced by the voltage Vout according to the change in the surrounding situation, and stable circuit operation can be ensured.

  With the configuration and operation as described above, the semiconductor integrated circuit device 100 according to the present embodiment controls the voltage Vout by applying feedback to the amplifier 120 in accordance with the change in the frequency of the output signal Sosc due to the voltage Vout. . For this feedback, a change in the resistance value of the switched capacitor SC1 according to a change in the frequency fosc of the output signal Sosc is used. By such feedback control, the delay time of the logic circuit 110 is always kept within a predetermined operation margin, variation can be reduced, and stable circuit operation can be performed. Therefore, in the circuit configuration of the semiconductor integrated circuit device 100 according to the present embodiment, the feedback loop is directly used by using the output signal Sosc from the ring oscillator in the logic circuit without using the counter and the integrator as in the prior art. Can be controlled inside. As a result, the circuit scale can be reduced as compared with the prior art while maintaining the same effect as the prior art, and accordingly, the circuit manufacturing cost can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the configuration described above, the ring oscillator 130 functions independently to monitor the delay of the logic circuit 110 and generate the output signal Sosc. However, here, a circuit that is directly used in the logic operation of the logic circuit 110 may be used to generate and output a signal whose frequency changes due to a change in delay.

1 is an example of a configuration of a semiconductor integrated circuit device according to an embodiment; It is an example of the structure of the switched capacitor concerning embodiment. It is an example of the structure of the ring oscillator concerning embodiment. It is a characteristic view of the resistance value of the switched capacitor concerning an embodiment. It is an output characteristic of each part of the semiconductor integrated circuit device concerning an embodiment. It is the output voltage characteristic of the amplifier concerning embodiment. This is a configuration of a conventional semiconductor integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit device 110 Logic circuit 120 Amplifier 130 Ring oscillator 140 Differential amplifier R1-R3 Resistance element Tr1-Tr3 Transistor SC1 Switched capacitor C1 Capacitance element Iv1-Ivn Inverter

Claims (6)

Logic circuit;
A delay characteristic detection circuit that outputs a detection signal having a frequency corresponding to a change in delay of the logic circuit;
A first resistance element whose resistance value changes according to the detection signal;
A reference voltage generation circuit that outputs a reference voltage according to a change in the resistance value of the resistance element;
A voltage supply circuit for outputting the reference voltage to the logic circuit and the delay characteristic detection circuit;
A semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 1, wherein a circuit including a ring oscillator is used as the delay characteristic detection circuit.   The semiconductor integrated circuit device according to claim 2, wherein the ring oscillator is formed in the logic circuit, and the frequency of the detection signal is changed according to a change in delay of the logic circuit.   4. The semiconductor integrated circuit device according to claim 1, wherein a circuit including a switched capacitor is used as the first resistance element. 5.   The semiconductor integrated circuit device according to claim 4, wherein the switched capacitor uses a circuit having an inverter having the detection signal as an input and a capacitance element connected to an output. The voltage supply circuit includes a differential amplifier,
One input terminal of the differential amplifier is a combined resistance value of the resistance value of the switched capacitor, the resistance value of the second resistance element connected in parallel with the switched capacitor, and the resistance value of the third resistance element. The voltage divided from the power supply voltage is input,
6. The semiconductor integrated circuit device according to claim 4, wherein a voltage output from the voltage supply circuit is input to the other input terminal of the differential amplifier.

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