JPS6139722A - Delay time stabilizing circuit - Google Patents

Abstract

PURPOSE:To make a delay circuit in a gate circuit constant by obtaining an analog voltage corresponding to a signal delay time of the gate circuit and giving the said voltage as an operating voltage of the gate circuit. CONSTITUTION:A control voltage generating circuit 36 smoothes an output pulse of a comparator 30 to generate DC voltages Vc1, Vc2. The voltages Vc1, Vc2 are inputted to control input terminals c1, c2 of a ring oscillator 20 as control voltages to control the applied voltage. The delay characteristic of inverters 22, 24, 26 depends on the applied voltage, a PLL is constituted by forming a negative feedback through the said loop and each said inverter is controlled to a prescribed delay time independently of fluctuation of a power supply voltage and a temperature. In supplying the control voltages Vc1, Vc2 as the control voltages to a circuit 38 to be controlled, the delay characteristic of the circuit 38 is stabilized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a delay circuit that utilizes the signal delay characteristics of a gate circuit, in which the delay time is made constant regardless of changes in the power supply voltage or mi. related to what was done. .

[Conventional technology]

As a delay circuit that utilizes the delay time of the signal R of the gate circuit,
Some use CMOS inverters.

This is a p-channel MO8-FE as shown in FIG.
The gates of T12 and the n-channel MO8-FET14 are connected to each other, the drains are connected to each other, and the sources are connected to the power supply voltage V. , V88 respectively, input a signal to the gate via the input terminal 13, and input the signal from the drain to the output terminal 1.
5, an inverted signal of the input signal is output.

In this CMOS inverter 10, a delay time occurs between the input and the output. This delay time is determined by the power supply voltage V, as shown in FIG. Depends on 1l-Vss and temperature, the smaller the electric voltage VDD-■ss, the larger the delay time.
The rate of change is also large. Furthermore, the higher the temperature, the longer the delay time. This is because the element conductance changes depending on the power supply voltage (Dll-v88) and temperature.

CM O,S inverter 10 is approximately 3 to 5 μs per piece.
A longer delay time can be obtained by cascading these in multiple stages.

The delay circuit thus obtained is used in a wide range of fields such as oscillation circuits and demodulation circuits.

However, as mentioned above, the dependence on power supply voltage and temperature is so large that it cannot be ignored, and these effects appear in instability of the oscillation cycle, increased distortion in the transmission system, etc. It is difficult to use.

As a way to solve this problem, we use a strictly regulated power supply,
It is also conceivable to buy the elements in stages in a constant temperature bath, but this would be a labor-intensive process.

[Problem that the invention seeks to solve]

The present invention aims to solve one of the drawbacks of the conventional techniques and provide a delay time stabilizing circuit that can reliably stabilize the delay time in a cylinder.

[Means for solving problems]

In this invention, the gate circuit signal ′! ! By obtaining an analog voltage corresponding to the delay time and applying this voltage as the operating voltage of the gate circuit, the delay time of l- to the gate circuit is made constant.

[For production]

According to the solving means of the present invention, even if the delay time attempts to change due to fluctuations in the power supply voltage or temperature, the voltage applied to the gate I-circuit is controlled accordingly, so fluctuations in the delay time are suppressed. It will be done.

[Example 1] An example of the present invention is shown in FIG. This stabilizes the oscillation frequency of the ring oscillator and uses the control voltage used for this stabilization to stabilize other circuits including the inverter.

In FIG. 1, a ring oscillator 20 utilizes the delay characteristics of an inverter, and an odd number of inverters 22, 2
4.26 are connected in series, and the output of the inverter 26 at the final stage is input to the inverter 22 at the first stage. The oscillation frequency of the ring oscillator 20 is determined by the delay time of the oven loop.

The oscillation output of the ring oscillator 20 is waveform-shaped by the inverter 28 and then input to the comparator 30. The comparator 30 compares the frequency and phase of this signal with a reference frequency signal obtained by dividing the output pulse of the oscillator 32 by the frequency divider 34, and outputs a signal with a pulse width corresponding to the difference. .

The control voltage generation circuit 36 smoothes the output pulses of the comparator 30 to generate DC voltages Vc1 and VC2.

These DC voltages VC1, Vc2 are used as voltages to control the ring oscillator 20, and the inverters 22, 24, . ．．
26 control input terminals C1 and c2 to control the applied voltage. Inverter 22.24. ．． As mentioned above, the delay characteristics of 26 depend on the applied voltage, so if the above loop is configured with angular feedback, it becomes a so-called PLL (face-locked loop), so it can be used as a ring oscillator. 20, an extremely stable oscillation frequency (accuracy of reference frequency) can be obtained. In other words, regardless of fluctuations in power supply voltage or temperature, each inverter 22.24.2
6 is controlled to a constant delay time.

The above is a case where this invention is applied to stabilizing the oscillation frequency of a ring oscillator, and the control voltage VC1 obtained here is
, VC2 as a control voltage for another circuit (controlled circuit 38) including the inverter placed in the same environment as the inverters 22, 24, 26 (for example, on the same board of an integrated circuit), this controlled circuit The delay characteristics at 38 can also be stabilized. As the controlled circuit 38, for example, those shown in FIGS. 4 to 7 can be considered.

FIG. 4 shows inverters 40-1, 40-2...

, '40-n are connected in series, a signal is inputted from an input terminal 42, and a delayed output is taken out from an output terminal 44. By controlling the voltages applied to the inverters 71o-i to 40-n using the control voltages Vc1 and Vc2, the delay time can be made constant.

FIG. 5 shows an odd number of inverters 46-1. ....

46-n are connected in series, and the output of the r4-stage inverter 46-n is input to the first-stage inverter 46-1 to output the output terminal 4.
This is a ring oscillator configured as J: which performs oscillation output from 7. Inverter 46-1.
. . , 46-n, each inverter 46-1 . . . , 46-n can be made constant to make the oscillation frequency constant.

FIG. 6 shows an FM demodulation circuit (pulse count detection circuit) which converts the modulated signal input from the input terminal 48 into an even number (four in this case) of inverters 50-1°50=2. ．． 50-
3. Input 50-4 to the circuit connected in cascade, and the final stage 50-
4 is input to an exclusive OR circuit 52, and the output of the exclusive OR circuit 52 is taken out via a low-pass filter 53 and guided to an output terminal 54 as a demodulated signal. Inverter 5 with control voltage MCI, V c, 2
By controlling the applied voltage from 0-1 to 50-4,
Accurate demodulation with less distortion can be performed.

FIG. 7 shows an FM modulation circuit in which modulation signals are input from input terminals 5 and 6 and input to an amplifier 58, and control voltages VC1 and V
C2 is modulated by this input signal, and this modulated control voltage V
An inverter 60 that constitutes a ring oscillator with cl and VC2
-1.60-2. ．． In order to control the applied voltage of 60-3, the final stage applied voltage 60-3 is applied to the output terminal 61.
The FM modulation output is outputted at the same time. By using the control voltages Vcl and VC2, accurate modulation with less variation in carrier frequency can be performed.

By the way, in the circuit shown in FIG. 1, the ring oscillator 20
The inverters 22, 24, 26 constituting the circuit and the inverters constituting the controlled circuit 38 (FIGS. 4 to 7) are as follows:
For example, it is convenient to configure as shown in FIGS. 8 to 13.

The inverter in FIG.
- P channel MO8 for voltage control applied between FET6.6 and power supply voltage VDD, V8S - FET64, n channel MO
8-FET68 are inserted respectively. A signal is input from an input terminal 70 and output from an output terminal 72. The control voltages Vc1 and VC2 (FIG. 1) are input from control input terminals CI and C2. Control voltage Vcl, V
C2 is a voltage symmetrical to the reference potential XLQ 11-'-5-5- (in other words, v cl-v ss = V
DO-V C2). V C1-V ss
=V DO-V If C2 is small, MO8-FET
The voltage applied to the CMOS inverter 61 composed of 62 and 66 becomes larger, the delay time becomes smaller, and VC,1
If −V ss =V DD −V C2, is large, then
The voltage applied to the CMOS inverter 61 becomes smaller and the delay time becomes longer.

- The inverter shown in FIG. 9 is such that the MO8-FET 6.8 in the inverter shown in FIG. 8 is deleted and the application type/pressure of the CMOS inverter is controlled only by the MO8-FET 64. Similarly, it is also possible to delete MO8-FET 64 in the inverter of FIG.

The inverter in Fig. 10 includes control MO3-FFT64,
68 is provided inside the CMOS inverter 61.

The inverter shown in Fig. 11 has two control systems, and MO8-FET 64°68 in Fig.
-FETs 64' and 68' are installed in parallel. In this case, the control voltage V C1' input to MO8-10-FET64', 68'
, V C2' are input manually or through a separate system by providing a separate control voltage generation circuit.

The inverter shown in FIG. 12 has the control elements shown in FIG. 11 connected in series.

The inverter shown in FIG.
8-FET, 68 is inserted, and MO8-FET64 for control is inserted between MO3-FET62 and ffi source V8, o17).
is inserted.

In the above embodiment, the applied voltage was controlled for each inverter, but if multiple stages of inverters are connected, it is reasonable to apply Iil+ control all at once as shown in FIG. That is, the circuit shown in FIG.
4.6B is connected in common and the power supply ■DI) is connected to V88.

[Embodiment 2] Another embodiment of the present invention is shown in FIG. This uses a pulse count detection circuit to stabilize the delay time.

In FIG. 15, a reference signal oscillated from a crystal oscillator 74 is frequency-divided by a frequency divider 76 and then input to a pulse count detection circuit 78. Pulse count detection circuit 78
Inverters 80-1 to 80-4 are connected in series,
The frequency divided signal from the frequency divider 76 is input to the first stage inverter 80-1, and the output of the final stage inverter 80-4 and the frequency divider 7
6 is input to an exclusive OR circuit 82'. The output pulse of the 15 + other OR circuit 82 is the output pulse of the inverter 8
The pulse width varies depending on the delay time of 0-1 to 8 (L-/I).

Since the reference level of the output pulse of the exclusive OR circuit 82 fluctuates, the base tF of the base tF power supply 87 is
ltl lightning pressure V,. f and level matching by comparing and level shifting.

The control voltage generation circuit 88 smoothes the output pulse of the amparator 86 to generate control I lightning voltages c1 and Vc2. These control voltages Vc1 and VC2 are input to control input terminals cl and c2 of inverters 80-1 to 80-4 constituting the pulse count detection circuit 78, and control the applied voltages. The delay characteristics of inverters 80-1 to 80-4 are as follows:
Previous) Since it depends on the applied voltage like di, the above loop returns 0)! By configuring Jζ such that Jζ becomes, a pulse with a constant pulse width is always obtained from the li altruistic OR circuit 82 as a detection output. ') The delay time of each inverter 80-1 to 80-4 is controlled to a constant value regardless of fluctuations in power supply voltage or temperature m.

Control voltage output [control voltage VC1 output from circuit 88
, VC2 are applied to the controlled circuit 38. The controlled circuit 38 is composed of circuits using inverters such as a delay circuit, an oscillation circuit, an FM demodulation circuit, and an FM modulation circuit, as shown in FIGS. 4 to 7 of 6Fi.

Therefore, if the inverter of the controlled circuit 38 is formed in the same IC as the inverters 80-1 to 80-4 of the pulse count detection circuit 78, the inverter in the controlled circuit 38 is connected to the inverter 80 of the pulse count detection circuit 78. -1
Since the signals 80-4 to 80-4 are controlled in common, their delay times are controlled to a constant value. Thereby, the controlled circuit 38 operates stably.

Note that even if d'3 is used in this embodiment, the inverter can be configured as shown in J of FIGS. 8 to 14 above.

〔Effect of the invention〕

According to the present invention, an analog voltage corresponding to the signal delay time of the gate circuit is obtained and this voltage is applied as the operating voltage of the gate circuit, so that a strictly stabilized power supply is required. The delay time can be easily and reliably made constant without using a thermostat or a thermostat.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing a CMOS inverter. FIG. 3 is a characteristic diagram showing power supply voltage-delay time characteristics in the CMOS inverter circuit of FIG. 2. FIGS. 4 to 7 are circuit diagrams showing configuration examples of the controlled circuit 38 in FIG. 1 or FIG. 15. FIGS. 8 to 14 are circuit diagrams showing configuration examples of the inverter in FIG. 1 or FIG. 15. FIG. 15 is a circuit diagram showing an embodiment of the present invention. 20... Ring oscillator, 38... Controlled circuit, 10
゜61...CMOS inverter, 78...Pulse count detection circuit. ■SS

Claims (1)

[Claims] A delay time stabilization circuit characterized in that the delay time in the gate circuit is made constant by obtaining an analog voltage corresponding to the signal delay time of the gate circuit and applying this voltage as the operating voltage of the gate circuit. .