JPH05136664A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To obtain minute delay with high resolution. CONSTITUTION:CMOS gates being a P-channel FET 21 and an N-channel FET 22 are connected to an input terminal 23 and drains are connected to an output terminal 24, the source of the FET 21 is connected to a positive power supply terminal 20 through resistor elements 370, 371, 372... composed of P-channel switchable FETs whose resistance is respectively R0, R1, R2... and the source of the FET 22 is connected to a negative power supply terminal 30 through resistive elements 380, 381, 382... composed of N-channel switchable FETs whose resistance is respectively R0, R1, R2.... The resistor elements 380, 381, 382... are composed of single FET only (Figure a), or series connection of plural FETs (Figure b), or parallel connection of plural FETs (Figure c), or series connection of a passive resistance element and one FET (Figure d). The resistance elements 370, 371, 372... are constituted similarly. Delay setting signals S0, S1... are decoded by a decoder 39.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit having a minute resolution.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional minute resolution variable delay circuit. The delay stages 11, 12 and 13 are connected in series, and each delay stage selects one of two paths branched from the input by the selector 14 and outputs the selected path.
In 1, the buffers 15 and 16 are respectively inserted in two paths, in the delay stage 12, one buffer 16 is inserted in only one path, and in the delay stage 13, only two buffers are connected in series to one path. The buffer 16 is inserted. Propagation delay T _pd of the buffer 16 is twice the propagation delay T _pd of the buffer 15. Each delay stage 11, 12, 13
By selectively controlling the select signal for each selector 14, the path between the input terminal 17 and the output terminal 18 is changed to obtain various delay amounts.

Further, as shown in FIG. 12, each delay stage 11, 1
Only the delay element 19 to one of the two paths at 2, 13 are inserted respectively, the delay amount t _1, t _2, t ₃ of each delay element 19, when a minimum resolution of interest and A, t ₁ = A, t ₂ = 2A, t ₃ = 4A, and when n delay stages are connected, the delay amount t _n of the delay element 19 inserted at the nth stage is 2 ^n-1 A It is said that.

[0004]

In the prior art shown in FIG. 11, the buffers 15 and 1 for giving each delay are provided.
6 has a relatively large delay amount, and the input terminals 17 to
It is difficult to increase the resolution because a large amount of fixed delay is included in the propagation delay amount up to 18. That is, it is difficult to increase the delay resolution because the variation among the respective elements has a great influence as a whole. Especially C
In the case of configuring as an integrated circuit using MOS, it is difficult to increase the resolution as compared with the case of configuring in bipolar.

In the configuration shown in FIG. 12 as well, the propagation delay is used as each delay element 19, but the delay amount of the delay element 19 varies due to variations in manufacturing and variations in power supply voltage and ambient temperature. It is also affected by variations in wiring capacitance. Assuming that the variation in each delay element 19 is α, when the sum of the delay amounts up to the preceding delay stage is minimized due to the variation, and the delay amount received in a certain delay stage is maximized due to the variation. However, the required resolution A must be secured. From such a relationship, in the first delay stage 11, (1 + α) t ₁ = A, and in the second delay stage 12 (1 + α) t ₂ = t ₁ (1-α) +
Therefore, t ₂ = 2A / (1 + α) ² . Further, in the third delay stage 13, (1 + α) t ₃ = (t ₁ + t ₂ ) (1-α) + A, and thus t ₃ = 4A / (1 + α) ³ . When n stages are cascaded, the delay amount is t _n = 2 ^n-1 · A / (1+
α) ⁿ .

For this reason, the variation α has a greater effect toward the final stage, and the delay amount is smaller than the delay amount t _n = 2 ^{n -1} · A in the ideal case. Therefore, the target variable amount is increased accordingly. I can't do that. Normally, α is about 0.6 when it is composed of a CMOS gate array, which is a considerably large value, so that the circuit scale becomes large to obtain the target delay amount, which is not realistic.

[0007]

According to the first aspect of the present invention, one ends of the first and second transistors having different conductivity types are connected to each other, and the connection point is connected to the output terminal. Both input ends of the second transistor are connected to each other and connected to the input terminal, and at least two switchable first resistance elements having different resistance values are provided between the other end of the first transistor and one end of the power supply. Are connected in parallel, and at least two switchable second resistance elements having different resistance values are connected in parallel between the other end of the second transistor and the other end of the power supply. At least one of each of the resistance element and the second resistance element is configured to be selectively turned on by the delay amount setting means.

According to the second aspect of the invention, the first FET having the same conductivity type as the FET at one end of the CMOS is connected between one end of the CMOS and one end of the power supply, and the other end of the CMOS and the other end of the power supply are connected. A second FET having the same conductivity type as the FET at the other end of the CMOS is connected between the CMOS and the first FET
A third FET having the same conductivity type as the first FET is connected between the connection point of the second power supply and the other end of the power supply, and the other end of the CMOS and the second FE are connected.
The fourth FE whose connection point with T has the same conductivity type as that of the second FET
Connected to one end of the power source through T, the first switch is inserted in series with the third FET, the second switch is inserted in series with the fourth FET, and a delay setting means for setting the first and second switches to ON / OFF simultaneously is provided. The second delay stage provided is connected in series to the delay circuit of the first aspect of the invention.

According to the third aspect of the present invention, one ends of the first and second transistors having different conductivity types are connected to each other, both input ends thereof are connected to a common input terminal, and the first and second transistors are connected to each other. The connection point of the two transistors is connected to the output terminal through the inverter, the third transistor is connected in series with the series connection of the first and second transistors, and the variable DC power supply is connected to the input terminal of the third transistor. It is connected.

[0010]

FIG. 1 shows an embodiment of the invention of claim 1. In this embodiment, a MOSFET is used as the transistor, and the p-channel FET 21 is used as the first transistor.
The n-channel FET 22 is used as the second transistor. Both input terminals of the FETs 21 and 22, that is, both gates are connected to each other and are connected to the input terminal 23.
One end of each of 1 and 22 is connected to each other, and the connection point is connected to the output terminal 24.

The p-channel FET 2 is provided between the other end of the FET 21 and the power supply terminal 20 to be connected to the positive side of the power supply 25.
6 and 27 series circuits are connected and p in parallel
The channel FET 28 is connected. A series circuit of n-channel FETs 29 and 31 is connected between the other end of the FET 22 and a power supply terminal 30 to be connected to the negative side of the power supply 25, and an n-channel FET 32 is connected in parallel with the series circuit.
The gates of the FETs 28, 29 and 31 are connected to the select signal terminal 33, and the select signal terminal 33 is connected to the gates of the FETs 26, 27 and 32 via the inverter 34. FETs 21, 22, 26 to 29, 31, 32
Are all of the same on-resistance.

In this structure, when the select signal at the terminal 33 is low level, the FETs 26, 27, 29, 31 are
Is turned off and the FETs 28 and 32 are turned on. Therefore, FE
When the on-resistance of T is r and the load capacitance existing at the output terminal 24 is C, when the select signal is at a low level, FIG.
The configuration of becomes the equivalent circuit shown in FIG. 2A. When the select signal at the terminal 33 is at high level, the FETs 26, 27, 29,
31 is turned on, FETs 28 and 32 are turned off, and the configuration of FIG. 1 becomes an equivalent circuit shown in FIG. 2B. When the select signal is at a low level, one FET is connected between the FETs 21 and 22 and the power supply terminals 20 and 30, and when the select signal is at a high level, there is two between the FETs 21 and 22 and the power supply terminals 20 and 30. They are connected by a series circuit of ON FETs.

When an input signal is applied to the input terminal 23 and it is at a low level, the FET 21 is turned on and the FET 22 is turned off, so that the FET 26, 27 or 28 is fed from the power supply terminal 20.
A current flows to the output terminal 24 through the FET 21, the FET 21 is turned off and the FET 22 is turned on when the input signal is at a high level, and a current flows from the output terminal 24 to the power supply terminal 30 through the FET 29, 31 or 32.

Therefore, when the input signal is input when the select signal is at the low level, the equivalent circuit has two ON resistances r between the input terminal 23 and the output terminal 24 as shown in FIG. 3A.
Are connected in series. When a step pulse is applied to this input terminal 23, the output of the output terminal 24 rises exponentially with a time constant of (r + r) C as shown in FIG. 3B.

On the other hand, when the select signal is at a high level and an input signal is input, the equivalent circuit has three ON resistors r connected in series between the input terminal 23 and the output terminal 24, as shown in FIG. 3C. It will be in a state of being. When a step pulse is applied to this input terminal 23, the output of the output terminal 24 rises exponentially with a time constant of (r + 2r) C as shown in FIG. 3D, and rises later than in the case of FIG. 3A.

Half of level 1 0.5, which gives the maximum output,
Assuming a threshold level, exp (-t / τ) = 0.5
The time from reaching to the threshold level is in the case of Fig. 3A
Is t ₁= 0.69C (r + r), t in the case of FIG. 3C₂=
It becomes 0.69C (2r + r). Thus, the delay time t
₁, T₂, The delay stages shown in FIG. 1 are connected in series.
To select the select signal to be given to each delay stage.
By doing so, various delay amounts can be set.

As shown in FIG. 4, FETs 26, 27, 28
May be connected in parallel and the FETs 24, 31, 32 may be connected in parallel. In this case, two ON resistances r are connected in parallel between the FETs 21 and 22 and the power supply terminals 20 and 30 when the select signal is at a high level.
The delay amount is smaller than when the select signal is low level.

In both FIG. 1 and FIG. 4, the FET 21,
It is only necessary that the same number of FETs are turned on at a low level of the select signal between the power supply terminals 22 and the power supply terminals 20 and 30, and the same number of FETs different from this number are turned on at a high level of the select signal. Is not limited to 1 and 2.
FIG. 5 shows another embodiment of the invention of claim 1, and the portions corresponding to those of FIG. 1 are designated by the same reference numerals. In this example, FET2
1 and the power supply terminal 20 between the p-channel FETs 28 and 35.
And are connected in parallel, and the FET 35 has an ON resistance twice that of the FET 28. FE
The n-channel FETs 32 and 36 are connected in parallel between the T22 and the power supply terminal 30, and the FET 36 has an ON resistance twice that of the FET 32.
It will be easily understood that, in this case as well, different delay amounts can be obtained depending on the low level and the high level of the select signal, as described above. In this example, the FETs 28 and 32 have the same on-resistance and the FETs 35 and 36 have the same on-resistance.
It suffices that the ET 28 and the FET 35 have different on-resistances.

In FIG. 1, FET 28 and FETs 26 and 27 respectively constitute switchable resistance elements having different resistance values, and FET 32 and F
The ETs 29 and 31 constitute switchable resistance elements having different resistance values. Similarly, in FIG. 4, FET 28 and FETs 26 and 27 respectively constitute switchable resistance elements having different resistance values, and FET 32 and FETs 29 and 31 are switchable having different resistance values from each other. A resistance element. Further, in FIG. 5, FET 28 and F
The ET 35 constitutes a switchable resistance element having a different resistance value, and the FET 32 and the FET 36 constitute a switchable resistance element having a different resistance value.

Next, in the above description, with respect to the CMOS, that is, the combination of the transistors 21 and 21, two switchable resistance elements having different resistance values are connected in parallel between both ends of the CMOS and the power supply. Although they are connected, in general, various delay amounts can be selected by providing a plurality of switchable resistance elements that are connected in parallel and have different resistance values.

That is, for example, as shown in FIG.
A plurality of switchable resistance elements 37 ₀ , 3 having different resistance values between the FET 21 and the positive power supply terminal 20 at one end of the series connection of the FETs 21 and 22 forming S.
7 ₁ , 37 _2, ... Are connected in parallel. Further, switchable resistance elements 38 ₀ , 38 ₁ , 38 _2, ... Having different resistance values are connected in parallel between the FET 22 and the negative power supply terminal 30.

In this example, the resistance elements 37 ₀ , 37 ₁ , 37 _2, ... Are each composed of a p-channel FET, and the resistance elements 38 ₀ , 38 ₁ , 38 _{2 ,} .
This is the case where each is composed of channel FETs. F
The resistance element connected between the ET 21 and the power supply terminal 20 corresponds to the resistance element connected between the FET 22 and the power supply terminal 30, that is, 37 ₀ and 38 ₀ , 37.
₁ and 38 ₁ , 37 ₂ and 38 ₂ have the same resistance value, that is, the resistance elements 37 ₀ and 38 ₀ ,
The resistance values of 37 ₁ and 38 ₁ , 37 ₂ and 38 _2, ... Are respectively R ₀ , R ₁ , R ₂ ... As shown in the figure.

The structure of these resistance elements is, for example, resistance elements 38 ₀ , 38 ₁ , 38 ₂ ...
6B, one composed of one n-channel FET as shown in FIG. 6B, one composed of two n-channel FETs connected in series as shown in FIG. 6B, or the one shown in the drawing. Although not provided, it is configured by connecting two or more n-channel FETs in series, or configured by connecting two n-channel FETs in parallel as shown in FIG. 7C, or two or more n-channels. An FET configured by connecting FETs in parallel, or an FET configured by connecting a passive resistance element in series with an n-channel FET as shown in d of FIG. 6B and having different resistance values of the passive resistance element is used. Further, as described with reference to FIG. 5 above, the ON resistances may be different from each other even when the FETs are composed of one FET.

The delay setting signals S ₀ , S ₁ , S ₂ ... Are input to a decoder 39 as a delay setting means and decoded, and one of the output terminals Y ₀ , Y ₁ , Y ₂ ... The output terminal becomes low level. The output terminal _{Y 0, Y 1, Y 2} ... Each resistance element 38 _0,
Of gates of the p-channel FETs of the resistor elements 37 ₀ , 37 ₁ , 37 _2, ... Connected directly to the gates of the n-channel FETs of which 38 ₁ , 38 _2, ... Respectively connected to.

Therefore, for example, the output terminal Y of the decoder 39
_{When 0} goes high, the resistance elements 37 ₀ and 38 ₀ are turned on at the same time, and the other resistance elements remain off. When the output terminal Y ₁ goes high, the resistance element 37 ₁
When 38 ₁ and is turned on at the same time, other resistive elements remain off. In this way, one of the resistance elements 37 ₀ , 37 ₁ , 37 ₂ ... And the corresponding resistance elements 38 ₀ , 38 ₁ , (having the same resistance value) 38 ₀ , 38 ₁ , by the delay setting signal.
One of 38 ₂ ... Turns on at the same time, and the propagation time during which the signal input to the input terminal 23 is output to the output terminal 24 is turned on by the same operation as that described with reference to FIG. Depending on the resistance value of the resistance element, various delay amounts can be set by the states of the delay setting signals S ₀ , S ₁ ...

FIG. 7 shows an embodiment of the invention of claim 2. In this example, a delay stage having another configuration is connected to the output side of the delay circuit shown in FIG. 1, and the FET 4 is provided between the output side of the CMOS including the FETs 21 and 22 and the output terminal 24.
A CMOS 43 composed of 1, 42 has an FET with its gate
It is inserted as the 21, 22 side. The FET 41 is a p-channel FET, and the other end (source) on the side opposite to the connection point of the FET 42 has the same conductivity type as this, that is, a p-channel FET.
Connected to the power supply terminal 20 through 44, and its gate is C
It is connected to the gate of the MOS 43. The source of the other FET 42 of the CMOS 43 has the same conductivity type as that of the FET 42. Therefore, the n-channel FET 45 is connected to the power supply terminal 30.
The gate of the FET 45 is also connected to the gate of the CMOS 43.

A p-channel FET 46 is connected between a connection point between the CMOS 43 and the FET 44 and the power supply terminal 30 via an n-channel FET 47 as a switch. Similarly, the connection point between the CMOS 43 and the FET 45 and the power supply terminal 20
An n-channel FET 48 is connected via a p-channel FET 49 as a switch. FET4
Each gate of 6, 48 is connected to the output terminal 24. The selection signal terminal 33 is the control terminal of the switch 47, that is, FE.
It is connected to the gate of T47, and the output side of the inverter 34 is connected to the control terminal of the switch 49, that is, the gate of the FET 49.

In such a structure, for example, FIG. 8A
As shown in FIG. ₁Voltage input rising from
Force signal V_iIs input, the selection signal at terminal 33 goes low.
In case of level, FETs 28 and 32 are on
Therefore, each of the FETs 21 and 22 and the power supply terminals 20 and 30
The resistance value is small, so that the input of CMOS43
Given voltage V_bIs the ratio as shown by the curve 51 in FIG. 8B.
Fall relatively quickly. Also, when the selection signal of the terminal 33 is low level
Because of this, the switches 47 and 49 are off, and F
The ETs 46 and 48 are connected to the CMOS 43, respectively.
However, the situation is the same as when these are removed.
Therefore, the threshold between the gate and the source of the FET 41, 42
Value is in the middle of high and low levels, for example
As shown by the curve 52 in FIG. 8C, the curve 51 has a high level.
When the value drops from half to half the value at that time t₃To output terminal 2
4 voltage V₀Rises from a low level to a high level.

On the other hand, the selection signal supplied to the terminal 33 has a high level.
In the case of, the FETs 26, 27, 29 and 31 are turned on.
Resistance of FETs 21 and 22 and power supply terminals 20 and 30
Since the value is larger than when the FETs 28 and 32 are on,
The voltage on the input side of the CMOS 43 as shown by the curve 53 of B
Is gradually lower than the curve 51. Also, switch 47,
Since both 49 are on, FET44 and CMOS
The connection point with 43 is grounded through the FET 46, and the output terminal
Child 24 is at time t₁FET46 is low level before
Is in the ON state, and the voltage V at the connection point of the FETs 41 and 46 is
_aIs at a low level. Each of the FETs 44 and 46
The voltage between the power supply terminals 20 and 30 is divided by the impedance.
Is given to the source of the FET 44. Voltage V_bIs a song
It goes down according to the line 53, and with this, the FET44 source voltage
V_aRises as shown by the dotted line in FIG.
CMOS 43 input more than the gate-source threshold
Voltage V_bWhen the FET drops, FET41 turns on and at that time
Point t₃To the output terminal 24 power voltage V₀Is the curve in Figure 8C
Stand up like 54. To turn on FET41 CM
Input voltage V of OS43_bIs below half of the high level
Should be lowered to. Input voltage V of CMOS 43_bBut
When changing as shown by the curve 53, the FETs 46, 4
If 8 is not connected, V_bIs high level half
Point t _FourThen the FET 41 is turned on. Therefore figure
The delay stage 40 including the CMOS 43 is connected to the circuit shown in FIG.
Setting the delay amount when the selection signal is high level.
Point t₃And t_FourCan be increased by a difference ΔT.

In FIG. 7, the delay amount is controlled to either one of two values depending on whether the selection signal is high level or low level.
Resistance elements 37 ₀ , 37 ₁ , 38 ₀ , 3 in the OS stage
If the ON / OFF control for 8 ₁ and the ON / OFF control for the switches 47, 49 are separately performed, the resistance elements 37 ₀ ,
38 ₀ are two can set different delay amount or to or off state to the switch 47 and 49 to the ON state with respect to the on state, the resistance element 37 ₁ and 38 ₁ are a switch 47 and 49 in the state of ON Two other different delay amounts can be set depending on whether they are turned on or off, and a total of four types of delay amounts can be controlled.

More generally, CMs of FETs 21 and 22
The OS stage may have the configuration shown in FIG. 6A, which makes it possible to control more kinds of delay amounts. The delay stage 40 includes transistors 21 and 22.
May be provided before the delay circuit including. FIG. 9A shows an embodiment of the invention of claim 3 and the same reference numerals are attached to the portions corresponding to those in the above description. That is, p channel F
The ET21 and the n-channel FET 22 have respective drains connected to each other, and their both gates are connected to the input terminal 23 so that the CMOS has p-channel FETs 21 and 22. In this example, the n-channel FET 22 has the same conductivity type as that of the CMOS. The FET 55 is connected in series with both ends of the power supply 25. A variable DC power supply 56 is connected to the gate of the FET 55. A variable resistor 57 is used as the variable DC power source 56.
Are connected to both ends of the power supply 25, and the output side of the mover is the output side of the variable DC power supply 56. Also FET2
The connection point between 1 and 22 or the drain is the inverter 58.
Through to the output terminal 24.

In this configuration, when the output of the variable DC power source 56 is changed between 0 and 5 volts, the FET 5
In No. 5, the resistance value between the source and drain changes, that is, the on-resistance changes. As a result, the threshold voltage of the CMOS composed of the FETs 21 and 22 is apparently changed. That is, when, for example, a positive square wave voltage is applied to the input terminal 23, the drain outputs of the FETs 21 and 22, that is, the input voltage of the inverter 58 becomes as shown in FIG. Figure 10
The parameter is the output voltage of the variable DC power supply 56, that is, the value obtained by changing the control voltage V _s from 2 V to 5 V, and if V _s is smaller than 0.2 V, the on-resistance of the FET 55 becomes smaller. The drain output voltage gradually falls and rises gradually, that is, the charging / discharging of the output side capacitance C is significantly slowed down, and the ON resistance of the FET 55 decreases as the control voltage V _s increases. The drain output voltage falls rapidly. If the threshold value of the inverter 58 is 2.5 volts, the falling edge and the rising edge of the drain output voltage change according to the control voltage V _s , that is, V _s.
The delay time can be controlled according to In this example, the control range is about 2 nanoseconds, and the control voltage V _s is
The delay time can be changed in steps of, for example, 50 picoseconds because the delay time can be made smaller than the step of 0.4 volt. That is, the delay control can be performed with extremely high resolution.

A normal gate array is provided with a 2-input NAND circuit. Therefore, by utilizing it, a delay circuit similar to that of FIG. 9A can be configured. That is, FIG. 9B
As shown in, a p-channel FET 59 is connected in parallel with the p-channel FET 21, and the gate of the FET 59 is connected to the output side of the variable DC power supply 56. That is, in a normal gate array, the gates of the FETs 21 and 59 are used as inputs, and the NANDs are formed by the FETs 21 and 59 and the FET 22.
A gate is provided. This NAND
The gate is connected in series with the FET 22 as shown in FIG. 9B.
55 is connected, and the gate of the FET 59 which is one input is connected to the variable DC power supply 56. Since the output voltage V _s of the DC power supply 56 changes only in a positive range such as 0 to 5 V, the FET 59 is always off, and therefore, FIG.
The same operation as that shown in A is performed. 9A and 9B, the FET 55 controlled by the variable DC power supply 56 is
It may be inserted on the 21 side. In this case, the FET 55 is of p channel type. Then, the variable DC power supply 56 is controlled to generate a voltage lower than the voltage of the power supply terminal 20.

The above-described embodiments, that is, the embodiments shown in FIGS. 1, 4, 5, 6, 7, and 9 may be used as independent variable delay circuits, or as shown in FIG.
1, it may be used as one delay stage in the case of multi-stage connection as shown in FIG. Further, although the FET is used as the transistor in the above description, a bipolar type transistor may be used.

[0035]

As described above, according to the first aspect of the present invention, a plurality of switchable resistance elements having different resistance values are used to selectively turn them on so that the charging speed with respect to the load capacitance is increased. , The delay amount is changed by this, but in that case, the on-resistance of the transistor is particularly used as the resistance value, and as a result, each on-resistance has the same value, especially as an integrated circuit. This is easy to configure, and therefore the on-resistance value can be increased and decreased with a certain value fairly accurately, the delay amount can be changed linearly, and the resolution can be improved.

In particular, as shown in FIG. 6A, when a large number of pairs of resistance elements are provided as one delay circuit, a large amount of delay can be set, and when this is configured as one stage of a multi-stage delay circuit, it is small. A large amount of delay can be set by the number of delay stages, and the fixed amount of delay decreases accordingly.
It is possible to configure a variable delay circuit with high resolution and less variation.

According to the invention of claim 2, CM is further cascaded to the input side or the output side of the variable delay circuit of the invention of claim 1.
By providing a delay stage including the OS43 and connecting or disconnecting the FETs 46 and 48 with a switch for the delay stage, it is possible to further increase the kinds of set delay amounts, and also to include the CMOS including the FETs 21 and 22. By controlling the switches 47 and 49 at the same time by the selection signal for the circuit, it is possible to increase the delay amount by one setting signal. Especially, when a plurality of delay stages are provided in series, the delay stage on the subsequent stage side is provided. Is effective for.

According to the invention of claim 3, one transistor is connected in series to a complementary circuit such as CMOS,
By controlling the on-resistance of the transistor with the variable DC power supply, the delay amount can be controlled with an extremely small step, for example, resolution of 50 picoseconds. In the conventional configuration shown in FIG. 12, assuming that a delay of 500 picoseconds can be obtained with one stage of gates, it is necessary to have seven gate delay stages in order to obtain the maximum variable of 3500 picoseconds. If the fixed delay in the selector is 50 picoseconds, the total fixed delay is 350 picoseconds, which is plus or minus 20 times the fixed delay.
%, The maximum variation of this fixed delay is about 100 picoseconds, and it is not possible to obtain a variable delay circuit having a resolution of 50 picoseconds in such a circuit, but as described above. According to the configuration shown in FIG. 9, this can be easily achieved.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of the invention of claim 1;

FIG. 2 is a diagram showing an equivalent circuit of FIG. 1 when a selection signal is given.

3A is a diagram showing an equivalent circuit in a state where an input signal is applied when the selection signal is at a low level, B is a diagram showing a step pulse response thereof, and C is an input signal when the selection signal is at a high level. FIG. 3 is a diagram showing an equivalent circuit in the above-described state, and D is a diagram showing its step pulse response.

FIG. 4 is a connection diagram showing another embodiment of the invention of claim 1;

FIG. 5 is a connection diagram showing still another embodiment of the invention of claim 1;

FIG. 6A is a connection diagram showing a general embodiment of the invention of claim 1, and B is a connection diagram showing each configuration example of the resistance elements 38 ₀ , 38 ₁ , 38 ₂ ...

FIG. 7 is a connection diagram showing an embodiment of the invention of claim 2;

8 is a waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 9 is a connection diagram showing an embodiment of the invention of claim 3;

FIG. 10 is a diagram showing an input waveform of an inverter with respect to the square wave input in the embodiment shown in FIG. 9A, using a gate voltage of FET 55 as a parameter.

FIG. 11 is a connection diagram showing a conventional variable delay circuit.

FIG. 12 is a connection diagram showing another configuration of a conventional variable delay circuit.

Claims (3)

[Claims] 1. A first transistor and a second transistor having different conductivity types, both input terminals of which are connected to each other, connected to an input terminal, and one ends thereof are connected to each other, and a connection point of which is connected to an output terminal. At least two switchable first resistance elements that are connected between the other end of the first transistor and one end of the power supply and have different resistance values, and the other end of the second transistor and the other end of the power supply. And at least two switchable second resistance elements having different resistance values, and delay setting means for setting ON / OFF states of the first resistance element and the second resistance element. A variable delay circuit provided. 2. A first CMOS element inserted between a CMOS, one end of the CMOS, and one end of the power source, which has the same conductivity type as the CMOS FET at the one end.
A second FET inserted between the FET and the other end of the CMOS and the other end of the power source, which has the same conductivity type as the CMOS FET at the other end.
A FET, a connection point between the CMOS and the first FET, and a third FET connected between the other end of the power supply and having the same conductivity type as the first FET, and a connection point between the CMOS and the second FET. A fourth FET connected to the other end of the power source and having the same conductivity type as the second FET, a first switch inserted in series with the third FET, and a second switch connected in series with the fourth FET. A second delay stage including a switch is connected in series to the input terminal or the output terminal, and the first switch and the second switch are simultaneously turned on or off by the delay setting means. The variable delay circuit according to claim 1. 3. A first transistor and a second transistor, both input terminals of which are connected to each other and are connected to an input terminal, one ends thereof are connected to each other, and the connection point is connected to an output terminal, the first and second transistors having different conductivity types. A third transistor inserted in series between both ends of the first and second transistors and both ends of the power source, a variable DC power source connected to an input terminal of the third transistor, and the first and second A variable delay circuit comprising: an inverter having an input side connected to a connection point of a transistor and an output side connected to an output terminal.